From 22c5b3e1dc4e3cf7de3f73ebbf5b59542f207f4b Mon Sep 17 00:00:00 2001 From: Josh Rahm Date: Sun, 17 Nov 2024 23:04:11 -0700 Subject: System clock is sort of working. It appears the frequency divider does not work. I've followed the data sheet, but no matter what I set the frequency divider to it appears to not work. It's possible maybe the GPIO is using an un-divided clock, but I'm not sure. Also the 32khz clock does not work I think. It might be an issue with the board. The waveform is jagged and looks awful. But I can switch from the HSE to the PLL. --- linker/ls.ld | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'linker') diff --git a/linker/ls.ld b/linker/ls.ld index 6f11aee..4ac7dc6 100644 --- a/linker/ls.ld +++ b/linker/ls.ld @@ -30,6 +30,12 @@ SECTIONS *(.srodata.*); } > flash AT>flash + .clock_change_listeners : ALIGN(0x04) { + CLOCK_CHANGE_LISTENERS_START = .; + KEEP(*(.clock_change_listeners)); + CLOCK_CHANGE_LISTENERS_END = .; + } > flash AT>flash + ISR_VECTOR_IN_FLASH = LOADADDR(.isr_vector); .isr_vector : ALIGN(0x04) { ISR_VECTOR_START = .; -- cgit