summaryrefslogtreecommitdiff
path: root/src/Language/Fiddle/Ast/Internal/SyntaxTree.hs
diff options
context:
space:
mode:
Diffstat (limited to 'src/Language/Fiddle/Ast/Internal/SyntaxTree.hs')
-rw-r--r--src/Language/Fiddle/Ast/Internal/SyntaxTree.hs13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/Language/Fiddle/Ast/Internal/SyntaxTree.hs b/src/Language/Fiddle/Ast/Internal/SyntaxTree.hs
index 0d0bc32..b597a25 100644
--- a/src/Language/Fiddle/Ast/Internal/SyntaxTree.hs
+++ b/src/Language/Fiddle/Ast/Internal/SyntaxTree.hs
@@ -18,6 +18,7 @@ module Language.Fiddle.Ast.Internal.SyntaxTree
FieldSpan (..),
QRegMetadata (..),
QBitsMetadata (..),
+ RegSz(..),
-- Witness Types
Witness (..),
-- AST Types
@@ -50,6 +51,7 @@ module Language.Fiddle.Ast.Internal.SyntaxTree
EnumConstantDecl (..),
PackageBody (..),
-- Helper Functions
+ regSzToBits,
mapDirected,
mapDirectedM,
asDirected,
@@ -105,6 +107,15 @@ deriving instance
(FromJSON (When s (FieldSpan Bytes))) =>
FromJSON (QRegMetadata s)
+data RegSz = RegSz8 | RegSz16 | RegSz32 | RegSz64
+ deriving (Eq, Ord, Show, Enum, Generic, ToJSON, FromJSON)
+
+regSzToBits :: RegSz -> N Bits
+regSzToBits RegSz8 = 8
+regSzToBits RegSz16 = 16
+regSzToBits RegSz32 = 32
+regSzToBits RegSz64 = 64
+
data QBitsMetadata (checkStage :: Bool) where
QBitsMetadata ::
{ bitsSpan :: When checkStage (FieldSpan Bits),
@@ -520,7 +531,7 @@ data ObjTypeDecl stage f a where
-- doesn't exist.
regIdent :: Guaranteed (stage .>= Qualified) (Identifier f a),
-- | Size of the register.
- regSize :: Expression Bits stage f a,
+ regSize :: Variant (stage .>= Qualified) RegSz (Expression Bits stage f a),
-- | Optional register body.
regBody :: Maybe (RegisterBody stage f a),
-- | Annotation for the register declaration.