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| author | ZyX <kp-pav@yandex.ru> | 2017-11-06 20:23:35 +0300 |
|---|---|---|
| committer | ZyX <kp-pav@yandex.ru> | 2017-11-06 20:23:35 +0300 |
| commit | 24a353364d6d186d528009fd0bb603d87183cf35 (patch) | |
| tree | a4070dc00731475d6bbdd3c84e61806b33802f7a /runtime/indent/verilog.vim | |
| parent | f2660bee6aca35be3d0ddb1d225784476c13cd27 (diff) | |
| parent | 946c2a8ee85830c543e389724575ae531e89b170 (diff) | |
| download | rneovim-24a353364d6d186d528009fd0bb603d87183cf35.tar.gz rneovim-24a353364d6d186d528009fd0bb603d87183cf35.tar.bz2 rneovim-24a353364d6d186d528009fd0bb603d87183cf35.zip | |
Merge branch 'master' into expression-parser
Diffstat (limited to 'runtime/indent/verilog.vim')
| -rw-r--r-- | runtime/indent/verilog.vim | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/runtime/indent/verilog.vim b/runtime/indent/verilog.vim index ecca462636..6222dc341f 100644 --- a/runtime/indent/verilog.vim +++ b/runtime/indent/verilog.vim @@ -1,10 +1,12 @@ " Language: Verilog HDL -" Maintainer: Chih-Tsun Huang <cthuang@larc.ee.nthu.edu.tw> -" Last Change: 2011 Dec 10 by Thilo Six -" URL: http://larc.ee.nthu.edu.tw/~cthuang/vim/indent/verilog.vim +" Maintainer: Chih-Tsun Huang <cthuang@cs.nthu.edu.tw> +" Last Change: 2017 Feb 24 by Chih-Tsun Huang +" URL: http://www.cs.nthu.edu.tw/~cthuang/vim/indent/verilog.vim " " Credits: " Suggestions for improvement, bug reports by +" Takuya Fujiwara <tyru.exe@gmail.com> +" Thilo Six <debian@Xk2c.de> " Leo Butlero <lbutler@brocade.com> " " Buffer Variables: @@ -38,7 +40,7 @@ function GetVerilogIndent() if exists('b:verilog_indent_width') let offset = b:verilog_indent_width else - let offset = &sw + let offset = shiftwidth() endif if exists('b:verilog_indent_modules') let indent_modules = offset |