diff options
| author | James McCoy <jamessan@jamessan.com> | 2016-06-20 10:37:19 -0400 |
|---|---|---|
| committer | James McCoy <jamessan@jamessan.com> | 2016-07-08 01:43:36 -0400 |
| commit | ea18b4a60f3b89d261c46b030d3d026ddad864bb (patch) | |
| tree | e853d1a1306f9b636d4eb183487a4458283e249f /runtime/syntax/vhdl.vim | |
| parent | 1f54d253e169fbc483cc485f9b3092a8da1f62db (diff) | |
| download | rneovim-ea18b4a60f3b89d261c46b030d3d026ddad864bb.tar.gz rneovim-ea18b4a60f3b89d261c46b030d3d026ddad864bb.tar.bz2 rneovim-ea18b4a60f3b89d261c46b030d3d026ddad864bb.zip | |
vim-patch:77cdfd1
Updated runtime files.
https://github.com/vim/vim/commit/77cdfd10382e01cc51f4ba1a9177032351843151
Ignore changes to:
* doc/channel.txt, doc/eval.txt: Channel related docs
* doc/options.txt: GUI related docs
* doc/tags: Generated at build time
* doc/todo.txt: Irrelevant for Neovim
Diffstat (limited to 'runtime/syntax/vhdl.vim')
| -rw-r--r-- | runtime/syntax/vhdl.vim | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/runtime/syntax/vhdl.vim b/runtime/syntax/vhdl.vim index 044ef83d17..32503823ee 100644 --- a/runtime/syntax/vhdl.vim +++ b/runtime/syntax/vhdl.vim @@ -54,37 +54,37 @@ syn match vhdlError "\<else\s\+if\>" " Types and type qualifiers " Predefined standard VHDL types -syn match vhdlType "bit[\']*" -syn match vhdlType "boolean[\']*" -syn match vhdlType "natural[\']*" -syn match vhdlType "positive[\']*" -syn match vhdlType "integer[\']*" -syn match vhdlType "real[\']*" -syn match vhdlType "time[\']*" - -syn match vhdlType "bit_vector[\']*" -syn match vhdlType "boolean_vector[\']*" -syn match vhdlType "integer_vector[\']*" -syn match vhdlType "real_vector[\']*" -syn match vhdlType "time_vector[\']*" - -syn match vhdlType "character[\']*" -syn match vhdlType "string[\']*" +syn match vhdlType "\<bit\>\'\=" +syn match vhdlType "\<boolean\>\'\=" +syn match vhdlType "\<natural\>\'\=" +syn match vhdlType "\<positive\>\'\=" +syn match vhdlType "\<integer\>\'\=" +syn match vhdlType "\<real\>\'\=" +syn match vhdlType "\<time\>\'\=" + +syn match vhdlType "\<bit_vector\>\'\=" +syn match vhdlType "\<boolean_vector\>\'\=" +syn match vhdlType "\<integer_vector\>\'\=" +syn match vhdlType "\<real_vector\>\'\=" +syn match vhdlType "\<time_vector\>\'\=" + +syn match vhdlType "\<character\>\'\=" +syn match vhdlType "\<string\>\'\=" "syn keyword vhdlType severity_level -syn match vhdlType "line[\']*" -syn match vhdlType "text[\']*" +syn keyword vhdlType line +syn keyword vhdlType text " Predefined standard IEEE VHDL types -syn match vhdlType "std_ulogic[\']*" -syn match vhdlType "std_logic[\']*" -syn match vhdlType "std_ulogic_vector[\']*" -syn match vhdlType "std_logic_vector[\']*" -syn match vhdlType "unresolved_signed[\']*" -syn match vhdlType "unresolved_unsigned[\']*" -syn match vhdlType "u_signed[\']*" -syn match vhdlType "u_unsigned[\']*" -syn match vhdlType "signed[\']*" -syn match vhdlType "unsigned[\']*" +syn match vhdlType "\<std_ulogic\>\'\=" +syn match vhdlType "\<std_logic\>\'\=" +syn match vhdlType "\<std_ulogic_vector\>\'\=" +syn match vhdlType "\<std_logic_vector\>\'\=" +syn match vhdlType "\<unresolved_signed\>\'\=" +syn match vhdlType "\<unresolved_unsigned\>\'\=" +syn match vhdlType "\<u_signed\>\'\=" +syn match vhdlType "\<u_unsigned\>\'\=" +syn match vhdlType "\<signed\>\'\=" +syn match vhdlType "\<unsigned\>\'\=" " array attributes |