diff options
Diffstat (limited to 'runtime/doc/indent.txt')
| -rw-r--r-- | runtime/doc/indent.txt | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/runtime/doc/indent.txt b/runtime/doc/indent.txt index afa88fd37f..6e96d9b816 100644 --- a/runtime/doc/indent.txt +++ b/runtime/doc/indent.txt @@ -718,7 +718,7 @@ also left unindented because continue statements are also used for purposes other than ending a do loop. Programs such as Tidy can convert structured do/continue loops to the do/enddo form. Do loops of the do/enddo variety can be indented. If you use only structured loops of the do/enddo form, you should -declare this by setting the fortran_do_enddo variable in your .vimrc as +declare this by setting the fortran_do_enddo variable in your vimrc as follows > let fortran_do_enddo=1 @@ -737,7 +737,7 @@ The indenting of program units (subroutines, functions, modules, and program blocks) is enabled by default but can be suppressed if a lighter, screen-width preserving indent style is desired. To suppress the indenting of program units for all fortran files set the global fortran_indent_less variable in -your .vimrc as follows > +your vimrc as follows > let fortran_indent_less=1 @@ -969,7 +969,7 @@ VERILOG *ft-verilog-indent* General block statements such as if, for, case, always, initial, function, specify and begin, etc., are indented. The module block statements (first level blocks) are not indented by default. you can turn on the indent with -setting a variable in the .vimrc as follows: > +setting a variable in the vimrc as follows: > let b:verilog_indent_modules = 1 @@ -1017,7 +1017,7 @@ To turn this off, add > let g:vhdl_indent_genportmap = 0 -to the .vimrc file, which causes the previous alignment example to change: > +to the vimrc file, which causes the previous alignment example to change: > ENTITY sync IS PORT ( @@ -1041,7 +1041,7 @@ To turn this off, add > let g:vhdl_indent_rhsassign = 0 -to the .vimrc file, which causes the previous alignment example to change: > +to the vimrc file, which causes the previous alignment example to change: > sig_out <= (bus_a(1) AND (sig_b OR sig_c)) OR |