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-rw-r--r--runtime/syntax/vhdl.vim34
1 files changed, 17 insertions, 17 deletions
diff --git a/runtime/syntax/vhdl.vim b/runtime/syntax/vhdl.vim
index efcb840284..06fc2e795e 100644
--- a/runtime/syntax/vhdl.vim
+++ b/runtime/syntax/vhdl.vim
@@ -1,9 +1,9 @@
" Vim syntax file
" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language]
-" Maintainer: Daniel Kho <daniel.kho@tauhop.com>
+" Maintainer: Daniel Kho <daniel.kho@logik.haus>
" Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
-" Last Changed: 2018 May 06 by Daniel Kho
+" Last Changed: 2020 Apr 04 by Daniel Kho
" quit when a syntax file was already loaded
if exists("b:current_syntax")
@@ -16,10 +16,10 @@ set cpo&vim
" case is not significant
syn case ignore
-" VHDL keywords
-syn keyword vhdlStatement access after alias all assert
+" VHDL 1076-2019 keywords
+syn keyword vhdlStatement access after alias all
syn keyword vhdlStatement architecture array attribute
-syn keyword vhdlStatement assume assume_guarantee
+syn keyword vhdlStatement assert assume
syn keyword vhdlStatement begin block body buffer bus
syn keyword vhdlStatement case component configuration constant
syn keyword vhdlStatement context cover
@@ -34,20 +34,19 @@ syn keyword vhdlStatement map
syn keyword vhdlStatement new next null
syn keyword vhdlStatement of on open others out
syn keyword vhdlStatement package port postponed procedure process pure
-syn keyword vhdlStatement parameter property protected
+syn keyword vhdlStatement parameter property protected private
syn keyword vhdlStatement range record register reject report return
-syn keyword vhdlStatement release restrict restrict_guarantee
-syn keyword vhdlStatement select severity signal shared
-syn keyword vhdlStatement subtype
+syn keyword vhdlStatement release restrict
+syn keyword vhdlStatement select severity signal shared subtype
syn keyword vhdlStatement sequence strong
syn keyword vhdlStatement then to transport type
syn keyword vhdlStatement unaffected units until use
-syn keyword vhdlStatement variable
-" VHDL-2017 interface
-syn keyword vhdlStatement view
-syn keyword vhdlStatement vmode vprop vunit
+syn keyword vhdlStatement variable view
+syn keyword vhdlStatement vpkg vmode vprop vunit
syn keyword vhdlStatement wait when while with
-syn keyword vhdlStatement note warning error failure
+
+" VHDL predefined severity levels
+syn keyword vhdlAttribute note warning error failure
" Linting of conditionals.
syn match vhdlStatement "\<\(if\|else\)\>"
@@ -124,7 +123,7 @@ syn match vhdlAttribute "\'succ"
syn match vhdlAttribute "\'val"
syn match vhdlAttribute "\'image"
syn match vhdlAttribute "\'value"
-" VHDL-2017 interface attribute
+" VHDL-2019 interface attribute
syn match vhdlAttribute "\'converse"
syn keyword vhdlBoolean true false
@@ -167,7 +166,7 @@ syn match vhdlOperator "=\|\/=\|>\|<\|>="
syn match vhdlOperator "<=\|:="
syn match vhdlOperator "=>"
-" VHDL-2017 concurrent signal association (spaceship) operator
+" VHDL-202x concurrent signal association (spaceship) operator
syn match vhdlOperator "<=>"
" VHDL-2008 conversion, matching equality/non-equality operators
@@ -188,7 +187,7 @@ syn match vhdlError "\(<\)[&+\-\/\\]\+"
syn match vhdlError "[>=&+\-\/\\]\+\(<\)"
" Covers most operators
" support negative sign after operators. E.g. q<=-b;
-" Supports VHDL-2017 spaceship (concurrent simple signal association).
+" Supports VHDL-202x spaceship (concurrent simple signal association).
syn match vhdlError "\(<=\)[<=&+\*\\?:]\+"
syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)"
syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+"
@@ -265,4 +264,5 @@ let b:current_syntax = "vhdl"
let &cpo = s:cpo_save
unlet s:cpo_save
+
" vim: ts=8