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author | Josh Rahm <joshuarahm@gmail.com> | 2018-01-23 23:14:31 -0700 |
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committer | Josh Rahm <joshuarahm@gmail.com> | 2018-01-23 23:14:31 -0700 |
commit | 7aa10db46c13ad8adc88aadff39b8cf6b15db09d (patch) | |
tree | b1e34a6703de33250b0bd97d34999b687a36a00f /01-system-clock/src/gpio.c | |
parent | acd8afd83da625d36ef39bc01717f29f3b689952 (diff) | |
download | stm32l4-7aa10db46c13ad8adc88aadff39b8cf6b15db09d.tar.gz stm32l4-7aa10db46c13ad8adc88aadff39b8cf6b15db09d.tar.bz2 stm32l4-7aa10db46c13ad8adc88aadff39b8cf6b15db09d.zip |
rename folders to give notion of progression
Diffstat (limited to '01-system-clock/src/gpio.c')
-rw-r--r-- | 01-system-clock/src/gpio.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/01-system-clock/src/gpio.c b/01-system-clock/src/gpio.c new file mode 100644 index 0000000..2404398 --- /dev/null +++ b/01-system-clock/src/gpio.c @@ -0,0 +1,37 @@ +#include "gpio.h" +#include "rcc.h" + +/* + * Sets the mode of a pin on a gpio por. + */ +void set_gpio_pin_mode( + __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode) +{ + /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */ + gpio_port->mode_r &= ~(0x03 << pin * 2); + gpio_port->mode_r |= mode << pin * 2; +} + +gpio_output_pin_t set_gpio_pin_output( + __IO gpio_port_t* gpio_port, gpio_pin_t pin) +{ + set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT); + + return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin}; +} + +void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff) +{ + if (onoff) { + pin.gpio_port->output_r |= 1 << pin.pin; + } else { + pin.gpio_port->output_r &= ~(1 << pin.pin); + } +} + +#define GPIO_PORTS_BASE_ADDR ((uint32_t)0x48000000) +__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) +{ + RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ + return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); +} |