Add new GPIO subsystem.

This gpio subsystem keeps track of the GPIO pins which
have been reserved and takes care of the housekeeping
with keeping them running.

This gpio subsystem also knows which alternate functions
belong to which pins, so it can automatically configure
the pins for the alternate functions.

6 files changed, 157 insertions, 281 deletions

diff --git a/02-usart/include/arch/arm/arch.h b/02-usart/include/arch/arm/arch.h
index 42b33bb..22d0987 100644
--- a/02-usart/include/arch/arm/arch.h
+++ b/02-usart/include/arch/arm/arch.h
@@ -20,6 +20,7 @@
 #define GPIOA_BASE (0x48000000)
 #define GPIOB_BASE (0x48000400)
 #define GPIOC_BASE (0x48000800)
+#define GPIOH_BASE (0x48001C00)
 
 #define SRAM1_BASE (0x20000000)
 #define SRAM2_BASE (0x2000C000)
diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h b/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h
index 20acf71..944d725 100644
--- a/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h
+++ b/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h
@@ -7,320 +7,60 @@
 #include <stdint.h>
 
 /*
- * Possible GPIO ports.
- */
-typedef enum {
-  GPIO_PORT_A = 0,
-  GPIO_PORT_B = 1,
-  GPIO_PORT_C = 2,
-  GPIO_PORT_D = 3
-} gpio_port_number_t;
-
-/*
  * Structure defining the layout of the layout of the GPIO registers on the
  * stm32l432 development board.
  */
 typedef struct GPIO_PORT_STR {
   /* Mode of each GPIO pin for this GPIO port. */
-#define gpio_mode0   (3 << 0)
-#define gpio_mode1   (3 << 2)
-#define gpio_mode2   (3 << 4)
-#define gpio_mode3   (3 << 6)
-#define gpio_mode4   (3 << 8)
-#define gpio_mode5   (3 << 10)
-#define gpio_mode6   (3 << 12)
-#define gpio_mode7   (3 << 14)
-#define gpio_mode8   (3 << 16)
-#define gpio_mode9   (3 << 18)
-#define gpio_mode10  (3 << 20)
-#define gpio_mode11  (3 << 22)
-#define gpio_mode12  (3 << 24)
-#define gpio_mode13  (3 << 26)
-#define gpio_mode14  (3 << 28)
-#define gpio_mode15  (3 << 30)
+#define gpio_mode_n(off) (3 << ((off) * 2))
   __IO uint32_t mode_r;   /* Mode register */
  
   /* Output type for each gpio pin in this port. */
-#define gpio_otype0   (1 <<  0)
-#define gpio_otype1   (1 <<  1)
-#define gpio_otype2   (1 <<  2)
-#define gpio_otype3   (1 <<  3)
-#define gpio_otype4   (1 <<  4)
-#define gpio_otype5   (1 <<  5)
-#define gpio_otype6   (1 <<  6)
-#define gpio_otype7   (1 <<  7)
-#define gpio_otype8   (1 <<  8)
-#define gpio_otype9   (1 <<  9)
-#define gpio_otype10  (1 << 10)
-#define gpio_otype11  (1 << 11)
-#define gpio_otype12  (1 << 12)
-#define gpio_otype13  (1 << 13)
-#define gpio_otype14  (1 << 14)
-#define gpio_otype15  (1 << 15)
+#define gpio_otype_n(off) (1 << (off))
   __IO uint32_t otype_r;
 
   /* GPIO port output speed. */
-#define gpio_ospeed0   (3 << 0)
-#define gpio_ospeed1   (3 << 2)
-#define gpio_ospeed2   (3 << 4)
-#define gpio_ospeed3   (3 << 6)
-#define gpio_ospeed4   (3 << 8)
-#define gpio_ospeed5   (3 << 10)
-#define gpio_ospeed6   (3 << 12)
-#define gpio_ospeed7   (3 << 14)
-#define gpio_ospeed8   (3 << 16)
-#define gpio_ospeed9   (3 << 18)
-#define gpio_ospeed10  (3 << 20)
-#define gpio_ospeed11  (3 << 22)
-#define gpio_ospeed12  (3 << 24)
-#define gpio_ospeed13  (3 << 26)
-#define gpio_ospeed14  (3 << 28)
-#define gpio_ospeed15  (3 << 30)
+#define gpio_ospeed_n(off) (3 << ((off) * 2))
   __IO uint32_t ospeed_r;
 
   /* GPIO port pull-up/pull-down register */
-#define gpio_pupd0   (3 << 0)
-#define gpio_pupd1   (3 << 2)
-#define gpio_pupd2   (3 << 4)
-#define gpio_pupd3   (3 << 6)
-#define gpio_pupd4   (3 << 8)
-#define gpio_pupd5   (3 << 10)
-#define gpio_pupd6   (3 << 12)
-#define gpio_pupd7   (3 << 14)
-#define gpio_pupd8   (3 << 16)
-#define gpio_pupd9   (3 << 18)
-#define gpio_pupd10  (3 << 20)
-#define gpio_pupd11  (3 << 22)
-#define gpio_pupd12  (3 << 24)
-#define gpio_pupd13  (3 << 26)
-#define gpio_pupd14  (3 << 28)
-#define gpio_pupd15  (3 << 30)
+#define gpio_pupd_n(off) (3 << ((off) * 2))
   __IO uint32_t pupd_r;
 
   /* GPIO port input data register. */
-#define gpio_idr0   (1 <<  0)
-#define gpio_idr1   (1 <<  1)
-#define gpio_idr2   (1 <<  2)
-#define gpio_idr3   (1 <<  3)
-#define gpio_idr4   (1 <<  4)
-#define gpio_idr5   (1 <<  5)
-#define gpio_idr6   (1 <<  6)
-#define gpio_idr7   (1 <<  7)
-#define gpio_idr8   (1 <<  8)
-#define gpio_idr9   (1 <<  9)
-#define gpio_idr10  (1 << 10)
-#define gpio_idr11  (1 << 11)
-#define gpio_idr12  (1 << 12)
-#define gpio_idr13  (1 << 13)
-#define gpio_idr14  (1 << 14)
-#define gpio_idr15  (1 << 15)
+#define gpio_idr_n(off) (1 << (off))
   __IO uint32_t id_r;
 
   /* GPIO port output data register. */
-#define gpio_odr0   (1 <<  0)
-#define gpio_odr1   (1 <<  1)
-#define gpio_odr2   (1 <<  2)
-#define gpio_odr3   (1 <<  3)
-#define gpio_odr4   (1 <<  4)
-#define gpio_odr5   (1 <<  5)
-#define gpio_odr6   (1 <<  6)
-#define gpio_odr7   (1 <<  7)
-#define gpio_odr8   (1 <<  8)
-#define gpio_odr9   (1 <<  9)
-#define gpio_odr10  (1 << 10)
-#define gpio_odr11  (1 << 11)
-#define gpio_odr12  (1 << 12)
-#define gpio_odr13  (1 << 13)
-#define gpio_odr14  (1 << 14)
-#define gpio_odr15  (1 << 15)
-  __IO uint32_t output_r;
+#define gpio_odr_n(off) (1 << (off))
+  __IO uint32_t od_r;
 
   /* GPIO port bit set/reset register. */
-#define gpio_bs0   (1 <<  0)
-#define gpio_bs1   (1 <<  1)
-#define gpio_bs2   (1 <<  2)
-#define gpio_bs3   (1 <<  3)
-#define gpio_bs4   (1 <<  4)
-#define gpio_bs5   (1 <<  5)
-#define gpio_bs6   (1 <<  6)
-#define gpio_bs7   (1 <<  7)
-#define gpio_bs8   (1 <<  8)
-#define gpio_bs9   (1 <<  9)
-#define gpio_bs10  (1 << 10)
-#define gpio_bs11  (1 << 11)
-#define gpio_bs12  (1 << 12)
-#define gpio_bs13  (1 << 13)
-#define gpio_bs14  (1 << 14)
-#define gpio_bs15  (1 << 15)
-#define gpio_br0   (1 << 16)
-#define gpio_br1   (1 << 17)
-#define gpio_br2   (1 << 18)
-#define gpio_br3   (1 << 19)
-#define gpio_br4   (1 << 20)
-#define gpio_br5   (1 << 21)
-#define gpio_br6   (1 << 22)
-#define gpio_br7   (1 << 23)
-#define gpio_br8   (1 << 24)
-#define gpio_br9   (1 << 25)
-#define gpio_br10  (1 << 26)
-#define gpio_br11  (1 << 27)
-#define gpio_br12  (1 << 28)
-#define gpio_br13  (1 << 29)
-#define gpio_br14  (1 << 30)
-#define gpio_br15  (1 << 31)
+#define gpio_bs_n(off) (1 << (off))
+#define gpio_br_n(off) (1 << (off))
   __IO uint32_t bsr_r;
 
   /* GPIO port configuration lock register. */
-#define gpio_lck0   (1 <<  0)
-#define gpio_lck1   (1 <<  1)
-#define gpio_lck2   (1 <<  2)
-#define gpio_lck3   (1 <<  3)
-#define gpio_lck4   (1 <<  4)
-#define gpio_lck5   (1 <<  5)
-#define gpio_lck6   (1 <<  6)
-#define gpio_lck7   (1 <<  7)
-#define gpio_lck8   (1 <<  8)
-#define gpio_lck9   (1 <<  9)
-#define gpio_lck10  (1 << 10)
-#define gpio_lck11  (1 << 11)
-#define gpio_lck12  (1 << 12)
-#define gpio_lck13  (1 << 13)
-#define gpio_lck14  (1 << 14)
-#define gpio_lck15  (1 << 15)
+#define gpio_lck_n(off) (1 << (off))
 #define gpio_lckk   (1 << 16)
   __IO uint32_t lck_r;
 
   /* Alternate function low-register. */
-#define gpio_afsel0 (0xF <<  0)
-#define gpio_afsel1 (0xF <<  4)
-#define gpio_afsel2 (0xF <<  8)
-#define gpio_afsel3 (0xF << 12)
-#define gpio_afsel4 (0xF << 16)
-#define gpio_afsel5 (0xF << 20)
-#define gpio_afsel6 (0xF << 24)
-#define gpio_afsel7 (0xF << 28)
+#define gpio_afsel_n(off) (0xf << ((off) * 4))
   __IO uint32_t af_rl;
-
   /* Alternate function high-register. */
-#define gpio_afsel8  (0xF <<  0)
-#define gpio_afsel9  (0xF <<  4)
-#define gpio_afsel10 (0xF <<  8)
-#define gpio_afsel11 (0xF << 12)
-#define gpio_afsel12 (0xF << 16)
-#define gpio_afsel13 (0xF << 20)
-#define gpio_afsel14 (0xF << 24)
-#define gpio_afsel15 (0xF << 28)
   __IO uint32_t af_rh;
-} PACKED gpio_port_t;
 
-/*
- * Enum defining the PINs in a GPIO port. Each port has 16 pins to use in
- * the stm32l432.
- */
-typedef enum GPIO_PIN_ENUM {
-  PIN_0 = 0,
-  PIN_1 = 1,
-  PIN_2 = 2,
-  PIN_3 = 3,
-  PIN_4 = 4,
-  PIN_5 = 5,
-  PIN_6 = 6,
-  PIN_7 = 7,
-  PIN_8 = 8,
-  PIN_9 = 9,
-  PIN_10 = 10,
-  PIN_11 = 11,
-  PIN_12 = 12,
-  PIN_13 = 13,
-  PIN_14 = 14,
-  PIN_15 = 15
-} gpio_pin_t;
+  /* GPIO port bit register. */
+#define gpio_br_n(off) (1 << (off))
+  __IO uint32_t br_r;
 
-/* Alternate function number. */
-typedef enum {
-  AFN_0 = 0,
-  AFN_1 = 1,
-  AFN_2 = 2,
-  AFN_3 = 3,
-  AFN_4 = 4,
-  AFN_5 = 5,
-  AFN_6 = 6,
-  AFN_7 = 7,
-  AFN_8 = 8,
-  AFN_9 = 9,
-  AFN_10 = 10,
-  AFN_11 = 11,
-  AFN_12 = 12,
-  AFN_13 = 13,
-  AFN_14 = 14,
-  AFN_15 = 15
-} alternate_function_t;
-
-/*
- * Enum defining the pin modes that are possible.
- */
-typedef enum {
-  MODE_INPUT = 0,
-  MODE_OUTPUT = 1,
-  MODE_ALTERNATE = 2,
-  MODE_ANALOG = 3
-} gpio_pin_mode_t;
-
-/*
- * Enum defining the pin speeds that are possible.
- */
-typedef enum {
-  SPEED_2MHZ = 0,
-  SPEED_10MHZ = 1,
-  SPEED_50MHZ = 3,
-} speed_t;
-
-/*
- * Structure defining an OUTPUT pin. Structurally equivalent to the input pin,
- * but can be used in a slightly type-safe manner.
- */
-typedef struct {
-  __IO gpio_port_t* gpio_port;
-  gpio_pin_t pin;
-} gpio_output_pin_t;
-
-/*
- * Sets the mode on a GPIO pin.
- *
- * gpio_port: the gpio port to use.
- * pin: the pin number to set.
- * pin_mode: the mode to set the pin to.
- */
-void set_gpio_pin_mode(
-    __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode);
-
-/*
- * Sets the given GPIO pin to be an output pin. Returns an output_pin struct
- * corresponding to
- */
-gpio_output_pin_t set_gpio_pin_output(
-    __IO gpio_port_t* gpio_port, gpio_pin_t pin);
-
-/*
- * Sets an output pin on or off.
- *
- * pin: the pin to toggle.
- * onoff: 0 for off, non-zero of on.
- */
-void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff);
-
-#define pin_on(p) set_gpio_output_pin(p, 1)
-
-#define pin_off(p) set_gpio_output_pin(p, 0)
-
-/*
- * Enables a GPIO port and returns a reference to the register definition
- * of that GPIO port.
- */
-__IO gpio_port_t* enable_gpio(gpio_port_number_t number);
+  /* Analog switch control register. */
+#define gpio_asc_n(off) (1 << (off))
+  __IO uint32_t asc_r;
+} PACKED gpio_port_config_t;
 
-/* Sets the alternate function for a GPIO pin. */
-void set_gpio_alternate_function(
-    __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn);
+static_assert(
+    offsetof(gpio_port_config_t, asc_r) == 0x2C, "Offset check failed");
 
-#endif /* CORE_GPIO_H__ */
+#endif
diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/rcc.h b/02-usart/include/arch/stm32l4xxx/peripherals/rcc.h
index 861504e..de7b568 100644
--- a/02-usart/include/arch/stm32l4xxx/peripherals/rcc.h
+++ b/02-usart/include/arch/stm32l4xxx/peripherals/rcc.h
@@ -63,6 +63,14 @@ typedef struct {
 #define rcc_tscen   (1 << 16) /* Touch sensing controller clock enable. */
 #define rcc_dmad2en (1 << 17) /* DMA2D clock enabled. */
   __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */
+
+#define  rcc_gpioen(port)  (1  <<  (port))
+#define  rcc_otgfsen       (1  <<  12)
+#define  rcc_adcen         (1  <<  13)
+#define  rcc_dcmien        (1  <<  14)
+#define  rcc_assen         (1  <<  16)
+#define  rcc_hashen        (1  <<  17)
+#define  rcc_rngen         (1  <<  18)
   __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */
   __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */
 
diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc b/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc
new file mode 100644
index 0000000..66d347c
--- /dev/null
+++ b/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc
@@ -0,0 +1,100 @@
+AFN(CAN1_RX,           9,   PA11)
+AFN(CAN1_TX,           9,   PA12)
+AFN(COMP1_OUT,         12,  PA0,   12,  PB0,   6,   PA11,  6,  PA6)
+AFN(COMP2_OUT,         12,  PA2,   12,  PA7,   12,  PB5)
+AFN(I2C1_SCL,          4,   PA9,   4,   PB6)
+AFN(I2C1_SDA,          4,   PA10,  4,   PB7)
+AFN(I2C1_SMBA,         4,   PA14,  4,   PA1,   4,   PB5)
+AFN(I2C3_SCL,          4,   PA7)
+AFN(I2C3_SDA,          4,   PB4)
+AFN(IR_OUT,            1,   PA13)
+AFN(JTCK_SWCLK,        0,   PA14)
+AFN(JTDI,              0,   PA15)
+AFN(JTDO_TRACESWO,     0,   PB3)
+AFN(JTMS_SWDIO,        0,   PA13)
+AFN(LPTIM1_ETR,        1,   PB6)
+AFN(LPTIM1_IN1,        1,   PB5)
+AFN(LPTIM1_IN2,        1,   PB7)
+AFN(LPTIM1_OUT,        1,   PA14)
+AFN(LPTIM2_ETR,        14,  PA5)
+AFN(LPTIM2_IN1,        14,  PB1)
+AFN(LPTIM2_OUT,        14,  PA4,   14,  PA8)
+AFN(LPUART1_CTS,       8,   PA6)
+AFN(LPUART1_RTS_DE,    8,   PB1)
+AFN(LPUART1_RX,        8,   PA3)
+AFN(LPUART1_TX,        8,   PA2)
+AFN(MCO,               0,   PA8)
+AFN(NJTRST,            0,   PB4)
+AFN(QUADSPI_BK1_IO0,   10,  PB1)
+AFN(QUADSPI_BK1_IO1,   10,  PB0)
+AFN(QUADSPI_BK1_IO2,   10,  PA7)
+AFN(QUADSPI_BK1_IO3,   10,  PA6)
+AFN(QUADSPI_BK1_NCS,   10,  PA2)
+AFN(QUADSPI_CLK,       10,  PA3)
+AFN(SAI1_EXTCLK,       13,  PA0,   13,  PB0)
+AFN(SAI1_FS_A,         13,  PA9)
+AFN(SAI1_FS_B,         13,  PA14,  13,  PA4,   13,  PB6)
+AFN(SAI1_MCLK_A,       13,  PA3)
+AFN(SAI1_MCLK_B,       13,  PB4)
+AFN(SAI1_SCK_A,        13,  PA8)
+AFN(SAI1_SCK_B,        13,  PB3)
+AFN(SAI1_SD_A,         13,  PA10)
+AFN(SAI1_SD_B,         13,  PA13,  13,  PB5)
+AFN(SPI1_MISO,         5,   PA11,  5,   PA6,   5,   PB4)
+AFN(SPI1_MOSI,         5,   PA12,  5,   PA7,   5,   PB5)
+AFN(SPI1_NSS,          5,   PA15,  5,   PA4,   5,   PB0)
+AFN(SPI1_SCK,          5,   PA1,   5,   PA5,   5,   PB3)
+AFN(SPI3_MISO,         6,   PB4)
+AFN(SPI3_MOSI,         6,   PB5)
+AFN(SPI3_NSS,          6,   PA15,  6,   PA4)
+AFN(SPI3_SCK,          6,   PB3)
+AFN(SWPMI1_IO,         12,  PA8)
+AFN(SWPMI1_RX,         12,  PA14)
+AFN(SWPMI1_SUSPEND,    12,  PA15)
+AFN(SWPMI1_TX,         12,  PA13)
+AFN(TIM15_BKIN,        14,  PA9)
+AFN(TIM15_CH1,         14,  PA2)
+AFN(TIM15_CH1N,        14,  PA1)
+AFN(TIM15_CH2,         14,  PA3)
+AFN(TIM16_BKIN,        14,  PB5)
+AFN(TIM16_CH1,         14,  PA6)
+AFN(TIM16_CH1N,        14,  PB6)
+AFN(TIM1_BKIN,         1,   PA6)
+AFN(TIM1_BKIN2,        2,   PA11)
+AFN(TIM1_BKIN2_COMP1,  12,  PA11)
+AFN(TIM1_BKIN_COMP2,   12,  PA6)
+AFN(TIM1_CH1,          1,   PA8)
+AFN(TIM1_CH1N,         1,   PA7)
+AFN(TIM1_CH2,          1,   PA9)
+AFN(TIM1_CH2N,         1,   PB0)
+AFN(TIM1_CH3,          1,   PA10)
+AFN(TIM1_CH3N,         1,   PB1)
+AFN(TIM1_CH4,          1,   PA11)
+AFN(TIM1_ETR,          1,   PA12)
+AFN(TIM2_CH1,          1,   PA0,   1,   PA15,  1,   PA5)
+AFN(TIM2_CH2,          1,   PA1,   1,   PB3)
+AFN(TIM2_CH3,          1,   PA2)
+AFN(TIM2_CH4,          1,   PA3)
+AFN(TIM2_ETR,          14,  PA0,   2,   PA15,  2,   PA5)
+AFN(TSC_G2_IO1,        9,   PB4)
+AFN(TSC_G2_IO2,        9,   PB5)
+AFN(TSC_G2_IO3,        9,   PB6)
+AFN(TSC_G2_IO4,        9,   PB7)
+AFN(TSC_G3_IO1,        9,   PA15)
+AFN(USART1_CK,         7,   PA8,   7,   PB5)
+AFN(USART1_CTS,        7,   PA11,  7,   PB4)
+AFN(USART1_RTS_DE,     7,   PA12,  7,   PB3)
+AFN(USART1_RX,         7,   PA10,  7,   PB7)
+AFN(USART1_TX,         7,   PA9,   7,   PB6)
+AFN(USART2_CK,         7,   PA4)
+AFN(USART2_CTS,        7,   PA0)
+AFN(USART2_RTS_DE,     7,   PA1)
+AFN(USART2_RX,         3,   PA15,  7,   PA3)
+AFN(USART2_TX,         7,   PA2)
+AFN(USART3_CK,         7,   PB0)
+AFN(USART3_CTS,        7,   PA6)
+AFN(USART3_RTS_DE,     7,   PA15,  7,   PB1)
+AFN(USB_CRS_SYNC,      10,  PA10)
+AFN(USB_DM,            10,  PA11)
+AFN(USB_DP,            10,  PA12)
+AFN(USB_NOE,           10,  PA13)
diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc b/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc
new file mode 100644
index 0000000..21c7234
--- /dev/null
+++ b/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc
@@ -0,0 +1,26 @@
+PORT(A, 0)
+PORT(A, 1)
+PORT(A, 2)
+PORT(A, 3)
+PORT(A, 4)
+PORT(A, 5)
+PORT(A, 6)
+PORT(A, 7)
+PORT(A, 8)
+PORT(A, 9)
+PORT(A, 10)
+PORT(A, 11)
+PORT(A, 12)
+PORT(A, 13)
+PORT(A, 14)
+PORT(A, 15)
+PORT(B, 0)
+PORT(B, 1)
+PORT(B, 3)
+PORT(B, 4)
+PORT(B, 5)
+PORT(B, 6)
+PORT(B, 7)
+PORT(C, 14)
+PORT(C, 15)
+PORT(H, 3)
diff --git a/02-usart/include/arch/x86_64/arch.h b/02-usart/include/arch/x86_64/arch.h
index 5e1217c..c17721d 100644
--- a/02-usart/include/arch/x86_64/arch.h
+++ b/02-usart/include/arch/x86_64/arch.h
@@ -17,6 +17,7 @@
 #define GPIOA_BASE (load_fake_ahb2__() + 0x0)
 #define GPIOB_BASE (load_fake_ahb2__() + 0x400)
 #define GPIOC_BASE (load_fake_ahb2__() + 0x800)
+#define GPIOH_BASE (load_fake_ahb2__() + 0x1C00)
 
 #define SRAM1_BASE (load_fake_sram1__() + 0x0)
 #define SRAM2_BASE (load_fake_sram2__() + 0x0)