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| author | Josh Rahm <joshuarahm@gmail.com> | 2020-11-20 18:41:49 -0700 |
|---|---|---|
| committer | Josh Rahm <joshuarahm@gmail.com> | 2020-11-20 19:03:01 -0700 |
| commit | fd763486d875968941c77386e23936e817856c8e (patch) | |
| tree | ed85ffe2d6c27b502d06aefa5e63244450bb7028 /02-usart/include/core/nvic.h | |
| parent | 3b6018348d51c77f53adca90e498d7bf268c91c9 (diff) | |
| download | stm32l4-fd763486d875968941c77386e23936e817856c8e.tar.gz stm32l4-fd763486d875968941c77386e23936e817856c8e.tar.bz2 stm32l4-fd763486d875968941c77386e23936e817856c8e.zip | |
Finally got a peripheral interrupt!
Diffstat (limited to '02-usart/include/core/nvic.h')
| -rw-r--r-- | 02-usart/include/core/nvic.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/02-usart/include/core/nvic.h b/02-usart/include/core/nvic.h new file mode 100644 index 0000000..c761574 --- /dev/null +++ b/02-usart/include/core/nvic.h @@ -0,0 +1,46 @@ +#ifndef NVIC_H_ +#define NVIC_H_ + +#include "arch.h" +#include "common.h" + +typedef __IO struct { +#define nvic_intlinesnum (0x0F << 0) + uint32_t ict_r; /* Interrupt control type register. */ + + uint8_t reserved0[0xF8]; + + uint32_t ise_r[8]; + + uint8_t reserved1[0x60]; + + uint32_t ice_r[8]; + + uint8_t reserved2[0x60]; + + uint32_t isp_r[8]; + + uint8_t reserved3[0x60]; + + uint32_t icp_r[8]; + + uint8_t reserved4[0x60]; + + uint32_t iab_r[8]; + + uint8_t reserved5[0xE0]; + + uint32_t ip_r[60]; +} nvic_t; + +static_assert(offsetof(nvic_t, ise_r) == 0x00FC, "Offset check failed"); +static_assert(offsetof(nvic_t, ice_r) == 0x017C, "Offset check failed"); +static_assert(offsetof(nvic_t, isp_r) == 0x01FC, "Offset check failed"); +static_assert(offsetof(nvic_t, icp_r) == 0x027C, "Offset check failed"); +static_assert(offsetof(nvic_t, iab_r) == 0x02FC, "Offset check failed"); +static_assert(offsetof(nvic_t, ip_r) == 0x03FC, "Offset check failed"); + +#define NVIC (* (nvic_t*) NVIC_BASE) + + +#endif /* NVIC_H_ */ |