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author | Josh Rahm <joshuarahm@gmail.com> | 2020-11-16 21:02:48 -0700 |
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committer | Josh Rahm <joshuarahm@gmail.com> | 2020-11-16 21:02:48 -0700 |
commit | c0e1b4cdf20c55f2cbbdf3a5889f447974135fd8 (patch) | |
tree | 003c27f4551f02de304da28cc60314a4516c40ed /02-usart/include/rcc.h | |
parent | cd115ba47253ce8d2680178248116d251abacb23 (diff) | |
download | stm32l4-c0e1b4cdf20c55f2cbbdf3a5889f447974135fd8.tar.gz stm32l4-c0e1b4cdf20c55f2cbbdf3a5889f447974135fd8.tar.bz2 stm32l4-c0e1b4cdf20c55f2cbbdf3a5889f447974135fd8.zip |
Got the DMA to send a simple message through UART2.
Diffstat (limited to '02-usart/include/rcc.h')
-rw-r--r-- | 02-usart/include/rcc.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/02-usart/include/rcc.h b/02-usart/include/rcc.h index 7ed4dee..05f5e5f 100644 --- a/02-usart/include/rcc.h +++ b/02-usart/include/rcc.h @@ -33,7 +33,21 @@ typedef struct { __IO uint32_t reserved_4; /* Not used. offset 0x44. */ - __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ + __IO union { + __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ + struct { + bits_t dma1en:1; /* DMA1 clock enable. */ + bits_t dma2en:1; /* DMA2 clock enable. */ + bits_t reserved0:6; + bits_t flashen:1; /* Flash memory interface clock enable. */ + bits_t reserved1:3; + bits_t crcen:1; /* CRC clock enable. */ + bits_t reserved2:3; + bits_t tscen:1; /* Touch sensing controller clock enable. */ + bits_t dmad2en:1; /* DMA2D clock enabled. */ + bits_t reserved3:14; + } ahb1en_bf; + }; __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ @@ -60,6 +74,8 @@ typedef struct { __IO uint32_t ccip_r; /* 0x88 */ } PACKED rcc_t; +static_assert(offsetof(rcc_t, ccip_r) == 0x88, "Offset check failed."); + #define RCC (*(__IO rcc_t*)RCC_BASE) /* Macros to operate on the RCC registers. */ |