Add DMA header file which defines the DMA registers and add

testing_harness with fake environment to allow testing on x86
development machines.

1 files changed, 73 insertions, 11 deletions

diff --git a/02-usart/include/usart.h b/02-usart/include/usart.h
index 257aab6..d806397 100644
--- a/02-usart/include/usart.h
+++ b/02-usart/include/usart.h
@@ -1,13 +1,17 @@
 #ifndef H__USART_
 #define H__USART_
 
+#include <arch.h>
+#include <stdint.h>
+
 #include "common.h"
 #include "rcc.h"
 
-#include <stdint.h>
+#define USART1 (* (__IO usart_t*) USART1_BASE)
+#define USART2 (* (__IO usart_t*) USART2_BASE)
 
 /*
- * Possibel USART clock sources.
+ * Possible USART clock sources.
  */
 typedef enum {
   USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */
@@ -43,24 +47,82 @@ typedef struct {
       bits_t eobie:1;
       bits_t m1:1;
       bits_t reserved:3;
-    } PACKED c1_bf;
-  };
+    } PACKED c1_bf; /* c1_bf = c1 bit field */
+  }; /* USART Control Register 1. */
   uint32_t c_r2;
-  uint32_t c_r3;
+
+  union {
+    uint32_t c_r3;
+    struct {
+      bits_t eie:1;   // Error interrupt enable. 
+      bits_t iren:1;  // IrDA mode enabled
+      bits_t irlp:1;  // IrDA low power
+      bits_t hdsel:1; // Half duplex selection
+      bits_t nack:1;  // Smartcard NACK enable
+      bits_t scen:1;  // Smartocard mode enable
+      bits_t dmar:1;  // DMA enable reciever
+      bits_t dmat:1;  // DMA enable transmitter
+      bits_t rtse:1;  // RTS enable
+      bits_t ctse:1;  // CTS enable
+      bits_t ctsie:1; // CTS interrupt enable
+      bits_t onebit:1; // One sample bit method enable
+      bits_t ovrdis:1; // Overrun disable
+      bits_t ddre:1; // DMA Disable on reception error
+      bits_t dem:1; // Driver enable mode
+      bits_t dep:1; // Driver enable polarity selection
+      bits_t reserved0:1;
+      bits_t scarcnt:3; // Smartcard auto-retry count.
+      bits_t wus:2; // Wakeup from STOP mode interrept flag selection
+      bits_t wufie:1; // Wakeup from STOP mode interrup enable
+      bits_t ucesm:1; // USART clock enable in STOP mode.
+      bits_t tcbgtie:1; // Transmission complete before guard time interrupt
+      bits_t reserved1:7;
+    } PACKED c3_bf;
+  };
 
   /* USART baud rate register. */
   uint32_t br_r;
   uint32_t gtp_r;
   uint32_t rto_r;
   uint32_t rq_r;
-  uint32_t is_r;
+
+  /* USART ISR register. Offset = 0x1c*/
+  union {
+    uint32_t is_r; /* Interrupt service register. */
+    struct {
+      bits_t pe:1;    // Parity error
+      bits_t fe:1;    // Framing error
+      bits_t nf:1;    // START bit noise detection flag.
+      bits_t ore:1;   // Overrun error
+      bits_t dlie:1;  // Idle line detected
+      bits_t rxne:1;  // Read data register not empty
+      bits_t tc:1;    // Transmission complete
+      bits_t txe:1;   // Transmit data register empty
+      bits_t lbdf:1;  // LIN break detection flag
+      bits_t ctsif:1; // CTS interrupt flag
+      bits_t cts:1;   // CTS flag.
+      bits_t rtof:1;  // Receiever timeout
+      bits_t eobf:1;  // End of block flag
+      bits_t reserved0:1;
+      bits_t abre:1;  // Auto baud rate error
+      bits_t abrf:1;  // Auto baud rate flag
+      bits_t busy:1;  // Busy flag
+      bits_t cmf:1;   // Character match flag
+      bits_t sbkf:1;  // send break flag
+      bits_t rwu:1;   // receiver wakeup frlom mute mode.
+      bits_t wuf:1;   // Wakeup from stop mode flag
+      bits_t teack:1; // Transmit enable acknowledge flag.
+      bits_t reack:1; // Receieve enable acknowledge flag.
+      bits_t reserved1:2;
+      bits_t tcbgt:1; // Transmission completer before guard time completion.
+      bits_t reserved2:6;
+    } PACKED is_bf; /* Interrupt servite bit field. */
+  };
   uint32_t ic_r;
   uint32_t rd_r;
   uint32_t td_r;
 } usart_t;
 
-#define USART1 (* (__IO usart_t*) 0x40013800)
-#define USART2 (* (__IO usart_t*) 0x40004400)
 typedef enum {
   OVERSAMPLE_8,
   OVERSAMPLE_16
@@ -112,7 +174,7 @@ void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled);
  * Send a byte on the usart, This command blocks until the data
  * is fully sent.
  */
-void usart_transmit_byte(__IO usart_t* usart, uint8_t byte);
+void usart_transmit_byte_sync(__IO usart_t* usart, uint8_t byte);
 
 void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src);
 
@@ -122,10 +184,10 @@ void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src);
 
 void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable);
 
-void usart_transmit_bytes(
+void usart_transmit_bytes_sync(
     __IO usart_t* usart, const uint8_t* bytes, uint32_t n);
 
-void usart_transmit_str(__IO usart_t* usart, const char* str);
+void usart_transmit_str_sync(__IO usart_t* usart, const char* str);
 
 
 #endif /* H__USART_ */