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authorJosh Rahm <joshuarahm@gmail.com>2020-11-23 19:41:05 -0700
committerJosh Rahm <joshuarahm@gmail.com>2020-11-23 19:41:05 -0700
commit60b1e3055c179312eef809fe1d01f58042b64d5f (patch)
treec620b5ca1eab2d05c9396637db50d0a110328d29 /02-usart/src/arch/stm32l4xxx/peripherals/gpio.c
parent2a6ae24ba769892993ec7a173c564f59feb06495 (diff)
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Add new GPIO subsystem.
This gpio subsystem keeps track of the GPIO pins which have been reserved and takes care of the housekeeping with keeping them running. This gpio subsystem also knows which alternate functions belong to which pins, so it can automatically configure the pins for the alternate functions.
Diffstat (limited to '02-usart/src/arch/stm32l4xxx/peripherals/gpio.c')
-rw-r--r--02-usart/src/arch/stm32l4xxx/peripherals/gpio.c52
1 files changed, 0 insertions, 52 deletions
diff --git a/02-usart/src/arch/stm32l4xxx/peripherals/gpio.c b/02-usart/src/arch/stm32l4xxx/peripherals/gpio.c
deleted file mode 100644
index a1e82c7..0000000
--- a/02-usart/src/arch/stm32l4xxx/peripherals/gpio.c
+++ /dev/null
@@ -1,52 +0,0 @@
-#include "arch/stm32l4xxx/peripherals/gpio.h"
-#include "arch/stm32l4xxx/peripherals/rcc.h"
-
-/*
- * Sets the mode of a pin on a gpio por.
- */
-void set_gpio_pin_mode(
- __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode)
-{
- /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */
- gpio_port->mode_r &= ~(0x03 << pin * 2);
- gpio_port->mode_r |= mode << pin * 2;
-}
-
-gpio_output_pin_t set_gpio_pin_output(
- __IO gpio_port_t* gpio_port, gpio_pin_t pin)
-{
- set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT);
-
- return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin};
-}
-
-void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff)
-{
- if (onoff) {
- pin.gpio_port->output_r |= 1 << pin.pin;
- } else {
- pin.gpio_port->output_r &= ~(1 << pin.pin);
- }
-}
-
-void set_gpio_alternate_function(
- __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn)
-{
- __IO uint32_t* reg;
- if (gpio_pin < 8) {
- reg = &(port->af_rl);
- } else {
- reg = &(port->af_rh);
- gpio_pin -= 8;
- }
-
- uint32_t tmp = *reg & (~0x0f << gpio_pin * 4);
- *reg = tmp | (afn << gpio_pin * 4);
-}
-
-#define GPIO_PORTS_BASE_ADDR ((uint8_t*)0x48000000)
-__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number)
-{
- RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */
- return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400));
-}