Moved action to top level.

Removed old iterations of the project and moved the files from 02-usart
to the root directory since that's the sole place where the action is
and that subproject has outgrown its initial title.

21 files changed, 0 insertions, 1278 deletions

diff --git a/02.5-collatz/Makefile.preamble b/02.5-collatz/Makefile.preamble
deleted file mode 100644
index 3c8a61b..0000000
--- a/02.5-collatz/Makefile.preamble
+++ /dev/null
@@ -1,21 +0,0 @@
-OPT?=-O
-PREFIX?=arm-unknown-eabi-
-CC=$(PREFIX)gcc
-LD=$(PREFIX)ld
-CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude
-LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static
-
-
-all: _$(PREFIX)_obs/main.elf
-
-_$(PREFIX)_obs/main.bin: _$(PREFIX)_obs/main.elf
-	$(PREFIX)objcopy -O binary _$(PREFIX)_obs/main.elf _$(PREFIX)_obs/main.bin
-
-flash: _$(PREFIX)_obs/main.bin
-	st-flash write _$(PREFIX)_obs/main.bin 0x8000000
-
-clean:
-	rm -rf _*_obs
-
-genmake:
-	./genmake.pl > Makefile
diff --git a/02.5-collatz/genmake.pl b/02.5-collatz/genmake.pl
deleted file mode 100755
index 341db3d..0000000
--- a/02.5-collatz/genmake.pl
+++ /dev/null
@@ -1,70 +0,0 @@
-#!/usr/bin/perl
-
-# This script is designed to introspect C files and generate a makefile to use.
-
-sub header_deps {
-  my $file = @_[0];
-  my @headers;
-
-  if (open(my $fh, '<:encoding(UTF-8)', $file)) {
-    print STDERR "\x1b[35m[Trace] - Reading file $file\x1b[00m\n";
-    push(@headers, $file);
-
-    while (<$fh>) {
-      /#include\s+"(.*)"\s*$/ && push(@headers, header_deps("include/$1"));
-    }
-  }
-
-  return @headers;
-}
-
-my @files = glob('src/*.c');
-my @obj_files;
-
-open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble")
-    or die "Missing Makefile.preamble";
-
-while (<$fh>) {
-  print "$_";
-}
-
-# Emit a rule that will rerun genmake if the c files do not match.
-my $idempotency_cmd =
-    "ls src/*.c include/*.h| sha1sum | awk '{print \$1}'";
-
-my $idempotency_cmd_make =
-    "ls src/*.c include/*.h | sha1sum | awk '{print \$\$1}'";
-
-print "IDEMPOTENCY_HASH=" . `$idempotency_cmd` . "\n";
-
-my $arch_obs_dir = "_\$(PREFIX)_obs";
-print "CHEAT_PRE_MAKE := \$(shell mkdir -p $arch_obs_dir)\n";
-
-foreach $file (@files) {
-  my $c_file = $file;
-  (my $file_no_ext = $file) =~ s/src\/(.*)\.c$/\1/g;
-
-  my $obj_file = "$arch_obs_dir/${file_no_ext}.o";
-  my $s_file = "${file_no_ext}.s";
-
-  push(@obj_files, $obj_file);
-  my @deps = header_deps($c_file);
-
-  my $deps_as_join = join(" ", @deps);
-
-  # Emit the rule to make the object file.
-  print "$obj_file: $deps_as_join\n\t";
-  print '$(CC) -c ' . $c_file . ' -o ' . $obj_file . ' $(CFLAGS)' . "\n\n";
-
-  # Emit the rule to make the assembly file.
-  print "$s_file: $deps_as_join\n\t";
-  print '$(CC) -S ' . $c_file . ' -o ' . $s_file . ' $(CFLAGS)' . "\n\n";
-}
-
-my $obj_files_deps = join(' ', @obj_files);
-print "FORCE:\n\t\n\n";
-print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t";
-print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] "
-        . "&& ./genmake.pl > Makefile && make main.elf ) "
-        . "|| "
-        . "\$(LD) -o $arch_obs_dir/main.elf \$(LD_FLAGS) $obj_files_deps\n\n";
diff --git a/02.5-collatz/include/apb.h b/02.5-collatz/include/apb.h
deleted file mode 100644
index 11fa7ab..0000000
--- a/02.5-collatz/include/apb.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef H__APB_
-#define H__APB_
-
-#endif /* H__APB_ */
diff --git a/02.5-collatz/include/clock.h b/02.5-collatz/include/clock.h
deleted file mode 100644
index 46ac6f2..0000000
--- a/02.5-collatz/include/clock.h
+++ /dev/null
@@ -1,126 +0,0 @@
-#ifndef CLOCK_H__
-#define CLOCK_H__
-
-#include <stdint.h>
-#include "rcc.h"
-
-#define PERIPH_BASE ((uint32_t)0x40000000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00)
-#define PWR_BASE (PERIPH_BASE + 0x7000)
-#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
-
-#ifndef __IO
-#define __IO volatile
-#endif
-
-typedef struct {
-  __IO uint32_t cr;
-  __IO uint32_t csr;
-} pwr_t;
-
-// typedef struct {
-//   __IO uint32_t acr;
-//   __IO uint32_t pecr;
-//   __IO uint32_t pdkeyr;
-//   __IO uint32_t pekeyr;
-//   __IO uint32_t prgkeyr;
-//   __IO uint32_t optkeyr;
-//   __IO uint32_t sr;
-//   __IO uint32_t obr;
-//   __IO uint32_t wrpr;
-// } flash_t;
-
-// #define FLASH (*(flash_t*) (FLASH_R_BASE))
-#define PWR (*(pwr_t*)(PWR_BASE))
-
-/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */
-typedef enum {
-  PLL_DIVISOR_2 = 1,
-  PLL_DIVISOR_4 = 3,
-  PLL_DIVISOR_6 = 5,
-  PLL_DIVISOR_8 = 7,
-  PLL_DIVISOR_OFF = 0,
-} pll_divisor_t;
-
-/* Valid values for the PLLP bits off the PLLCFG register. */
-typedef enum {
-  PLLP_DIVISOR_7 = 1,
-  PLLP_DIVISOR_17 = 3,
-  PLLP_DIVISOR_OFF = 0,
-} pllp_divisor_t;
-
-/* Valid values for the PLLM bits of the PLLCFG register. */
-typedef enum {
-  PLLM_DIVISOR_1 = 0,
-  PLLM_DIVISOR_2 = 1,
-  PLLM_DIVISOR_3 = 2,
-  PLLM_DIVISOR_4 = 3,
-  PLLM_DIVISOR_5 = 4,
-  PLLM_DIVISOR_6 = 5,
-  PLLM_DIVISOR_7 = 6,
-  PLLM_DIVISOR_8 = 7,
-} pllm_divisor_t;
-
-/* Possible sources for the input clock. */
-typedef enum {
-  PLL_SRC_NONE = 0,
-  PLL_SRC_MSI = 1,
-  PLL_SRC_HSI = 2,
-  PLL_SRC_HSE = 3,
-} pll_src_t;
-
-/* Valid sources for the system clock. */
-typedef enum {
-  SYSTEM_CLOCK_SRC_MSI = 0,
-  SYSTEM_CLOCK_SRC_HSI = 1,
-  SYSTEM_CLOCK_SRC_HSE = 2,
-  SYSTEM_CLOCK_SRC_PLL = 3,
-} system_clock_src_t;
-
-#define E_BADPLLN (-2)
-#define E_BADPLLP_DIV (-1)
-#define E_TIMEOUT (-3)
-#define E_NOT_OFF (-4)
-#define E_BAD_ARG (-5)
-
-#define enable_hsi(rcc, enabled) do { \
-  if (enabled) { \
-    (rcc)->c_r |= BIT(8); \
-  } else { \
-    (rcc)->c_r &= ~BIT(8); \
-  } \
-} while(0)
-
-/*
- * Sets the system clock to a full 80Mhz.
- */
-int set_system_clock_MHz(uint8_t mhz);
-
-/*
- * Set the PLL on.
- */
-int pll_on();
-
-/*
- * Set the PLL off.
- */
-int pll_off();
-
-/*
- * Sets the source of the system clock.
- */
-int set_system_clock_src(system_clock_src_t src);
-
-/*
- * Configure the PLL.
- */
-int configure_pll(
-    uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */
-    pll_divisor_t pllq,  /* Divison factor for PLL48M1CLK. */
-    pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */
-    uint8_t plln,        /* PLL numerator. */
-    pllm_divisor_t pllm, /* PLL denominator. */
-    pll_src_t pllsrc /* PLL source */);
-
-#endif /* CLOCK_H__ */
diff --git a/02.5-collatz/include/common.h b/02.5-collatz/include/common.h
deleted file mode 100644
index 9d5c7cd..0000000
--- a/02.5-collatz/include/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef COMMON__H
-#define COMMON__H
-
-#include <stdint.h>
-
-/* Define __IO to be volatile if it's not already. */
-#ifndef __IO
-#define __IO volatile
-#endif
-
-#define bool int
-#ifndef __cplusplus
-#define true 1
-#define false 0
-#endif
-
-#define PACKED __attribute__((packed))
-#define BIT(n) (1 << (n))
-
-#define RESERVED_CONCAT_IMPL(x, y) x ## y
-#define RESERVED_MACRO_CONCAT(x, y) RESERVED_CONCAT_IMPL(x, y)
-#define RESERVED(n) \
-  bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) :n
-  
-#define RESERVE(type) \
-  __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__)
-
-typedef uint32_t bits_t;
-
-#endif /* COMMON_H */
diff --git a/02.5-collatz/include/delay.h b/02.5-collatz/include/delay.h
deleted file mode 100644
index 65a26d6..0000000
--- a/02.5-collatz/include/delay.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef H__DELAY__
-#define H__DELAY__
-
-#include <stdint.h>
-
-/*
- * Loops and count-downs the delay, the time this takes depends on the speed
- * of the clock.
- */
-void delay(uint32_t delay);
-
-#endif /* H__DELAY__ */
diff --git a/02.5-collatz/include/flash.h b/02.5-collatz/include/flash.h
deleted file mode 100644
index a163a25..0000000
--- a/02.5-collatz/include/flash.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef H__FLASH_
-#define H__FLASH_
-
-#include "common.h"
-
-/*
- * Header file for dealing with flash.
- */
-
-#define FLASH_BASE 0x40022000
-
-typedef struct {
-  __IO uint32_t ac_r; /* Flash access control register. */
-
-  /* TODO fill out the rest. */
-} PACKED flash_t;
-
-#define FLASH (*(__IO flash_t*)FLASH_BASE)
-
-#endif /* H__FLASH_ */
diff --git a/02.5-collatz/include/gpio.h b/02.5-collatz/include/gpio.h
deleted file mode 100644
index 62169c6..0000000
--- a/02.5-collatz/include/gpio.h
+++ /dev/null
@@ -1,146 +0,0 @@
-#ifndef GPIO_H__
-#define GPIO_H__
-
-#include "common.h"
-#include "rcc.h"
-
-#include <stdint.h>
-
-/*
- * Possible GPIO ports.
- */
-typedef enum {
-  GPIO_PORT_A = 0,
-  GPIO_PORT_B = 1,
-  GPIO_PORT_C = 2,
-  GPIO_PORT_D = 3
-} gpio_port_number_t;
-
-/*
- * Structure defining the layout of the layout of the GPIO registers on the
- * stm32l432 development board.
- */
-typedef struct GPIO_PORT_STR {
-  __IO uint32_t mode_r;   /* Mode register */
-  __IO uint32_t otype_r;
-  __IO uint32_t ospeed_r;
-  __IO uint32_t pupd_r;
-  __IO uint32_t id_r;
-  __IO uint32_t output_r;
-  __IO uint32_t bsr_r;
-  __IO uint32_t lck_r;
-  __IO uint32_t af_rl;
-  __IO uint32_t af_rh;
-} PACKED gpio_port_t;
-
-/*
- * Enum defining the PINs in a GPIO port. Each port has 16 pins to use in
- * the stm32l432.
- */
-typedef enum GPIO_PIN_ENUM {
-  PIN_0 = 0,
-  PIN_1 = 1,
-  PIN_2 = 2,
-  PIN_3 = 3,
-  PIN_4 = 4,
-  PIN_5 = 5,
-  PIN_6 = 6,
-  PIN_7 = 7,
-  PIN_8 = 8,
-  PIN_9 = 9,
-  PIN_10 = 10,
-  PIN_11 = 11,
-  PIN_12 = 12,
-  PIN_13 = 13,
-  PIN_14 = 14,
-  PIN_15 = 15
-} gpio_pin_t;
-
-/* Alternate function number. */
-typedef enum {
-  AFN_0 = 0,
-  AFN_1 = 1,
-  AFN_2 = 2,
-  AFN_3 = 3,
-  AFN_4 = 4,
-  AFN_5 = 5,
-  AFN_6 = 6,
-  AFN_7 = 7,
-  AFN_8 = 8,
-  AFN_9 = 9,
-  AFN_10 = 10,
-  AFN_11 = 11,
-  AFN_12 = 12,
-  AFN_13 = 13,
-  AFN_14 = 14,
-  AFN_15 = 15
-} alternate_function_t;
-
-/*
- * Enum defining the pin modes that are possible.
- */
-typedef enum {
-  MODE_INPUT = 0,
-  MODE_OUTPUT = 1,
-  MODE_ALTERNATE = 2,
-  MODE_ANALOG = 3
-} gpio_pin_mode_t;
-
-/*
- * Enum defining the pin speeds that are possible.
- */
-typedef enum {
-  SPEED_2MHZ = 0,
-  SPEED_10MHZ = 1,
-  SPEED_50MHZ = 3,
-} speed_t;
-
-/*
- * Structure defining an OUTPUT pin. Structurally equivalent to the input pin,
- * but can be used in a slightly type-safe manner.
- */
-typedef struct {
-  __IO gpio_port_t* gpio_port;
-  gpio_pin_t pin;
-} gpio_output_pin_t;
-
-/*
- * Sets the mode on a GPIO pin.
- *
- * gpio_port: the gpio port to use.
- * pin: the pin number to set.
- * pin_mode: the mode to set the pin to.
- */
-void set_gpio_pin_mode(
-    __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode);
-
-/*
- * Sets the given GPIO pin to be an output pin. Returns an output_pin struct
- * corresponding to
- */
-gpio_output_pin_t set_gpio_pin_output(
-    __IO gpio_port_t* gpio_port, gpio_pin_t pin);
-
-/*
- * Sets an output pin on or off.
- *
- * pin: the pin to toggle.
- * onoff: 0 for off, non-zero of on.
- */
-void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff);
-
-#define pin_on(p) set_gpio_output_pin(p, 1)
-
-#define pin_off(p) set_gpio_output_pin(p, 0)
-
-/*
- * Enables a GPIO port and returns a reference to the register definition
- * of that GPIO port.
- */
-__IO gpio_port_t* enable_gpio(gpio_port_number_t number);
-
-/* Sets the alternate function for a GPIO pin. */
-void set_gpio_alternate_function(
-    __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn);
-
-#endif /* GPIO_H__ */
diff --git a/02.5-collatz/include/isr_vector.h b/02.5-collatz/include/isr_vector.h
deleted file mode 100644
index 3e55f52..0000000
--- a/02.5-collatz/include/isr_vector.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef h__ISR_VECTOR_H__
-#define h__ISR_VECTOR_H__
-
-/*
- * Include file for interrupt service routines.
- */
-
-/*
- * The interrupt service routines. These link in the function `main` as the
- * main function.
- */
-extern const void* isr_vector[];
-
-/*
- * Defines an error state. This loops forever and defines a distinct flashing
- * pattern to let the user know an unhandled ISR happened.
- */
-void unhandled_isr();
-
-#endif /* h___ISR_VECTOR_H__ */
diff --git a/02.5-collatz/include/rcc.h b/02.5-collatz/include/rcc.h
deleted file mode 100644
index 7ed4dee..0000000
--- a/02.5-collatz/include/rcc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef H__RCC_
-#define H__RCC_
-
-#include "common.h"
-#include <stdint.h>
-
-#define RCC_BASE ((uint32_t)0x40021000)
-
-typedef struct {
-  __IO uint32_t c_r;      /* Clock control register. 0x00 */
-  __IO uint32_t icsc_r;   /* Internal clock srcs calibration register. 0x04 */
-  __IO uint32_t cfg_r;    /* clock confguration register. 0x08 */
-  __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */
-  __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */
-
-  __IO uint32_t reserved_1; /* Not used. offset 0x14. */
-
-  __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */
-  __IO uint32_t cif_r; /* Clock interrupt flag regiseter.  0x1c */
-  __IO uint32_t cic_r; /* Clock interrupt clear register.  0x20 */
-
-  __IO uint32_t reserved_2; /* Not used. offset 0x24. */
-
-  __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */
-  __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */
-  __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */
-
-  __IO uint32_t reserved_3; /* Not used. offset 0x34. */
-
-  __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */
-  __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */
-  __IO uint32_t apb2rst_r;  /* APB Peripheral reset register.   0x40 */
-
-  __IO uint32_t reserved_4; /* Not used. offset 0x44. */
-
-  __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */
-  __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */
-  __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */
-
-  __IO uint32_t reserved_5; /* Not used. offset 0x54. */
-
-  __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */
-  __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */
-  __IO uint32_t apb2en_r;  /* APB2 Peripheral enable register.   0x60 */
-
-  __IO uint32_t reserved_6; /* Not used. offset 0x64. */
-
-  __IO uint32_t ahb1smen_r; /* 0x68 */
-  __IO uint32_t ahb2smen_r; /* 0x6c */
-  __IO uint32_t ahb3smen_r; /* 0x70 */
-
-  __IO uint32_t reserved_7;
-
-  __IO uint32_t apb1smen_r1; /* 0x78 */
-  __IO uint32_t apb1smen_r2; /* 0x7c */
-  __IO uint32_t apb2smen_r;  /* 0x80 */
-
-  __IO uint32_t reserved_8;
-
-  __IO uint32_t ccip_r; /* 0x88 */
-} PACKED rcc_t;
-
-#define RCC (*(__IO rcc_t*)RCC_BASE)
-
-/* Macros to operate on the RCC registers. */
-
-/* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */
-#define set_hse(rcc, e)        \
-  do {                         \
-    if (e) {                   \
-      (rcc).c_r |= 1 << 16;    \
-    } else {                   \
-      (rcc).c_r &= ~(1 << 16); \
-    }                          \
-  } while (0)
-
-/* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */
-#define set_hsi(rcc, e)       \
-  do {                        \
-    if (e) {                  \
-      (rcc).c_r |= 1 << 8;    \
-    } else {                  \
-      (rcc).c_r &= ~(1 << 8); \
-    }                         \
-  } while (0)
-
-/* Checks to see if the hse is ready. */
-#define hse_ready(rcc) ((rcc).c_r & (1 << 17))
-
-/* Checks to see if the hse is ready. */
-#define hsi_ready(rcc) ((rcc).c_r & (1 << 10))
-
-#endif
diff --git a/02.5-collatz/include/spin.h b/02.5-collatz/include/spin.h
deleted file mode 100644
index a23d25b..0000000
--- a/02.5-collatz/include/spin.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef H__SPIN_
-#define H__SPIN_
-
-#include <stdint.h>
-
-/*
- * Flash a code on the status LED.
- *
- * The flash codes a binary from MSB to LSB. A long flash is a 1, a short flash
- * is a 0. Each independent flashing is succeced by a break of 4 times that
- * of a long flash.
- */
-void spin(uint32_t base_delay, uint8_t code);
-
-#endif /* H__SPIN_ */
diff --git a/02.5-collatz/include/usart.h b/02.5-collatz/include/usart.h
deleted file mode 100644
index 257aab6..0000000
--- a/02.5-collatz/include/usart.h
+++ /dev/null
@@ -1,131 +0,0 @@
-#ifndef H__USART_
-#define H__USART_
-
-#include "common.h"
-#include "rcc.h"
-
-#include <stdint.h>
-
-/*
- * Possibel USART clock sources.
- */
-typedef enum {
-  USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */
-  USART_CLK_SRC_SYSCLK = 1, /* System clock. */
-  USART_CLK_SRC_HSI16 = 2, /* 16MHz oscillator. */
-  USART_CLK_SRC_LSE = 3 /* Low power 32kHz clock. */
-} usart_clk_src_t;
-
-typedef struct {
-  /* USART configuration registers 0x04 - 0x0c. */
-  union {
-    uint32_t c_r1;
-    struct {
-      bits_t ue:1;     /* UART enable */
-      bits_t uesm:1;   /* UART enabled in stop mode. */
-      bits_t re:1;     /* reciever enabled. */
-      bits_t te:1;     /* transmitter enabled. */
-      bits_t idleie:1; /* Idle interrupt enabled. */
-      bits_t rxneie:1; /* RXNEIE RXNE interrupt enable. */
-      bits_t tcie:1;
-      bits_t txeie:1;
-      bits_t peie:1;
-      bits_t ps:1;
-      bits_t pce:1;
-      bits_t wake:1;
-      bits_t m0:1;
-      bits_t mme:1;
-      bits_t cmie:1;
-      bits_t over8:1;
-      bits_t dedt:4;
-      bits_t deat:4;
-      bits_t rtoie:1;
-      bits_t eobie:1;
-      bits_t m1:1;
-      bits_t reserved:3;
-    } PACKED c1_bf;
-  };
-  uint32_t c_r2;
-  uint32_t c_r3;
-
-  /* USART baud rate register. */
-  uint32_t br_r;
-  uint32_t gtp_r;
-  uint32_t rto_r;
-  uint32_t rq_r;
-  uint32_t is_r;
-  uint32_t ic_r;
-  uint32_t rd_r;
-  uint32_t td_r;
-} usart_t;
-
-#define USART1 (* (__IO usart_t*) 0x40013800)
-#define USART2 (* (__IO usart_t*) 0x40004400)
-typedef enum {
-  OVERSAMPLE_8,
-  OVERSAMPLE_16
-} oversampling_mode_t;
-
-static inline void usart_set_divisor(
-    __IO usart_t* usart,
-    uint32_t usartdiv)
-{
-  if (usart->c_r1 & (1 << 15)) {
-    /* OVER8 is set. */
-    usart->br_r =
-      (usartdiv & ~7) |
-      ((usartdiv & 7) >> 1);
-  } else {
-    /* OVER8 is not set. */
-    usart->br_r = usartdiv;
-  }
-}
-
-static inline void usart_set_oversampling_mode(
-    __IO usart_t* usart,
-    oversampling_mode_t mode)
-{
-  if (mode == OVERSAMPLE_8) {
-    usart->c_r1 |= 1 << 15;
-  } else {
-    usart->c_r1 &= ~(1 << 15);
-  }
-}
-
-typedef enum {
-  USART_PARITY_DISABLED = 0,
-  USART_PARITY_EVEN     = 2 << 9,
-  USART_PARITY_ODD      = 3 << 9,
-} usart_parity_t;
-
-typedef enum {
-  USART_ENABLE_TX       = 0x02,
-  USART_ENABLE_RX       = 0x01,
-  USART_ENABLE_DISABLED = 0x00,
-} usart_enable_t;
-
-void usart_set_parity(__IO usart_t* usart, usart_parity_t parity);
-
-void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled);
-
-/*
- * Send a byte on the usart, This command blocks until the data
- * is fully sent.
- */
-void usart_transmit_byte(__IO usart_t* usart, uint8_t byte);
-
-void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src);
-
-void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable);
-
-void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src);
-
-void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable);
-
-void usart_transmit_bytes(
-    __IO usart_t* usart, const uint8_t* bytes, uint32_t n);
-
-void usart_transmit_str(__IO usart_t* usart, const char* str);
-
-
-#endif /* H__USART_ */
diff --git a/02.5-collatz/linker/linker_script.ld b/02.5-collatz/linker/linker_script.ld
deleted file mode 100644
index 348d03b..0000000
--- a/02.5-collatz/linker/linker_script.ld
+++ /dev/null
@@ -1,36 +0,0 @@
-MEMORY
-{
-  flash : org = 0x08000000, len = 256k
-  sram1 : org = 0x20000000, len = 48k
-  sram2 : org = 0x10000000, len = 16k
-}
-
-SECTIONS
-{
-  /* This is where the code goes. */
-  . = ORIGIN(flash);
-  .text : {
-    *(.vectors); /* All .vector sections go here. */
-    *(.text);    /* All .text sections go here. */
-  } >flash
-
-  .data : {
-    /* Data segment as defined in the flash. */
-    INIT_DATA_VALUES = LOADADDR(.data);
-
-    /* Data segment where it will be in memory. */
-    DATA_SEGMENT_START = .;
-    *(.data);
-    DATA_SEGMENT_STOP = .;
-
-    /* Align by 4 so we can optimize the copier to use uint32's. */
-    . = ALIGN(0x04);
-  } >sram1 AT>flash
-
-  BSS_START = .;
-  .bss : {
-    *(.bss);
-    . = ALIGN(0x04);
-  } > sram1
-  BSS_END = .;
-}
diff --git a/02.5-collatz/src/clock.c b/02.5-collatz/src/clock.c
deleted file mode 100644
index 75bac97..0000000
--- a/02.5-collatz/src/clock.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * This file sets the system clock to its full glory of 80Mhz
- */
-
-#include "clock.h"
-#include <stdint.h>
-#include "flash.h"
-#include "gpio.h"
-#include "spin.h"
-
-#define TIMEOUT 10000
-
-int pll_off()
-{
-  uint32_t c;
-
-  RCC.c_r &= ~BIT(24); /* Turn off pll. */
-  for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c)
-    ; /* Wait for OFF. */
-
-  if (c == TIMEOUT) {
-    return E_TIMEOUT;
-  }
-
-  return 0;
-}
-
-int pll_on()
-{
-  uint32_t c;
-
-  RCC.c_r |= BIT(24); /* Turn on PLL. */
-  for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c)
-    ; /* Wait for RDY. */
-
-  if (c == TIMEOUT) {
-    return E_TIMEOUT;
-  }
-
-  return 0;
-}
-
-int configure_pll(
-    uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */
-    pll_divisor_t pllq,  /* Divison factor for PLL48M1CLK. */
-    pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */
-    uint8_t plln,        /* PLL numerator. */
-    pllm_divisor_t pllm, /* PLL denominator. */
-    pll_src_t pllsrc /* PLL source */)
-{
-  if (RCC.c_r & BIT(25)) {
-    /* PLL must be off to configure it. */
-    return E_NOT_OFF;
-  }
-
-  /* Make sure inputs are valid. */
-  if (pllp_div_factor == 1 || pllp_div_factor > 31) {
-    return E_BADPLLP_DIV;
-  }
-  if (plln < 8 || plln > 86) {
-    return E_BADPLLN;
-  }
-
-  RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) |
-                 (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0);
-
-  return 0;
-}
-
-int set_system_clock_MHz(uint8_t mhz)
-{
-  /* Set the source of the system colck to MSI temporarily. */
-  set_system_clock_src(SYSTEM_CLOCK_SRC_MSI);
-
-  if (mhz <= 8 || mhz > 80) {
-    return E_BAD_ARG;
-  }
-
-  pll_off();
-
-  configure_pll(
-      0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */,
-      PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */,
-
-      /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz.
-       */
-      mhz /* plln    | mhz */, PLLM_DIVISOR_1 /* pllm    | 01 */,
-      PLL_SRC_MSI /* pll src | 04 Mhz */);
-
-  pll_on();
-
-  /* Configure the flash to have 4 wait states. This is required at
-   * 80 MHz. */
-  FLASH.ac_r &= ~0x07;
-  FLASH.ac_r |= 0x04;
-
-  /* Set the source of the system colck to PLL. */
-  set_system_clock_src(SYSTEM_CLOCK_SRC_PLL);
-  return 0;
-}
-
-int set_system_clock_src(system_clock_src_t src)
-{
-  uint8_t value = RCC.cfg_r & ~0x03;
-  RCC.cfg_r = value | src;
-}
diff --git a/02.5-collatz/src/delay.c b/02.5-collatz/src/delay.c
deleted file mode 100644
index 2a16d47..0000000
--- a/02.5-collatz/src/delay.c
+++ /dev/null
@@ -1,9 +0,0 @@
-#include "delay.h"
-
-void delay(uint32_t delay)
-{
-  while (delay--) {
-    /* needed to keep the compiler from optimizing away the loop. */
-    asm volatile("");
-  }
-}
diff --git a/02.5-collatz/src/gpio.c b/02.5-collatz/src/gpio.c
deleted file mode 100644
index 02933b7..0000000
--- a/02.5-collatz/src/gpio.c
+++ /dev/null
@@ -1,52 +0,0 @@
-#include "gpio.h"
-#include "rcc.h"
-
-/*
- * Sets the mode of a pin on a gpio por.
- */
-void set_gpio_pin_mode(
-    __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode)
-{
-  /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */
-  gpio_port->mode_r &= ~(0x03 << pin * 2);
-  gpio_port->mode_r |= mode << pin * 2;
-}
-
-gpio_output_pin_t set_gpio_pin_output(
-    __IO gpio_port_t* gpio_port, gpio_pin_t pin)
-{
-  set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT);
-
-  return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin};
-}
-
-void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff)
-{
-  if (onoff) {
-    pin.gpio_port->output_r |= 1 << pin.pin;
-  } else {
-    pin.gpio_port->output_r &= ~(1 << pin.pin);
-  }
-}
-
-void set_gpio_alternate_function(
-    __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn)
-{
-  __IO uint32_t* reg;
-  if (gpio_pin < 8) {
-    reg = &(port->af_rl);
-  } else {
-    reg = &(port->af_rh);
-    gpio_pin -= 8;
-  }
-
-  uint32_t tmp = *reg & (~0x0f << gpio_pin * 4);
-  *reg = tmp | (afn << gpio_pin * 4);
-}
-
-#define GPIO_PORTS_BASE_ADDR ((uint8_t*)0x48000000)
-__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number)
-{
-  RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */
-  return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400));
-}
diff --git a/02.5-collatz/src/isr_vector.c b/02.5-collatz/src/isr_vector.c
deleted file mode 100644
index ab38dc2..0000000
--- a/02.5-collatz/src/isr_vector.c
+++ /dev/null
@@ -1,165 +0,0 @@
-#include "isr_vector.h"
-#include "delay.h"
-#include "gpio.h"
-
-/* Forward-declare the main function. This is implemented in main.c. */
-void main();
-
-/* These are defined in the linker script. */
-extern uint32_t INIT_DATA_VALUES;
-extern uint32_t DATA_SEGMENT_START;
-extern uint32_t DATA_SEGMENT_STOP;
-extern uint32_t BSS_START;
-extern uint32_t BSS_END;
-
-/*
- * Runs before main. Initializes the data and bss segments by loading them
- * into memory.
- */
-void init()
-{
-  uint32_t* src;
-  uint32_t* dest;
-
-  src = &INIT_DATA_VALUES;
-  dest = &DATA_SEGMENT_START;
-
-  /* Copy the values from flash into the data segment. */
-  while (dest != &DATA_SEGMENT_STOP) {
-    *(dest++) = *(src++);
-  }
-
-  /* Everything in the BSS segment is set to zero. */
-  dest = &BSS_START;
-  while (dest != &BSS_END) {
-    *(dest++) = 0;
-  }
-
-  /* Jump to main. */
-  main();
-}
-
-const void* vectors[] __attribute__((section(".vectors"))) = {
-    (void*)0x2000c000, /* Top of stack at top of sram1. 48k */
-    init,              /* Reset handler */
-    unhandled_isr,     /* NMI */
-    unhandled_isr,     /* Hard Fault */
-    unhandled_isr,     /* MemManage */
-    unhandled_isr,     /* BusFault  */
-    unhandled_isr,     /* UsageFault */
-    unhandled_isr,     /* Reserved */
-    unhandled_isr,     /* Reserved */
-    unhandled_isr,     /* Reserved */
-    unhandled_isr,     /* Reserved */
-    unhandled_isr,     /* SVCall */
-    unhandled_isr,     /* Debug */
-    unhandled_isr,     /* Reserved */
-    unhandled_isr,     /* PendSV */
-    unhandled_isr,     /* SysTick */
-
-    /* External interrupt handlers follow */
-    unhandled_isr, /* 0 WWDG */
-    unhandled_isr, /* 1 PVD */
-    unhandled_isr, /* 2 TAMP_SAMP */
-    unhandled_isr, /* 3 RTC_WKUP */
-    unhandled_isr, /* 4 FLASH */
-    unhandled_isr, /* 5 RCC */
-    unhandled_isr, /* 6 EXTI0 */
-    unhandled_isr, /* 7 EXTI1 */
-    unhandled_isr, /* 8 EXTI2 */
-    unhandled_isr, /* 9 EXTI3 */
-    unhandled_isr, /* 10 EXTI4 */
-    unhandled_isr, /* 11 DMA_CH1 */
-    unhandled_isr, /* 12 DMA_CH2 */
-    unhandled_isr, /* 13 DMA_CH3 */
-    unhandled_isr, /* 14 DMA_CH4 */
-    unhandled_isr, /* 15 DMA_CH5 */
-    unhandled_isr, /* 16 DMA_CH6 */
-    unhandled_isr, /* 17 DMA_CH7 */
-    unhandled_isr, /* 18 ADC1 */
-    unhandled_isr, /* 19 CAN_TX */
-    unhandled_isr, /* 20 CAN_RX0 */
-    unhandled_isr, /* 21 CAN_RX1 */
-    unhandled_isr, /* 22 CAN_SCE */
-    unhandled_isr, /* 23 EXTI9_5 */
-    unhandled_isr, /* 24 TIM1_BRK/TIM15 */
-    unhandled_isr, /* 25 TIM1_UP/TIM16 */
-    unhandled_isr, /* 26 TIM1_TRG_COM */
-    unhandled_isr, /* 27 TIM1_CC */
-    unhandled_isr, /* 28 TIM2 */
-    unhandled_isr, /* 29 Reserved */
-    unhandled_isr, /* 30 Reserved */
-    unhandled_isr, /* 31 I2C1_EV */
-    unhandled_isr, /* 32 I2C1_ER */
-    unhandled_isr, /* 33 I2C2_EV */
-    unhandled_isr, /* 34 I2C2_ER */
-    unhandled_isr, /* 35 SPI1 */
-    unhandled_isr, /* 36 SPI2 */
-    unhandled_isr, /* 37 USART1 */
-    unhandled_isr, /* 38 USART2 */
-    unhandled_isr, /* 39 USART3 */
-    unhandled_isr, /* 40 EXTI15_10 */
-    unhandled_isr, /* 41 RTCAlarm */
-    unhandled_isr, /* 42 Reserved */
-    unhandled_isr, /* 43 Reserved */
-    unhandled_isr, /* 44 Reserved */
-    unhandled_isr, /* 45 Reserved */
-    unhandled_isr, /* 46 Reserved */
-    unhandled_isr, /* 47 Reserved */
-    unhandled_isr, /* 48 Reserved */
-    unhandled_isr, /* 49 SDMMC1 */
-    unhandled_isr, /* 50 Reserved */
-    unhandled_isr, /* 51 SPI3 */
-    unhandled_isr, /* 52 Reserved */
-    unhandled_isr, /* 53 Reserved */
-    unhandled_isr, /* 54 TIM6_DACUNDER */
-    unhandled_isr, /* 55 TIM7 */
-    unhandled_isr, /* 56 DMA2_CH1 */
-    unhandled_isr, /* 57 DMA2_CH2 */
-    unhandled_isr, /* 58 DMA2_CH3 */
-    unhandled_isr, /* 59 DMA2_CH4 */
-    unhandled_isr, /* 60 DMA2_CH5 */
-    unhandled_isr, /* 61 Reserved */
-    unhandled_isr, /* 62 Reserved */
-    unhandled_isr, /* 63 Reserved*/
-    unhandled_isr, /* 64 COMP */
-    unhandled_isr, /* 65 LPTIM1 */
-    unhandled_isr, /* 66 LPTIM2 */
-    unhandled_isr, /* 67 USB_FS */
-    unhandled_isr, /* 68 DMA_CH6 */
-    unhandled_isr, /* 69 DMA_CH7 */
-    unhandled_isr, /* 70 LPUART1 */
-    unhandled_isr, /* 71 QUADSPI */
-    unhandled_isr, /* 72 I2C3_EV */
-    unhandled_isr, /* 73 I2C3_ER */
-    unhandled_isr, /* 74 SAI1 */
-    unhandled_isr, /* 75 Reserved */
-    unhandled_isr, /* 76 SWPMI1 */
-    unhandled_isr, /* 77 TSC */
-    unhandled_isr, /* 78 Reserved */
-    unhandled_isr, /* 79 AES */
-    unhandled_isr, /* 80 RNG */
-    unhandled_isr, /* 81 FPU */
-    unhandled_isr  /* 82 CRS */
-};
-
-/*
- * Does nothing ... forever.
- */
-void unhandled_isr()
-{
-  __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B);
-  gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3);
-  for (;;) {
-    /* Flash in a distinct pattern to know that something went wrong. */
-
-    pin_off(pin3);
-    delay(1000000);
-    pin_on(pin3);
-    delay(1000000);
-    pin_off(pin3);
-    delay(1000000);
-    pin_on(pin3);
-    delay(5000000);
-  }
-}
diff --git a/02.5-collatz/src/main.c b/02.5-collatz/src/main.c
deleted file mode 100644
index 5af52ed..0000000
--- a/02.5-collatz/src/main.c
+++ /dev/null
@@ -1,93 +0,0 @@
-
-#include "clock.h"
-#include "delay.h"
-#include "gpio.h"
-#include "spin.h"
-#include "usart.h"
-
-volatile uint32_t delay_amt = 20000000 / 4;
-
-int enable_usart2(uint32_t baud_rate)
-{
-  __IO gpio_port_t* port_a = enable_gpio(GPIO_PORT_A);
-  enable_hsi(&RCC, true);
-
-  // Turn on the clock for the USART2 peripheral
-  set_usart2_clock_src(&RCC, USART_CLK_SRC_HSI16);
-  set_usart2_clock_enabled(&RCC, true);
-
-  // Configure the I/O pins.  Will use PA2 as TX and PA15 as RX so setup for
-  // alternate function
-  set_gpio_pin_mode(port_a, PIN_2, MODE_ALTERNATE);
-  set_gpio_pin_mode(port_a, PIN_15, MODE_ALTERNATE);
-  set_gpio_alternate_function(port_a, PIN_2, AFN_7);
-  set_gpio_alternate_function(port_a, PIN_15, AFN_3);
-
-  // De-assert reset of USART2
-  RCC.apb1rst1_r &= ~BIT(17);
-
-  // Configure the USART
-  // disable USART first to allow setting of other control bits
-  // This also disables parity checking and enables 16 times oversampling
-
-  USART2.c_r1 = 0;
-  USART2.c_r2 = 0;
-  USART2.c_r3 = 0;
-
-  usart_set_divisor(&USART2, 16000000 / baud_rate);
-  usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX);
-}
-
-int enable_usart1(uint32_t baud_rate)
-{
-  /* Enable the GPIO bus. */
-  __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B);
-
-  /* Enable the USART clock. */
-  RCC.apb2en_r |= BIT(14);
-
-  /* == Configure the IO Pins. == */
-
-  /* GPIO D5 (Port B pin 6) is USART1 Tx,
-   * GPIO D6 (Port B pin 7) is USART1 Rx. */
-  set_gpio_pin_mode(port_b, PIN_6, MODE_ALTERNATE);
-  set_gpio_pin_mode(port_b, PIN_7, MODE_ALTERNATE);
-
-  /* Set the GPIO pins to use the USART alternate function. */
-  set_gpio_alternate_function(port_b, PIN_6, AFN_7);
-  set_gpio_alternate_function(port_b, PIN_7, AFN_7);
-
-  RCC.apb2rst_r &= ~BIT(14); /* De-assert reset of USART1 */
-
-  uint32_t baud_rate_div = 80000000 / baud_rate;
-  USART1.c_r1 = 0;
-  USART1.c_r2 = 0;
-  USART1.c_r3 = 0;
-  USART1.br_r = baud_rate_div;
-
-  USART1.c_r1 |= BIT(3) | BIT(2);
-  USART1.c_r1 |= BIT(0);
-
-  /* Enable the transmitter and the receiver. */
-  usart_set_enabled(&USART1, USART_ENABLE_TX);
-  asm volatile(" cpsie i ");
-}
-
-/* Main function. This gets executed from the interrupt vector defined above. */
-int main()
-{
-  /* Enable the GPIO port B. */
-
-  __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B);
-  gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3);
-  gpio_output_pin_t pin1 = set_gpio_pin_output(port_b, PIN_1);
-
-  /* Enable a higher clock frequency. */
-  set_system_clock_MHz(80);
-
-  enable_usart2(115200);
-
-  pin_on(pin3);
-  usart_transmit_str(&USART2, "Hello, World\n");
-  for(;;);
-}
diff --git a/02.5-collatz/src/spin.c b/02.5-collatz/src/spin.c
deleted file mode 100644
index fbd16b6..0000000
--- a/02.5-collatz/src/spin.c
+++ /dev/null
@@ -1,49 +0,0 @@
-#include "spin.h"
-#include "delay.h"
-#include "gpio.h"
-
-#define SHORT_DELAY 200000
-#define LONG_DELAY (SHORT_DELAY * 2)
-
-static void flash_bit(
-    uint32_t base, gpio_output_pin_t out_pin,
-    uint8_t bit /* 0 => 0, non-zero => 1 */)
-{
-  pin_on(out_pin);
-  if (bit) {
-    delay(base * 2);
-  } else {
-    delay(base);
-  }
-  pin_off(out_pin);
-  delay(base);
-}
-
-void spin(uint32_t base, uint8_t c)
-{
-  uint8_t code;
-  __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B);
-  gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3);
-
-  for (;;) {
-    code = c;
-    flash_bit(base, pin3, code & 0x80);
-    code <<= 1;
-    flash_bit(base, pin3, code & 0x80);
-    code <<= 1;
-    flash_bit(base, pin3, code & 0x80);
-    code <<= 1;
-    flash_bit(base, pin3, code & 0x80);
-
-    code <<= 1;
-    flash_bit(base, pin3, code & 0x80);
-    code <<= 1;
-    flash_bit(base, pin3, code & 0x80);
-    code <<= 1;
-    flash_bit(base, pin3, code & 0x80);
-    code <<= 1;
-    flash_bit(base, pin3, code & 0x80);
-
-    delay(base * 4);
-  }
-}
diff --git a/02.5-collatz/src/usart.c b/02.5-collatz/src/usart.c
deleted file mode 100644
index eddfbe7..0000000
--- a/02.5-collatz/src/usart.c
+++ /dev/null
@@ -1,80 +0,0 @@
-#include "usart.h"
-#include "delay.h"
-
-void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src)
-{
-  rcc->ccip_r = rcc->ccip_r & (~0x03) | usart_clk_src;
-}
-
-void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src)
-{
-  rcc->ccip_r = rcc->ccip_r & ~(0x03 << 2) | (usart_clk_src << 2);
-}
-
-void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable)
-{
-  if (enable) {
-    rcc->apb1en1_r |= BIT(17);
-  } else {
-    rcc->apb1en1_r &= ~BIT(17);
-  }
-}
-
-void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable)
-{
-  if (enable) {
-    rcc->apb2en_r |= BIT(14);
-  } else {
-    rcc->apb2en_r &= ~BIT(14);
-  }
-}
-
-void usart_set_parity(__IO usart_t* usart, usart_parity_t parity)
-{
-  uint32_t c_r1 = usart->c_r1;
-  c_r1 &= ~(0x3 << 9);
-  c_r1 |= parity;
-  usart->c_r1 = c_r1;
-}
-
-void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled)
-{
-  uint32_t c_r1 = usart->c_r1;
-
-  if (!enabled) {
-    usart->c1_bf.ue = 0;
-  } else {
-    /* Set the rx enabled. */
-    usart->c1_bf.re = !!(enabled & USART_ENABLE_RX);
-    usart->c1_bf.te = !!(enabled & USART_ENABLE_TX);
-    usart->c1_bf.ue = 1;
-  }
-}
-
-void usart_transmit_byte(__IO usart_t* usart, uint8_t byte)
-{
-  usart->td_r = byte;
-  /* Per the manual, when bit 7 of the IS register is set, then the usart
-   * data has been sent to the shift register.
-   *
-   * This bit is cleared by writing to the TD register. */
-  while (!(usart->is_r & BIT(7)))
-    ;
-}
-
-void usart_transmit_bytes(__IO usart_t* usart, const uint8_t* bytes, uint32_t n)
-{
-  while (n --) {
-    usart_transmit_byte(usart, *(bytes ++));
-  }
-}
-
-void usart_transmit_str(__IO usart_t* usart, const char* str)
-{
-  while (*str) {
-    if (*str == '\n') {
-      usart_transmit_byte(usart, '\r');
-    }
-    usart_transmit_byte(usart, *(str ++));
-  }
-}
diff --git a/02.5-collatz/src/vector.c b/02.5-collatz/src/vector.c
deleted file mode 100644
index e69de29..0000000
--- a/02.5-collatz/src/vector.c
+++ /dev/null