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authorJosh Rahm <joshuarahm@gmail.com>2018-01-24 00:12:03 -0700
committerJosh Rahm <joshuarahm@gmail.com>2018-01-24 00:12:03 -0700
commit80360c4b8361320b726897c86ee13f9b4caf004a (patch)
tree9a590055e440025d7d36701a540d9e7e39c082d4 /03-refactor/include/rcc.h
parent2545ae2d57e5b70975e3fd3b3e570da13dbf62f0 (diff)
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More fields in USART and RCC set to use bitfields.
Diffstat (limited to '03-refactor/include/rcc.h')
-rw-r--r--03-refactor/include/rcc.h119
1 files changed, 88 insertions, 31 deletions
diff --git a/03-refactor/include/rcc.h b/03-refactor/include/rcc.h
index b2abcd2..827d66f 100644
--- a/03-refactor/include/rcc.h
+++ b/03-refactor/include/rcc.h
@@ -6,6 +6,20 @@
#define RCC_BASE ((uint32_t)0x40021000)
+typedef enum {
+ SYS_CLK_SW_MSI,
+ SYS_CLK_SW_HSI,
+ SYS_CLK_SW_HSE,
+ SYS_CLK_SW_PLL,
+} sys_clk_sw_t;
+
+typedef enum {
+ PLL_SRC_NONE,
+ PLL_SRC_MSI,
+ PLL_SRC_HSI,
+ PLL_SRC_HSE
+} pll_src_t;
+
typedef struct {
/* Clock control register. Offset 0x00. */
union RCC_CR {
@@ -41,9 +55,80 @@ typedef struct {
} PACKED;
} __IO c;
- __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */
- __IO uint32_t cfg_r; /* clock confguration register. 0x08 */
- __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */
+ /* Internal clock sources calibration register (RCC_ICSCR) Offset 0x04. */
+ union RCC_ICSCR {
+ __IO uint32_t r; /* 32 bit register. */
+
+ /* Bit field for icsc_r. */
+ struct {
+ bits_t msical:8;
+ bits_t msitrim:8;
+ bits_t hsical:8;
+ bits_t hsitrim:5;
+
+ RESERVED(3);
+ } PACKED;
+ } __IO icscr;
+
+
+ /* Clock configuration register. */
+ union RCC_CFGR {
+ __IO uint32_t r;
+
+ /* Bitfields for cfg_r. */
+ struct {
+ sys_clk_sw_t sw:2; /* System clock switch. @see sys_clk_sw_t enum. */
+ sys_clk_sw_t sws:2; /* System clock switch status. */
+
+ bits_t hpre:4; /* AHB prescaler. */
+ bits_t ppre:3; /* APB low-speed prescaller. */
+
+ RESERVED(1);
+
+ bits_t stopwuck:1; /* Wakeup from Stop and CSS backup clock selection. */
+ bits_t mcosel:4; /* Microcontroller clock output. */
+ bits_t mcopre:3; /* MCO prescaller. */
+
+ RESERVED(1);
+ } PACKED __IO;
+ } __IO cfg;
+
+ /* PLL Configuration register. Offset 0x0c */
+ union RCC_PLLCFGR {
+ __IO uint32_t r;
+
+ /* Bitfields for pllcfg_r */
+ struct {
+ pll_src_t pllsrc:2; /* PLL input source clock. */
+
+ RESERVED(2);
+
+ bits_t pllm:3; /* Divisions factor for the main PLL and audio PLL */
+
+ RESERVED(1);
+
+ bits_t plln:7; /* main PLL multiplication factor for VCO, must be
+ * on interval [8, 86] inclusive */
+ RESERVED(1);
+
+ bits_t pllpen:1; /* Main PLL PLLSAI1CLK output enable. */
+ bits_t pllp:1; /* Main division factor for PLLP.
+ * 0 = 7, 1 = 17 */
+ RESERVED(2);
+
+ bits_t pllqen:1; /* Main PLL PLL48M1CLK output enabled. */
+ bits_t pllq:2; /* PLLQ division factor. in 2^x. */
+
+ RESERVED(1);
+
+ bits_t pllren:1; /* PLL PLLCLK enabled. */
+ bits_t pllr:2; ; /* main pll divion factor. 2^x. */
+
+ bits_t pllpdiv:5; /* PLLP division factor. 0 to be handled by PLLP. */
+
+ } PACKED __IO;
+ } __IO pllcfg;
+
__IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */
__IO uint32_t reserved_1; /* Not used. offset 0x14. */
@@ -95,32 +180,4 @@ typedef struct {
#define RCC (*(__IO rcc_t*)RCC_BASE)
-/* Macros to operate on the RCC registers. */
-
-/* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */
-#define set_hse(rcc, e) \
- do { \
- if (e) { \
- (rcc).c_r |= 1 << 16; \
- } else { \
- (rcc).c_r &= ~(1 << 16); \
- } \
- } while (0)
-
-/* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */
-#define set_hsi(rcc, e) \
- do { \
- if (e) { \
- (rcc).c_r |= 1 << 8; \
- } else { \
- (rcc).c_r &= ~(1 << 8); \
- } \
- } while (0)
-
-/* Checks to see if the hse is ready. */
-#define hse_ready(rcc) ((rcc).c_r & (1 << 17))
-
-/* Checks to see if the hse is ready. */
-#define hsi_ready(rcc) ((rcc).c_r & (1 << 10))
-
#endif