Add the System Control Block (SCB) in system.h.

5 files changed, 98 insertions, 1 deletions

diff --git a/02-usart/include/arch/arm/arch.h b/02-usart/include/arch/arm/arch.h
index 6c10213..a136b4a 100644
--- a/02-usart/include/arch/arm/arch.h
+++ b/02-usart/include/arch/arm/arch.h
@@ -1,8 +1,11 @@
 #ifndef ARCH_H_
 #define ARCH_H_
 
-
+#ifndef ARCH_STM32L4
 #define ARCH_STM32L4
+#endif
+
+#define CORTEX_M4
 
 #define enable_interrupts() \
   asm volatile(" cpsie i ")
@@ -21,7 +24,11 @@
 #define SRAM1_BASE (0x20000000)
 #define SRAM2_BASE (0x2000C000)
 
+#define SYSTEM_CONFIG_BLOCK_BASE (0xE000E008)
+
 #include <stdint.h>
+#ifndef DRY_RUN
 _Static_assert(sizeof(void*) == sizeof(uint32_t), "Pointers must be 32 bits");
+#endif
 
 #endif /* ARCH_H_ */
diff --git a/02-usart/include/arch/x86_64/arch.h b/02-usart/include/arch/x86_64/arch.h
index 2b99239..6723eea 100644
--- a/02-usart/include/arch/x86_64/arch.h
+++ b/02-usart/include/arch/x86_64/arch.h
@@ -19,4 +19,6 @@
 #define SRAM1_BASE (load_fake_sram1__() + 0x0)
 #define SRAM2_BASE (load_fake_sram2__() + 0x0)
 
+#define SYSTEM_CONFIG_BLOCK_BASE (load_fake_scb__())
+
 #endif /* ARCH_H_ */
diff --git a/02-usart/include/system.h b/02-usart/include/system.h
new file mode 100644
index 0000000..f2a4de9
--- /dev/null
+++ b/02-usart/include/system.h
@@ -0,0 +1,84 @@
+#ifndef SYSTEM_H_
+#define SYSTEM_H_
+
+#include <stdint.h>
+#include "common.h"
+
+typedef __IO struct {
+  uint32_t actl_r; /* Auxiliary Control Register, ACTLR on page 4-5 */
+
+  uint32_t reserved0;
+
+  union {
+    uint32_t stcs_r; /* SysTick Control and Status Register */
+    struct {
+      bits_t enable:1;
+      bits_t tickint:1;
+      bits_t clksource:1;
+
+      bits_t reserved0:13;
+
+      bits_t countflag:1;
+
+      bits_t reserved1:15;
+    } stcs_bf;
+  };
+  uint32_t strv_r; /* SysTick Reload Value Register */
+  uint32_t stcv_r; /* SysTick Current Value Register */
+  uint32_t stc_r;  /* SysTick Calibration Value Register */
+
+  uint8_t reserved1[3296];
+
+  uint32_t cpuid; /* CPUID Base Register, CPUID on page 4-5 */
+  uint32_t ics_r; /* RO 0x00000000 Interrupt Control and State Register */
+  uint32_t vto_r; /* Vector Table Offset Register */
+  uint32_t airc_r; /* Application Interrupt and Reset Control Register */
+  uint32_t sc_r; /* System Control Register */
+  uint32_t cc_r; /* Configuration and Control Register. */
+  uint32_t shp_r1; /* System Handler Priority Register 1 */
+  uint32_t shp_r2; /* System Handler Priority Register 2 */
+  uint32_t shp_r3; /* System Handler Priority Register 3 */
+  uint32_t shcs_r; /* System Handler Control and State Register */
+  uint32_t cfs_r; /* Configurable Fault Status Registers */
+  uint32_t hfs_r; /* HardFault Status register */
+  uint32_t dfs_r; /* Debug Fault Status Register */
+  uint32_t mmfa_r; /* MemManage Address Registerb */
+  uint32_t bfa_r; /* BusFault Address Registerb */
+  uint32_t afs_r; /* Auxiliary Fault Status Register, AFSR on page 4-6 */
+  uint32_t id_pf_r0; /* Processor Feature Register 0 */
+  uint32_t id_pf_r1; /* Processor Feature Register 1 */
+  uint32_t id_df_r0; /* Debug Features Register 0 */
+  uint32_t id_af_r0; /* Auxiliary Features Register 0 */
+  uint32_t id_mmf_r0; /* Memory Model Feature Register 0 */
+  uint32_t id_mmf_r1; /* 0x00000000 Memory Model Feature Register 1 */
+  uint32_t id_mmf_r2; /* Memory Model Feature Register 2 */
+  uint32_t id_mmf_r3; /* Memory Model Feature Register 3 */
+  uint32_t id_isa_r0; /* Instruction Set Attributes Register 0 */
+  uint32_t id_isa_r1; /* Instruction Set Attributes Register 1 */
+  uint32_t id_isa_r2; /* Instruction Set Attributes Register 2 */
+  uint32_t id_isa_r3; /* Instruction Set Attributes Register 3 */
+  uint32_t id_isa_r4; /* Instruction Set Attributes Register 4 */
+  
+  uint8_t reserved2[20];
+
+  uint32_t cpac_r; /* Coprocessor Access Control Register */
+
+  uint8_t reserved3[372];
+
+  uint32_t sti_r; /* Software Triggered Interrupt Register */
+} system_control_block_t;
+
+#define ARM_SYSCFG_BASE 0xE000E008
+#define CHECK_OFFSET(member, expected) \
+  static_assert(ARM_SYSCFG_BASE + offsetof(system_control_block_t, member) == expected, \
+      "Offset check failed")
+
+CHECK_OFFSET(stcs_r, 0xE000E010);
+CHECK_OFFSET(cpuid, 0xE000ED00);
+CHECK_OFFSET(cpac_r, 0xE000ED88);
+CHECK_OFFSET(id_mmf_r3, 0xE000ED5C);
+CHECK_OFFSET(sti_r,  0xE000EF00);
+
+#define SCB (*(system_control_block_t*)SYSTEM_CONFIG_BLOCK_BASE)
+
+#endif
diff --git a/02-usart/test_harness/fake_env.c b/02-usart/test_harness/fake_env.c
index 45cb1e9..f9c2a4d 100644
--- a/02-usart/test_harness/fake_env.c
+++ b/02-usart/test_harness/fake_env.c
@@ -20,6 +20,9 @@ DEFINE_MEMORY_SEGMENT(apb2, 0x40010000, 0x40020000)
 DEFINE_MEMORY_SEGMENT(ahb1, 0x40020000, 0x40024400)
 DEFINE_MEMORY_SEGMENT(ahb2, 0x48000000, 0x50060C00)
 
+/* System Control Block */
+DEFINE_MEMORY_SEGMENT(scb,  0xE000E008, 0xE000EF04)
+
 /* SRAM */
 DEFINE_MEMORY_SEGMENT(sram1, 0x20000000, 0x2000C000)
 DEFINE_MEMORY_SEGMENT(sram2, 0x2000C000, 0x20018000)
diff --git a/02-usart/test_harness/fake_env.h b/02-usart/test_harness/fake_env.h
index 12c09ff..09891bc 100644
--- a/02-usart/test_harness/fake_env.h
+++ b/02-usart/test_harness/fake_env.h
@@ -9,5 +9,6 @@ void* load_fake_apb1__();
 void* load_fake_apb2__();
 void* load_fake_sram1__();
 void* load_fake_sram2__();
+void* load_fake_scb__();
 
 #endif /* FAKE_ENV_H_ */