Double the SPI bandwith by writing only 8 bits to the spi data register instead of 16 (with 8 leading 0's).

2 files changed, 10 insertions, 6 deletions

diff --git a/include/arch/stm32l4xxx/peripherals/spi.h b/include/arch/stm32l4xxx/peripherals/spi.h
index e5b44fe..478664e 100644
--- a/include/arch/stm32l4xxx/peripherals/spi.h
+++ b/include/arch/stm32l4xxx/peripherals/spi.h
@@ -92,7 +92,15 @@ typedef __IO struct {
   /* spi data register. Really only the least-significant 16 bits are used.
    * reading from this register reads from the Rx FIFO while writing to it
    * writes to the Tx FIFO. */
-  __IO uint32_t d_r;
+  union {
+    /* The lower 8 its of the spi data register. */
+    __IO uint8_t dl_r;
+
+    /* The data register. */
+    __IO uint16_t d_r;
+  };
+
+  __IO uint16_t unused;
 
   /* spi CRC polynomial register. */
   uint32_t crcp_r;
diff --git a/src/kern/main.c b/src/kern/main.c
index 9d93247..c76d025 100644
--- a/src/kern/main.c
+++ b/src/kern/main.c
@@ -98,7 +98,7 @@ static void spi_write(uint8_t byte)
 {
   while (!regget(SPI1.s_r, spi_txe))
     ;
-  SPI1.d_r = byte;
+  SPI1.dl_r = byte;
   asm volatile("nop");
 }
 
@@ -106,8 +106,6 @@ static void write_rgb(uint8_t red, uint8_t green, uint8_t blue)
 {
 #undef BIT
 #define BIT(b, n) (!!((b) & (1 << (n))))
-  spi_write(0);
-
   spi_write(
       (1 << 7) | (BIT(green, 7) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
       (BIT(green, 6) << 2) | (0 << 1) | (0 << 0));
@@ -146,8 +144,6 @@ static void write_rgb(uint8_t red, uint8_t green, uint8_t blue)
   spi_write(
       (1 << 7) | (BIT(blue, 1) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
       (BIT(blue, 0) << 2) | (0 << 1) | (0 << 0));
-
-  spi_write(0);
 }
 
 void latch()