Added NVIC definition

5 files changed, 46 insertions, 5 deletions

diff --git a/02-usart/include/arch/arm/arch.h b/02-usart/include/arch/arm/arch.h
index a136b4a..a3b93dc 100644
--- a/02-usart/include/arch/arm/arch.h
+++ b/02-usart/include/arch/arm/arch.h
@@ -25,6 +25,7 @@
 #define SRAM2_BASE (0x2000C000)
 
 #define SYSTEM_CONFIG_BLOCK_BASE (0xE000E008)
+#define NVIC_BASE (0xE000E004)
 
 #include <stdint.h>
 #ifndef DRY_RUN
diff --git a/02-usart/include/arch/x86_64/arch.h b/02-usart/include/arch/x86_64/arch.h
index 6723eea..a39df9a 100644
--- a/02-usart/include/arch/x86_64/arch.h
+++ b/02-usart/include/arch/x86_64/arch.h
@@ -20,5 +20,6 @@
 #define SRAM2_BASE (load_fake_sram2__() + 0x0)
 
 #define SYSTEM_CONFIG_BLOCK_BASE (load_fake_scb__())
+#define NVIC_BASE (load_fake_nvic__())
 
 #endif /* ARCH_H_ */
diff --git a/02-usart/include/common.h b/02-usart/include/common.h
index 2f14e42..653279e 100644
--- a/02-usart/include/common.h
+++ b/02-usart/include/common.h
@@ -44,4 +44,7 @@ typedef __IO uint32_t bits_t;
 #define regset(reg, mask, val) \
   ((reg) = ((reg) & ~mask) | (val << CTZ(mask)))
 
+#define regget(reg, mask) \
+  (((reg) & mask) >> (CTZ(mask)))
+
 #endif /* COMMON_H */
diff --git a/02-usart/src/main.c b/02-usart/src/main.c
index 4602fd3..6d22486 100644
--- a/02-usart/src/main.c
+++ b/02-usart/src/main.c
@@ -5,6 +5,8 @@
 #include "core/gpio.h"
 #include "core/system.h"
 #include "core/usart.h"
+#include "core/nvic.h"
+
 #include "delay.h"
 #include "mem.h"
 #include "spin.h"
@@ -59,20 +61,48 @@ int main()
   set_system_clock_MHz(80);
 
   setup_usart2(115200);
+  regset(USART2.c_r1, usart_txeie, 1);
+  regset(USART2.c_r1, usart_rxneie, 1);
   usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX);
+  USART2.td_r = (uint8_t) 0x61;
+
+  __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B);
+  gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3);
+  pin_on(pin3);
+
+  usart_printf(&USART2, "\nUSART2.c_r1: %p\n", USART2.c_r1);
+  usart_printf(&USART2, "NVIC intlinesnum: %d\n",
+      regget(NVIC.ict_r, nvic_intlinesnum));
+
+  int off = 1;
+  int last;
+  for(;;) {
+    int next = USART2.is_r & usart_rxne;
+    volatile int y = USART2.rd_r;
+    if (next)
+      USART2.td_r = y;
+    if (last != next) {
+      if (off) {
+        pin_on(pin3);
+      } else {
+        pin_off(pin3);
+      }
+      off = !off;
+    }
+  }
 
-  usart_printf(&USART2, "Start Configuring Countdown!\n");
+  // usart_printf(&USART2, "Start Configuring Countdown!\n");
 
   /* Set the countdown to start from 1,000,0000. */
-  SCB.strv_r = 10000000;
+  // SCB.strv_r = 10000000;
 
   /* Enable interrupts. */
-  regset(SCB.stcs_r, scb_tickint, 1);
+  // regset(SCB.stcs_r, scb_tickint, 1);
 
   /* Start the systick. */
-  regset(SCB.stcs_r, scb_enable, 1);
+  // regset(SCB.stcs_r, scb_enable, 1);
 
-  usart_printf(&USART2, "Start Countdown Started!\n");
+  // usart_printf(&USART2, "Start Countdown Started!\n");
 }
 
 #endif
diff --git a/02-usart/test_harness/fake_env.c b/02-usart/test_harness/fake_env.c
index f9c2a4d..d1dba35 100644
--- a/02-usart/test_harness/fake_env.c
+++ b/02-usart/test_harness/fake_env.c
@@ -23,6 +23,12 @@ DEFINE_MEMORY_SEGMENT(ahb2, 0x48000000, 0x50060C00)
 /* System Control Block */
 DEFINE_MEMORY_SEGMENT(scb,  0xE000E008, 0xE000EF04)
 
+/* Nested Vector Interrupt Controller (NVIC) */
+/* Note that this memory space acutally overlaps with the SCB, but
+ * they are functionally distinct entitites and such are modeled as
+ * separate structures in memeory. */
+DEFINE_MEMORY_SEGMENT(nvic, 0xE000E004, 0xE000E4F0)
+
 /* SRAM */
 DEFINE_MEMORY_SEGMENT(sram1, 0x20000000, 0x2000C000)
 DEFINE_MEMORY_SEGMENT(sram2, 0x2000C000, 0x20018000)