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authorJosh Rahm <joshuarahm@gmail.com>2020-11-24 13:46:41 -0700
committerJosh Rahm <joshuarahm@gmail.com>2020-11-24 13:46:41 -0700
commit93b063fedfcf7409a67df035170ea5670cad22e1 (patch)
treea23321a7465d966b1ccf196ca00e65a70c9f9110 /include/arch/stm32l4xxx/peripherals/gpio.h
parentb040195d31df6ad759f16ea3456471897f55daa1 (diff)
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Moved action to top level.
Removed old iterations of the project and moved the files from 02-usart to the root directory since that's the sole place where the action is and that subproject has outgrown its initial title.
Diffstat (limited to 'include/arch/stm32l4xxx/peripherals/gpio.h')
-rw-r--r--include/arch/stm32l4xxx/peripherals/gpio.h66
1 files changed, 66 insertions, 0 deletions
diff --git a/include/arch/stm32l4xxx/peripherals/gpio.h b/include/arch/stm32l4xxx/peripherals/gpio.h
new file mode 100644
index 0000000..944d725
--- /dev/null
+++ b/include/arch/stm32l4xxx/peripherals/gpio.h
@@ -0,0 +1,66 @@
+#ifndef CORE_GPIO_H__
+#define CORE_GPIO_H__
+
+#include "kern/common.h"
+#include "arch/stm32l4xxx/peripherals/rcc.h"
+
+#include <stdint.h>
+
+/*
+ * Structure defining the layout of the layout of the GPIO registers on the
+ * stm32l432 development board.
+ */
+typedef struct GPIO_PORT_STR {
+ /* Mode of each GPIO pin for this GPIO port. */
+#define gpio_mode_n(off) (3 << ((off) * 2))
+ __IO uint32_t mode_r; /* Mode register */
+
+ /* Output type for each gpio pin in this port. */
+#define gpio_otype_n(off) (1 << (off))
+ __IO uint32_t otype_r;
+
+ /* GPIO port output speed. */
+#define gpio_ospeed_n(off) (3 << ((off) * 2))
+ __IO uint32_t ospeed_r;
+
+ /* GPIO port pull-up/pull-down register */
+#define gpio_pupd_n(off) (3 << ((off) * 2))
+ __IO uint32_t pupd_r;
+
+ /* GPIO port input data register. */
+#define gpio_idr_n(off) (1 << (off))
+ __IO uint32_t id_r;
+
+ /* GPIO port output data register. */
+#define gpio_odr_n(off) (1 << (off))
+ __IO uint32_t od_r;
+
+ /* GPIO port bit set/reset register. */
+#define gpio_bs_n(off) (1 << (off))
+#define gpio_br_n(off) (1 << (off))
+ __IO uint32_t bsr_r;
+
+ /* GPIO port configuration lock register. */
+#define gpio_lck_n(off) (1 << (off))
+#define gpio_lckk (1 << 16)
+ __IO uint32_t lck_r;
+
+ /* Alternate function low-register. */
+#define gpio_afsel_n(off) (0xf << ((off) * 4))
+ __IO uint32_t af_rl;
+ /* Alternate function high-register. */
+ __IO uint32_t af_rh;
+
+ /* GPIO port bit register. */
+#define gpio_br_n(off) (1 << (off))
+ __IO uint32_t br_r;
+
+ /* Analog switch control register. */
+#define gpio_asc_n(off) (1 << (off))
+ __IO uint32_t asc_r;
+} PACKED gpio_port_config_t;
+
+static_assert(
+ offsetof(gpio_port_config_t, asc_r) == 0x2C, "Offset check failed");
+
+#endif