Add module for controlling the MPU.

The MPU is a module in arm chips which allow for memory access
protection. They are more primitive than full MMUs, but can still
provide at least basic access control between different process
controls.

3 files changed, 52 insertions, 0 deletions

diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h
index bf96fae..e4ebb8d 100644
--- a/include/arch/arm/arch.h
+++ b/include/arch/arm/arch.h
@@ -13,6 +13,12 @@
 #define disable_all_interrupts() \
   asm volatile(" cpsid i ")
 
+#define __isb() \
+  asm volatile(" isb ")
+
+#define __dsb() \
+  asm volatile(" dsb ")
+
 
 #define DMA1_BASE (0x40020000)
 #define DMA2_BASE (0x40020400)
@@ -36,6 +42,7 @@
 #define SPI3_BASE (0x40003C00)
 
 #define STACK_TOP (0x2000c000)
+#define MPU_BASE (0xE000ED90)
 
 #include <stdint.h>
 #ifndef DRY_RUN
diff --git a/include/arch/arm/cortex-m4/mpu.h b/include/arch/arm/cortex-m4/mpu.h
new file mode 100644
index 0000000..fedaf79
--- /dev/null
+++ b/include/arch/arm/cortex-m4/mpu.h
@@ -0,0 +1,40 @@
+#ifndef ARCH_ARM_CORTEX_M4_MPU_H_
+#define ARCH_ARM_CORTEX_M4_MPU_H_
+
+#include "arch.h"
+
+typedef volatile struct {
+  volatile uint32_t type_r;
+#define mpu_en (1 << 0)
+  volatile uint32_t ctrl_r;
+  volatile uint32_t rn_r;
+
+  /**
+   * On the ARM Cortex-M4 processor, the
+   */
+  volatile union {
+#define mpu_size (0x1F << 1)
+#define mpu_srd (0xFF << 8)
+#define mpu_b (1 << 16)
+#define mpu_c (1 << 17)
+#define mpu_s (1 << 18)
+#define mpu_tex (7 << 19)
+#define mpu_ap (3 << 24)
+#define mpu_xn (1 << 28)
+
+#define mpu_valid (1 << 4)
+#define mpu_region (0xF << 0)
+    struct {
+      uint32_t rba_r;
+      uint32_t ras_r;
+    };
+    struct {
+      uint32_t rba_r;
+      uint32_t ras_r;
+    } aliased[4];
+  };
+} mpu_t;
+
+#define MPU (*((mpu_t*)(MPU_BASE)))
+
+#endif /* ARCH_ARM_CORTEX_M4_MPU_H_ */
diff --git a/include/arch/x86_64/arch.h b/include/arch/x86_64/arch.h
index 62ef730..ab26d1e 100644
--- a/include/arch/x86_64/arch.h
+++ b/include/arch/x86_64/arch.h
@@ -5,8 +5,11 @@
 #include "fake_env.h"
 
 #define ARCH_PC
+
 #define enable_all_interrupts() do {} while(0)
 #define disable_all_interrupts() do {} while(0)
+#define __isb() do {} while(0)
+#define __dsb() do {} while(0)
 
 #define RCC_BASE (load_fake_rcc__())
 
@@ -30,6 +33,8 @@
 #define SPI1_BASE (load_fake_spi1__())
 #define SPI3_BASE (load_fake_spi3__())
 
+#define MPU_BASE (load_fake_mpu__())
+
 // Pretend there's a data segement at the start of SRAM1 for more accurate
 // testing.
 #define GHOST_DATA_SEGMENT_SIZE 1200