Added kernel-level abstraction over the spi interface.

5 files changed, 252 insertions, 43 deletions

diff --git a/include/arch/stm32l4xxx/peripherals/rcc.h b/include/arch/stm32l4xxx/peripherals/rcc.h
index 65b2e86..cb04b94 100644
--- a/include/arch/stm32l4xxx/peripherals/rcc.h
+++ b/include/arch/stm32l4xxx/peripherals/rcc.h
@@ -80,8 +80,39 @@ typedef struct {
 
   __IO uint32_t reserved_5; /* Not used. offset 0x54. */
 
+#define rcc_lptim1en (1 << 31) /* Low power timer 1 clock enable */
+#define rcc_opampen (1 << 30) /* OPAMP interface clock enable */
+#define rcc_dac1en (1 << 29) /* DAC1 interface clock enable */
+#define rcc_pwren (1 << 28) /* Power interface clock enable */
+#define rcc_can2en (1 << 26) /* CAN2 clock enable (this bit is reserved for STM32L47x/L48x devices) */
+#define rcc_can1en (1 << 25) /* CAN1 clock enable */
+#define rcc_crsen (1 << 24) /* Clock Recovery System clock enable (this bit is reserved for STM32L47x/L48x */
+#define rcc_i2c3en (1 << 23) /* I2C3 clock enable */
+#define rcc_i2c2en (1 << 22) /* I2C2 clock enable */
+#define rcc_i2c1en (1 << 21) /* I2C1 clock enable */
+#define rcc_uart5en (1 << 20) /* UART5 clock enable */
+#define rcc_uart4en (1 << 19) /* UART4 clock enable */
+#define rcc_usart3en (1 << 18) /* USART3 clock enable */
+#define rcc_usart2en (1 << 17) /* USART2 clock enable */
+#define rcc_spi3en (1 << 15) /* SPI3 clock enable */
+#define rcc_spi2en (1 << 14) /* SPI2 clock enable */
+#define rcc_wwdgen (1 << 11) /* Window watchdog clock enable */
+#define rcc_rtcapben (1 << 10) /* RTC APB clock enable (this bit is reserved for STM32L47x/L48x devices) */
+#define rcc_lcden (1 << 9) /* LCD clock enable (this bit is reserved for STM32L471/L4x5 devices) */
+#define rcc_tim7en (1 << 5) /* TIM7 timer clock enable */
+#define rcc_tim6en (1 << 4) /* TIM6 timer clock enable */
+#define rcc_tim5en (1 << 3) /* TIM5 timer clock enable */
+#define rcc_tim4en (1 << 2) /* TIM4 timer clock enable */
+#define rcc_tim3en (1 << 1) /* TIM3 timer clock enable */
+#define rcc_tim2en (1 << 0) /* TIM2 timer clock enable */
   __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */
+
+#define lptim2en (1 << 5) /*Low power timer 2 clock enable */
+#define swpmi1en (1 << 2) /* Single wire protocol clock enable */
+#define i2c4en (1 << 1) /* I2C4 clock enable (this bit is reserved for STM32L47x/L48x devices) */
+#define lpuart1en (1 << 0) /* Low power UART 1 clock enable */
   __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */
+
 #define rcc_syscfgen (1 << 0)
 #define rcc_fwen (1 << 7)
 #define rcc_sdmmc1en (1 << 10)
diff --git a/include/arch/stm32l4xxx/peripherals/spi.h b/include/arch/stm32l4xxx/peripherals/spi.h
index 478664e..eb9741e 100644
--- a/include/arch/stm32l4xxx/peripherals/spi.h
+++ b/include/arch/stm32l4xxx/peripherals/spi.h
@@ -4,38 +4,38 @@
 #include "kern/common.h"
 #include "arch.h"
 
-#define SPI1 (*((spi_t*)(SPI1_BASE)))
-#define SPI3 (*((spi_t*)(SPI3_BASE)))
+#define SPI1 (*((spi_regs_t*)(SPI1_BASE)))
+#define SPI3 (*((spi_regs_t*)(SPI3_BASE)))
 
 typedef enum {
-  SPI_BAUD_FPCLK_DIV_2   = 0,
-  SPI_BAUD_FPCLK_DIV_4   = 1,
-  SPI_BAUD_FPCLK_DIV_8   = 2,
-  SPI_BAUD_FPCLK_DIV_16  = 3,
-  SPI_BAUD_FPCLK_DIV_32  = 4,
-  SPI_BAUD_FPCLK_DIV_64  = 5,
-  SPI_BAUD_FPCLK_DIV_128 = 6,
-  SPI_BAUD_FPCLK_DIV_256 = 7,
+  SPI_BAUD_RATE_FPCLK_DIV_2   = 0,
+  SPI_BAUD_RATE_FPCLK_DIV_4   = 1,
+  SPI_BAUD_RATE_FPCLK_DIV_8   = 2,
+  SPI_BAUD_RATE_FPCLK_DIV_16  = 3,
+  SPI_BAUD_RATE_FPCLK_DIV_32  = 4,
+  SPI_BAUD_RATE_FPCLK_DIV_64  = 5,
+  SPI_BAUD_RATE_FPCLK_DIV_128 = 6,
+  SPI_BAUD_RATE_FPCLK_DIV_256 = 7,
 } spi_baud_rate_t;
 
 typedef enum {
-  SPI_DATA_SIZE_NOT_USED_0  = 0,
-  SPI_DATA_SIZE_NOT_USED_1  = 1,
-  SPI_DATA_SIZE_NOT_USED_2  = 2,
-  SPI_DATA_SIZE_4_BITS      = 3,
-  SPI_DATA_SIZE_5_BITS      = 4,
-  SPI_DATA_SIZE_6_BITS      = 5,
-  SPI_DATA_SIZE_7_BITS      = 6,
-  SPI_DATA_SIZE_8_BITS      = 7,
-  SPI_DATA_SIZE_9_BITS      = 8,
-  SPI_DATA_SIZE_10_BITS     = 9,
-  SPI_DATA_SIZE_11_BITS     = 10,
-  SPI_DATA_SIZE_12_BITS     = 11,
-  SPI_DATA_SIZE_13_BITS     = 12,
-  SPI_DATA_SIZE_14_BITS     = 13,
-  SPI_DATA_SIZE_15_BITS     = 14,
-  SPI_DATA_SIZE_16_BITS     = 15,
-} spi_data_size_t;
+  SPI_REG_DATA_SIZE_NOT_USED_0  = 0,
+  SPI_REG_DATA_SIZE_NOT_USED_1  = 1,
+  SPI_REG_DATA_SIZE_NOT_USED_2  = 2,
+  SPI_REG_DATA_SIZE_4_BITS      = 3,
+  SPI_REG_DATA_SIZE_5_BITS      = 4,
+  SPI_REG_DATA_SIZE_6_BITS      = 5,
+  SPI_REG_DATA_SIZE_7_BITS      = 6,
+  SPI_REG_DATA_SIZE_8_BITS      = 7,
+  SPI_REG_DATA_SIZE_9_BITS      = 8,
+  SPI_REG_DATA_SIZE_10_BITS     = 9,
+  SPI_REG_DATA_SIZE_11_BITS     = 10,
+  SPI_REG_DATA_SIZE_12_BITS     = 11,
+  SPI_REG_DATA_SIZE_13_BITS     = 12,
+  SPI_REG_DATA_SIZE_14_BITS     = 13,
+  SPI_REG_DATA_SIZE_15_BITS     = 14,
+  SPI_REG_DATA_SIZE_16_BITS     = 15,
+} spi_reg_data_size_t;
 
 typedef enum {
   SPI_FIFO_STATUS_EMPTY = 0,
@@ -110,8 +110,8 @@ typedef __IO struct {
 
   /* spi tx CRC register. */
   uint32_t txcrc_r;
-} spi_t;
+} spi_regs_t;
 
-static_assert(offsetof(spi_t, txcrc_r) == 0x18, "Offset check failed.");
+static_assert(offsetof(spi_regs_t, txcrc_r) == 0x18, "Offset check failed.");
 
 #endif /* CORE_SPI_H_ */
diff --git a/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc
new file mode 100644
index 0000000..5a91e8b
--- /dev/null
+++ b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc
@@ -0,0 +1,2 @@
+SPI(SPI1, SPI1)
+SPI(SPI2, SPI3) /* Stm32l432 doesn't have a SPI2. */
diff --git a/include/kern/common.h b/include/kern/common.h
index c5afe3f..021229b 100644
--- a/include/kern/common.h
+++ b/include/kern/common.h
@@ -1,9 +1,11 @@
 #ifndef COMMON__H
 #define COMMON__H
 
-#include <stdint.h>
-#include <stddef.h>
 #include <assert.h>
+#include <stddef.h>
+#include <stdint.h>
+
+typedef enum { ENDIANNESS_LITTLE, ENDIANNESS_BIG } endianness_t;
 
 #define WEAK __attribute__((weak))
 #define NORETURN __attribute__((noreturn))
@@ -28,23 +30,18 @@
 #define PACKED __attribute__((packed))
 #define BIT(n) (1 << (n))
 
-#define RESERVED_CONCAT_IMPL(x, y) x ## y
+#define RESERVED_CONCAT_IMPL(x, y) x##y
 #define RESERVED_MACRO_CONCAT(x, y) RESERVED_CONCAT_IMPL(x, y)
-#define RESERVED(n) \
-  bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) :n
-  
-#define RESERVE(type) \
-  __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__)
+#define RESERVED(n) bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) : n
+
+#define RESERVE(type) __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__)
 
-#define ptr2reg(ptr) \
-  ((uint32_t) (ptrdiff_t) (ptr))
+#define ptr2reg(ptr) ((uint32_t)(ptrdiff_t)(ptr))
 
 typedef __IO uint32_t bits_t;
 
-#define regset(reg, mask, val) \
-  ((reg) = ((reg) & ~mask) | (val << CTZ(mask)))
+#define regset(reg, mask, val) ((reg) = ((reg) & ~mask) | (val << CTZ(mask)))
 
-#define regget(reg, mask) \
-  (((reg) & mask) >> (CTZ(mask)))
+#define regget(reg, mask) (((reg)&mask) >> (CTZ(mask)))
 
 #endif /* COMMON_H */
diff --git a/include/kern/spi/spi_manager.h b/include/kern/spi/spi_manager.h
new file mode 100644
index 0000000..53e4c2a
--- /dev/null
+++ b/include/kern/spi/spi_manager.h
@@ -0,0 +1,179 @@
+#ifndef KERN_SPI_SPI_MANAGER_H_
+#define KERN_SPI_SPI_MANAGER_H_
+
+#include "kern/common.h"
+
+#define SPI_ERROR_ALREADY_IN_USE 1
+#define SPI_ERROR_SELECTION_NOT_VALID 2
+
+typedef enum { SPI_CRCL_8_BITS, SPI_CRCL_16_BITS } spi_crcl_t;
+
+typedef enum {
+  SPI_DATA_SIZE_NOT_USED_0  = 0,
+  SPI_DATA_SIZE_NOT_USED_1  = 1,
+  SPI_DATA_SIZE_NOT_USED_2  = 2,
+  SPI_DATA_SIZE_4_BITS      = 3,
+  SPI_DATA_SIZE_5_BITS      = 4,
+  SPI_DATA_SIZE_6_BITS      = 5,
+  SPI_DATA_SIZE_7_BITS      = 6,
+  SPI_DATA_SIZE_8_BITS      = 7,
+  SPI_DATA_SIZE_9_BITS      = 8,
+  SPI_DATA_SIZE_10_BITS     = 9,
+  SPI_DATA_SIZE_11_BITS     = 10,
+  SPI_DATA_SIZE_12_BITS     = 11,
+  SPI_DATA_SIZE_13_BITS     = 12,
+  SPI_DATA_SIZE_14_BITS     = 13,
+  SPI_DATA_SIZE_15_BITS     = 14,
+  SPI_DATA_SIZE_16_BITS     = 15,
+} spi_data_size_t;
+
+typedef enum {
+  SPI_BAUD_FPCLK_DIV_2 = 0,
+  SPI_BAUD_FPCLK_DIV_4 = 1,
+  SPI_BAUD_FPCLK_DIV_8 = 2,
+  SPI_BAUD_FPCLK_DIV_16 = 3,
+  SPI_BAUD_FPCLK_DIV_32 = 4,
+  SPI_BAUD_FPCLK_DIV_64 = 5,
+  SPI_BAUD_FPCLK_DIV_128 = 6,
+  SPI_BAUD_FPCLK_DIV_256 = 7,
+} spi_baud_t;
+
+typedef enum { SPI_MODE_MASTER, SPI_MODE_SLAVE } spi_mode_t;
+
+typedef enum { SPI_POLARITY_0, SPI_POLARITY_1 } spi_polarity_t;
+
+typedef enum {
+  /* The first clock transition is the first data capture edge. */
+  SPI_CLOCK_PHASE_FIRST,
+  /* The second clock transition is the first data capture edge. */
+  SPI_CLOCK_PHASE_SECOND,
+} spi_clock_phase_t;
+
+typedef enum {
+  SPI_DMA_PARITY_EVEN,
+  SPI_DMA_PARITY_ODD,
+} spi_dma_parity_t;
+
+typedef enum {
+  SPI_FIFO_THRESHOLD_HALF,
+  SPI_FIFO_THRESHOLD_QUARTER,
+} spi_fifo_threshold_t;
+
+typedef enum {
+  SPI_FRAME_FORMAT_MOTOROLA,
+  SPI_FRAME_FORMAT_TI,
+} spi_frame_format_t;
+
+typedef struct {
+  bool enable_bidirectional_data_mode;
+
+  /* Enable hardware crc checking. */
+  bool enable_crc;
+
+  /* CRC length. */
+  spi_crcl_t crc_length;
+
+  bool receieve_only;
+
+  bool enable_software_slave_management;
+
+  bool internal_slave_select;
+
+  endianness_t endianness;
+
+  spi_baud_t baud;
+
+  spi_mode_t spi_mode;
+
+  spi_polarity_t polarity;
+
+  spi_clock_phase_t clock_phase;
+
+  spi_dma_parity_t number_of_data_parity_tx;
+
+  spi_dma_parity_t number_of_data_parity_rx;
+
+  spi_fifo_threshold_t rx_interrupt_fifo_threshold;
+
+  spi_data_size_t data_size;
+
+  bool enable_tx_buffer_empty_interrupt;
+
+  bool enable_rx_buffer_not_empty_interrupt;
+
+  bool enable_error_interrupt;
+
+  spi_frame_format_t frame_format;
+
+  bool enable_nss_pulse;
+
+  bool enable_ss_output;
+
+  bool enable_tx_dma;
+
+  bool enable_rx_dma;
+
+  union {
+    struct {
+      bool output_enable;
+    } bidir_opts_t;
+  };
+} spi_opts_t;
+
+#define DEFAULT_SPI_OPTS { \
+   .enable_bidirectional_data_mode = 0,\
+   .enable_crc = 0,\
+   .crc_length = SPI_CRCL_8_BITS,\
+   .receieve_only = 0,\
+   .enable_software_slave_management = 1,\
+   .internal_slave_select = 1,\
+   .endianness = ENDIANNESS_LITTLE,\
+   .baud = SPI_BAUD_FPCLK_DIV_32,\
+   .spi_mode = SPI_MODE_MASTER,\
+   .polarity = SPI_POLARITY_0,\
+   .clock_phase = SPI_CLOCK_PHASE_FIRST,\
+   .number_of_data_parity_tx = SPI_DMA_PARITY_EVEN,\
+   .number_of_data_parity_rx = SPI_DMA_PARITY_EVEN,\
+   .rx_interrupt_fifo_threshold = SPI_FIFO_THRESHOLD_HALF,\
+   .data_size = SPI_DATA_SIZE_8_BITS,\
+   .enable_tx_buffer_empty_interrupt = 0,\
+   .enable_rx_buffer_not_empty_interrupt = 0,\
+   .enable_error_interrupt = 0,\
+   .frame_format = SPI_FRAME_FORMAT_MOTOROLA,\
+   .enable_nss_pulse = 0,\
+   .enable_ss_output = 0,\
+   .enable_tx_dma = 0 ,\
+   .enable_rx_dma = 0,\
+}
+
+typedef struct spi spi_t;
+
+typedef enum {
+#define SPI(sp, u) SPI_SELECT_##sp,
+#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc"
+#undef SPI
+
+  N_SPI_SELECT
+} spi_select_t;
+
+/* Reserve a spi bus. If an error occurs, NULL is returned
+ * and *ec is set to the appropriate value. */
+spi_t* reserve_spi(spi_select_t spi_select, spi_opts_t* opts, int* ec);
+
+/* Sets the SPI to enable. */
+void spi_start(spi_t* spi);
+
+/* Release the spi bus.  */;
+void release_spi(spi_t* spi);
+
+void spi_set_crc_next(spi_t* spi);
+
+void spi_write_8_sync(spi_t* spi, uint8_t data);
+
+void spi_write_16_sync(spi_t* spi, uint16_t data);
+
+uint8_t spi_read_8_sync(spi_t* spi);
+
+uint16_t spi_read_16_sync(spi_t* spi);
+
+#endif /* KERN_SPI_SPI_MANAGER_H_ */