Add module for controlling the MPU.

The MPU is a module in arm chips which allow for memory access
protection. They are more primitive than full MMUs, but can still
provide at least basic access control between different process
controls.

5 files changed, 137 insertions, 1 deletions

diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h
index bf96fae..e4ebb8d 100644
--- a/include/arch/arm/arch.h
+++ b/include/arch/arm/arch.h
@@ -13,6 +13,12 @@
 #define disable_all_interrupts() \
   asm volatile(" cpsid i ")
 
+#define __isb() \
+  asm volatile(" isb ")
+
+#define __dsb() \
+  asm volatile(" dsb ")
+
 
 #define DMA1_BASE (0x40020000)
 #define DMA2_BASE (0x40020400)
@@ -36,6 +42,7 @@
 #define SPI3_BASE (0x40003C00)
 
 #define STACK_TOP (0x2000c000)
+#define MPU_BASE (0xE000ED90)
 
 #include <stdint.h>
 #ifndef DRY_RUN
diff --git a/include/arch/arm/cortex-m4/mpu.h b/include/arch/arm/cortex-m4/mpu.h
new file mode 100644
index 0000000..fedaf79
--- /dev/null
+++ b/include/arch/arm/cortex-m4/mpu.h
@@ -0,0 +1,40 @@
+#ifndef ARCH_ARM_CORTEX_M4_MPU_H_
+#define ARCH_ARM_CORTEX_M4_MPU_H_
+
+#include "arch.h"
+
+typedef volatile struct {
+  volatile uint32_t type_r;
+#define mpu_en (1 << 0)
+  volatile uint32_t ctrl_r;
+  volatile uint32_t rn_r;
+
+  /**
+   * On the ARM Cortex-M4 processor, the
+   */
+  volatile union {
+#define mpu_size (0x1F << 1)
+#define mpu_srd (0xFF << 8)
+#define mpu_b (1 << 16)
+#define mpu_c (1 << 17)
+#define mpu_s (1 << 18)
+#define mpu_tex (7 << 19)
+#define mpu_ap (3 << 24)
+#define mpu_xn (1 << 28)
+
+#define mpu_valid (1 << 4)
+#define mpu_region (0xF << 0)
+    struct {
+      uint32_t rba_r;
+      uint32_t ras_r;
+    };
+    struct {
+      uint32_t rba_r;
+      uint32_t ras_r;
+    } aliased[4];
+  };
+} mpu_t;
+
+#define MPU (*((mpu_t*)(MPU_BASE)))
+
+#endif /* ARCH_ARM_CORTEX_M4_MPU_H_ */
diff --git a/include/arch/x86_64/arch.h b/include/arch/x86_64/arch.h
index 62ef730..ab26d1e 100644
--- a/include/arch/x86_64/arch.h
+++ b/include/arch/x86_64/arch.h
@@ -5,8 +5,11 @@
 #include "fake_env.h"
 
 #define ARCH_PC
+
 #define enable_all_interrupts() do {} while(0)
 #define disable_all_interrupts() do {} while(0)
+#define __isb() do {} while(0)
+#define __dsb() do {} while(0)
 
 #define RCC_BASE (load_fake_rcc__())
 
@@ -30,6 +33,8 @@
 #define SPI1_BASE (load_fake_spi1__())
 #define SPI3_BASE (load_fake_spi3__())
 
+#define MPU_BASE (load_fake_mpu__())
+
 // Pretend there's a data segement at the start of SRAM1 for more accurate
 // testing.
 #define GHOST_DATA_SEGMENT_SIZE 1200
diff --git a/include/kern/common.h b/include/kern/common.h
index 653279e..c5afe3f 100644
--- a/include/kern/common.h
+++ b/include/kern/common.h
@@ -19,7 +19,7 @@
 
 #define CTZ(n) __builtin_ctz(n)
 
-#define bool int
+#define bool unsigned int
 #ifndef __cplusplus
 #define true 1
 #define false 0
diff --git a/include/kern/mpu/mpu_manager.h b/include/kern/mpu/mpu_manager.h
new file mode 100644
index 0000000..5e0bc7b
--- /dev/null
+++ b/include/kern/mpu/mpu_manager.h
@@ -0,0 +1,84 @@
+#ifndef KERN_MPU_MPU_MANAGER_H_
+#define KERN_MPU_MPU_MANAGER_H_
+
+#include "kern/common.h"
+
+typedef enum {
+  REGION_SIZE_32 = 4,
+  REGION_SIZE_64 = 5,
+  REGION_SIZE_128 = 6,
+  REGION_SIZE_256 = 7,
+  REGION_SIZE_512 = 8,
+  REGION_SIZE_1Kb = 9,
+  REGION_SIZE_2Kb = 10,
+  REGION_SIZE_4Kb = 11,
+  REGION_SIZE_8Kb = 12,
+  REGION_SIZE_16Kb = 13,
+  REGION_SIZE_32Kb = 14,
+  REGION_SIZE_64Kb = 15,
+  REGION_SIZE_128Kb = 16,
+  REGION_SIZE_256Kb = 17,
+  REGION_SIZE_512Kb = 18,
+  REGION_SIZE_1Mb = 19,
+  REGION_SIZE_2Mb = 20,
+  REGION_SIZE_4Mb = 21,
+  REGION_SIZE_8Mb = 22,
+  REGION_SIZE_16Mb = 23,
+  REGION_SIZE_32Mb = 24,
+  REGION_SIZE_64Mb = 25,
+  REGION_SIZE_128Mb = 26,
+  REGION_SIZE_256Mb = 27,
+  REGION_SIZE_512Mb = 28,
+  REGION_SIZE_1Gb = 29,
+  REGION_SIZE_2Gb = 30,
+  REGION_SIZE_4Gb = 31,
+} region_size_t;
+
+#define region_size_mask(region_size) ((1 << (region_size)) - 1)
+
+typedef enum {
+  /* Neither Privileged nor non-Privileged code cannnot access this region */
+  ACCESS_PERMS_NO_ACCESS = 0,
+
+  /* Only privileged users can access this memory. */
+  ACCESS_PERMS_ONLY_PERMS = 1,
+
+  /* Privileged code can access fully, but non-privilege only has Read-only
+     access.*/
+  ACCESS_NON_PERMS_RO = 2,
+
+  /* Both Privileged and non-Privileged code can access this region fully. */
+  ACCESS_PERMS_FULL = 3,
+
+  /* Only privileged users can access this memory, and only as Read-only. */
+  ACCESS_PERMS_ONLY_PRIV_RO = 5,
+
+  /* Both privileged and non-privileged users can access this memory, but only
+     as Read-only.*/
+  ACCESS_PERMS_BOTH_RO = 5,
+} access_perms_t;
+
+typedef struct {
+  region_size_t size;
+  uint8_t subregion_disable;
+
+  struct {
+    bool enable : 1;
+    bool sharable : 1;
+    bool cacheable : 1;
+    bool bufferable : 1;
+    bool executable : 1;
+    uint8_t tex : 3;
+  };
+
+  access_perms_t perms;
+  void* region;
+} memory_region_opts_t;
+
+void mpu_set_enabled(bool enabled);
+
+/* Configures a memory region. The region number must be on the interval [0,8).
+ */
+void mpu_configure_region(int region_number, memory_region_opts_t* opts);
+
+#endif /* KERN_MPU_MPU_MANAGER_H_ */