Update .clang-format and run it on filse

1 files changed, 11 insertions, 8 deletions

diff --git a/src/arch/stm32l4xxx/peripherals/clock.c b/src/arch/stm32l4xxx/peripherals/clock.c
index 9051572..32cd00c 100644
--- a/src/arch/stm32l4xxx/peripherals/clock.c
+++ b/src/arch/stm32l4xxx/peripherals/clock.c
@@ -3,14 +3,13 @@
  */
 
 #include "arch/stm32l4xxx/peripherals/clock.h"
-#include "arch/stm32l4xxx/peripherals/flash.h"
-
-#include "kern/init.h"
 
 #include <stdint.h>
 
-#define TIMEOUT 10000
+#include "arch/stm32l4xxx/peripherals/flash.h"
+#include "kern/init.h"
 
+#define TIMEOUT 10000
 
 int pll_off()
 {
@@ -43,7 +42,8 @@ int pll_on()
 }
 
 int configure_pll(
-    uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */
+    uint8_t pllp_div_factor,
+    pll_divisor_t pllr,  /* System clock divisor. */
     pll_divisor_t pllq,  /* Divison factor for PLL48M1CLK. */
     pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */
     uint8_t plln,        /* PLL numerator. */
@@ -89,12 +89,15 @@ int set_system_clock_MHz(uint8_t mhz)
   pll_off();
 
   configure_pll(
-      0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */,
-      PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */,
+      0 /* pllp_div_factor */,
+      PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */,
+      PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */,
+      PLLP_DIVISOR_7 /* pllp */,
 
       /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz.
        */
-      mhz /* plln    | mhz */, PLLM_DIVISOR_1 /* pllm    | 01 */,
+      mhz /* plln    | mhz */,
+      PLLM_DIVISOR_1 /* pllm    | 01 */,
       PLL_SRC_MSI /* pll src | 04 Mhz */);
 
   pll_on();