diff options
| author | Josh Rahm <joshuarahm@gmail.com> | 2020-11-26 01:17:44 -0700 |
|---|---|---|
| committer | Josh Rahm <joshuarahm@gmail.com> | 2020-11-26 01:17:44 -0700 |
| commit | 4b8b2de19ed10c84d7a298c05907a1471bdf7077 (patch) | |
| tree | 6bb0b62aa3ad69116e65fd632aa8e88ce29ca7a2 /src/kern/main.c | |
| parent | ee89199793683b3120a55f1c1887e12333c5ea7e (diff) | |
| download | stm32l4-4b8b2de19ed10c84d7a298c05907a1471bdf7077.tar.gz stm32l4-4b8b2de19ed10c84d7a298c05907a1471bdf7077.tar.bz2 stm32l4-4b8b2de19ed10c84d7a298c05907a1471bdf7077.zip | |
Basic SPI working.
Diffstat (limited to 'src/kern/main.c')
| -rw-r--r-- | src/kern/main.c | 83 |
1 files changed, 82 insertions, 1 deletions
diff --git a/src/kern/main.c b/src/kern/main.c index 4fddb0a..d4393f3 100644 --- a/src/kern/main.c +++ b/src/kern/main.c @@ -1,7 +1,10 @@ #include "arch.h" #include "arch/arm/cortex-m4/mpu.h" #include "arch/stm32l4xxx/peripherals/clock.h" +#include "arch/stm32l4xxx/peripherals/rcc.h" +#include "arch/stm32l4xxx/peripherals/spi.h" #include "arch/stm32l4xxx/peripherals/system.h" +#include "kern/gpio/gpio_manager.h" #include "kern/init.h" #include "kern/log.h" #include "kern/mem.h" @@ -35,7 +38,85 @@ void configure_mpu() int main() { configure_mpu(); - jump_to_user_mode(); + + int ec; + + // gpio_enable_alternate_function( + // GPIO_ALTERNATE_FUNCTION_SPI1_MISO, GPIO_PIN_PA6, &ec); + // if (ec) { + // klogf("Unable to set pin PA6 (ec=%d)\n", ec); + // } + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_SPI1_MOSI, GPIO_PIN_PA7, &ec); + if (ec) { + klogf("Unable to set pin PA7 (ec=%d)\n", ec); + } + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_SPI1_NSS, GPIO_PIN_PA4, &ec); + if (ec) { + klogf("Unable to set pin PA4 (ec=%d)\n", ec); + } + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_SPI1_SCK, GPIO_PIN_PA5, &ec); + if (ec) { + klogf("Unable to set pin PA5 (ec=%d)\n", ec); + } + + regset(RCC.apb2en_r, rcc_spi1en, 1); + + uint32_t reg = 0; + regset(reg, spi_ldma_tx, 0); + regset(reg, spi_ldma_rx, 0); + regset(reg, spi_frxth, 0); + regset(reg, spi_ds, SPI_DATA_SIZE_8_BITS); + regset(reg, spi_txeie, 0); + regset(reg, spi_rxneie, 0); + regset(reg, spi_errie, 0); + regset(reg, spi_frf, 0); + regset(reg, spi_nssp, 0); + regset(reg, spi_ssoe, 0); + regset(reg, spi_txdmaen, 0); + regset(reg, spi_rxdmaen, 0); + SPI1.c_r2 = reg; + + reg = 0; + regset(reg, spi_bidimode, 0); + regset(reg, spi_crcen, 0); + regset(reg, spi_crcnext, 0); + regset(reg, spi_crcl, 0); + regset(reg, spi_rxonly, 0); + regset(reg, spi_ssm, 1); + regset(reg, spi_ssi, 1); + regset(reg, spi_lsbfirst, 0); + regset(reg, spi_spe, 1); + regset(reg, spi_br, SPI_BAUD_FPCLK_DIV_256); + regset(reg, spi_mstr, 1); + regset(reg, spi_cpol, 0); + regset(reg, spi_cpha, 0); + SPI1.c_r1 = reg; + + uint8_t val = 0xf0; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + SPI1.d_r = val; + klogf("4 Spi Status %p\n", SPI1.s_r); + + for (;;) SPI1.d_r = val; + // for (;;) { + // klogf("Spi Status %p\n", SPI1.s_r); + // // while (!regget(SPI1.s_r, spi_txe)) + // // ; + // // klogf("Write\n"); + // // SPI1.d_r = val; + // } } #endif |