Added kernel-level abstraction over the spi interface.

2 files changed, 239 insertions, 119 deletions

diff --git a/src/kern/main.c b/src/kern/main.c
index c76d025..aeb884d 100644
--- a/src/kern/main.c
+++ b/src/kern/main.c
@@ -1,14 +1,13 @@
 #include "arch.h"
 #include "arch/arm/cortex-m4/mpu.h"
 #include "arch/stm32l4xxx/peripherals/clock.h"
+#include "arch/stm32l4xxx/peripherals/spi.h"
 #include "arch/stm32l4xxx/peripherals/dma.h"
 #include "arch/stm32l4xxx/peripherals/irq.h"
 #include "arch/stm32l4xxx/peripherals/rcc.h"
-#include "arch/stm32l4xxx/peripherals/spi.h"
 #include "arch/stm32l4xxx/peripherals/system.h"
 #include "drv/ws2812B/ws2812b.h"
 #include "kern/delay.h"
-#include "kern/systick/systick_manager.h"
 #include "kern/dma/dma_manager.h"
 #include "kern/gpio/gpio_manager.h"
 #include "kern/gpio/sysled.h"
@@ -18,6 +17,8 @@
 #include "kern/mpu/mpu_manager.h"
 #include "kern/panic.h"
 #include "kern/priv.h"
+#include "kern/spi/spi_manager.h"
+#include "kern/systick/systick_manager.h"
 #include "user/syscall.h"
 
 void on_hard_fault()
@@ -27,7 +28,7 @@ void on_hard_fault()
 
 #ifdef ARCH_STM32L4
 
-void configure_spi1()
+spi_t* configure_spi()
 {
   int ec = 0;
 
@@ -47,38 +48,16 @@ void configure_spi1()
     panic("Unable to set pin PA5 (ec=%d)\n", ec);
   }
 
-  regset(RCC.apb2en_r, rcc_spi1en, 1);
-
-  uint32_t reg = 0;
-  regset(reg, spi_ldma_tx, 0);
-  regset(reg, spi_ldma_rx, 0);
-  regset(reg, spi_frxth, 0);
-  regset(reg, spi_ds, SPI_DATA_SIZE_8_BITS);
-  regset(reg, spi_txeie, 0);
-  regset(reg, spi_rxneie, 0);
-  regset(reg, spi_errie, 0);
-  regset(reg, spi_frf, 0);
-  regset(reg, spi_nssp, 0);
-  regset(reg, spi_ssoe, 0);
-  regset(reg, spi_txdmaen, 0);
-  regset(reg, spi_rxdmaen, 0);
-  SPI1.c_r2 = reg;
-
-  reg = 0;
-  regset(reg, spi_bidimode, 0);
-  regset(reg, spi_crcen, 0);
-  regset(reg, spi_crcnext, 0);
-  regset(reg, spi_crcl, 0);
-  regset(reg, spi_rxonly, 0);
-  regset(reg, spi_ssm, 1);
-  regset(reg, spi_ssi, 1);
-  regset(reg, spi_lsbfirst, 0);
-  regset(reg, spi_spe, 1);
-  regset(reg, spi_br, SPI_BAUD_FPCLK_DIV_32);
-  regset(reg, spi_mstr, 1);
-  regset(reg, spi_cpol, 0);
-  regset(reg, spi_cpha, 0);
-  SPI1.c_r1 = reg;
+
+  spi_opts_t opts = DEFAULT_SPI_OPTS;
+  opts.endianness = ENDIANNESS_BIG;
+  spi_t* spi = reserve_spi(SPI_SELECT_SPI1, &opts, &ec);
+
+  if (ec) {
+    panic("Unable to reserve spi bus. (ec=%d)\n", ec);
+  }
+
+  return spi;
 }
 
 static uint8_t* compiled;
@@ -90,100 +69,100 @@ static uint32_t time;
 
 static void on_systick(void* nil)
 {
-  // klogf("Systick.\n");
   ++time;
 }
 
-static void spi_write(uint8_t byte)
-{
-  while (!regget(SPI1.s_r, spi_txe))
-    ;
-  SPI1.dl_r = byte;
-  asm volatile("nop");
-}
-
-static void write_rgb(uint8_t red, uint8_t green, uint8_t blue)
+static void write_rgb(spi_t* spi, uint8_t red, uint8_t green, uint8_t blue)
 {
 #undef BIT
 #define BIT(b, n) (!!((b) & (1 << (n))))
-  spi_write(
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(green, 7) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(green, 6) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(green, 6) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(green, 5) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(green, 4) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(green, 4) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(green, 3) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(green, 2) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(green, 2) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(green, 1) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(green, 0) << 2) | (0 << 1) | (0 << 0));
+          (BIT(green, 0) << 2) | (0 << 1) | (0 << 0));
 
-  spi_write(
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(red, 7) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(red, 6) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(red, 6) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(red, 5) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(red, 4) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(red, 4) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(red, 3) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(red, 2) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(red, 2) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(red, 1) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(red, 0) << 2) | (0 << 1) | (0 << 0));
+          (BIT(red, 0) << 2) | (0 << 1) | (0 << 0));
 
-  spi_write(
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(blue, 7) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(blue, 6) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(blue, 6) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(blue, 5) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(blue, 4) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(blue, 4) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(blue, 3) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(blue, 2) << 2) | (0 << 1) | (0 << 0));
-  spi_write(
+          (BIT(blue, 2) << 2) | (0 << 1) | (0 << 0));
+  spi_write_8_sync(
+      spi,
       (1 << 7) | (BIT(blue, 1) << 6) | (0 << 5) | (0 << 4) | (1 << 3) |
-      (BIT(blue, 0) << 2) | (0 << 1) | (0 << 0));
+          (BIT(blue, 0) << 2) | (0 << 1) | (0 << 0));
 }
 
-void latch()
+void latch(spi_t* spi)
 {
   for (int i = 0; i < 20; ++i) {
-    spi_write(0);
+    spi_write_8_sync(spi, 0);
   }
 }
 
+#define min(a, b) (a) < (b) ? (a) : (b)
+
 static uint8_t amp(uint8_t in)
 {
-  uint8_t out = in;
+  uint32_t out = in;
 
-  for (int i = 0; i < 10; ++ i) {
+  for (int i = 0; i < 20; ++i) {
     out = (out * in) / 256;
   }
 
-  return out;
+  return min(out, 255);
+}
+
+static uint32_t bytescale(uint32_t n, uint32_t sc)
+{
+  return n * sc / 255;
 }
 
 /* Main function. This gets executed from the interrupt vector defined above. */
 int main()
 {
+  klogf("Entering main\n");
   gpio_reserved_pin_t sysled = get_sysled();
 
-  klogf("Start\n");
-  klogf("sintable: %p\n", sintable);
-  klogf("sintable[5]: %d\n", sintable[5]);
-  klogf("Flashed with OpenOCD!\n");
-
   systick_add_callback(on_systick, NULL);
   enable_systick(1000);
 
-  /* Enable interrupts. */
-  regset(SCB.stcs_r, scb_tickint, 1);
-
-  /* Start the systick. */
-  regset(SCB.stcs_r, scb_enable, 1);
-
-#define SIZE 128
+#define SIZE 256
   rgb_t rgb[SIZE];
   for (int i = 0; i < SIZE; ++i) {
     rgb[i].g = 0xff;
@@ -191,57 +170,47 @@ int main()
     rgb[i].b = 0xff;
   }
 
-  uint8_t red = 0x40;
-  uint8_t green = 0x40;
-  uint8_t blue = 0x40;
-
-  // compiled = ws2812b_compile_rgb(rgb, SIZE);
-  // compiled_len = SIZE * 9;
+  uint32_t red = 0x40;
+  uint32_t green = 0x40;
+  uint32_t brightness = 255;
 
-  configure_spi1();
+  klogf("Configure Spi\n");
+  spi_t* spi = configure_spi();
+  klogf("Done Configuring Spi\n");
 
   for (int i = 0; i < 100; ++i) {
-    write_rgb(0, 0, 0);
+    write_rgb(spi, 0, 0, 0);
   }
 
-  latch();
+  klogf("Latch\n");
+  latch(spi);
 
   for (;;) {
     set_gpio_pin_high(sysled);
 
-    latch();
+    klogf("Frame\n");
+
+    latch(spi);
 
     int i;
     for (i = 0; i < SIZE; ++i) {
-      red = byte_sin((i * 4 * 2 + time / 1000) & 0xff) / 2;
-      green = byte_sin((i * 4 * 3 + time / 1000) & 0xff) / 2;
-      blue = 0;
-      // blue = amp(byte_sin((i * 2 * 3 + time / 1000) & 0xff)) / 2;
+      red = byte_sin(time / 1000 + i * 4);
+      green = 255 - red;
 
-      // uint8_t red = byte_sin((i * 8 + 64 + time / 100) & 0xff);
-      // uint8_t green = byte_sin((i * 8 + 0 + time / 100) & 0xff);
-      // uint32_t blue = (((red - 128) * (green - 128)) / 256) + 128;
+      brightness = 3 * byte_sin(time / 5000) / 4 + 63;
 
-      write_rgb(red, green, blue);
-    }
+      uint32_t white = amp(byte_sin(time / 6310 + i / 4));
 
-    // write_rgb(0,0,0);
-    // write_rgb(0,0,0);
-    // write_rgb(0,0,0);
-    // write_rgb(0,0,0);
-    // write_rgb(0,0,0);
-    // write_rgb(0,0,0);
-    // write_rgb(0,0,0);
-    // write_rgb(0,0,0);
-    // write_rgb(red, green, blue);
+      write_rgb(
+          spi,
+          bytescale(min(red + white, 255), brightness),
+          bytescale(min(green + white, 255), brightness),
+          bytescale(white, brightness));
+    }
 
     set_gpio_pin_low(sysled);
 
-    latch();
-  }
-
-  for (;;) {
-    spi_write(0);
+    latch(spi);
   }
 }
 
diff --git a/src/kern/spi/spi_manager.c b/src/kern/spi/spi_manager.c
new file mode 100644
index 0000000..83b6e1f
--- /dev/null
+++ b/src/kern/spi/spi_manager.c
@@ -0,0 +1,151 @@
+#include "kern/spi/spi_manager.h"
+
+#include "arch/stm32l4xxx/peripherals/rcc.h"
+#include "arch/stm32l4xxx/peripherals/spi.h"
+#include "kern/log.h"
+
+struct spi {
+  __IO spi_regs_t* regs;
+  spi_select_t selection;
+  bool reserved;
+};
+
+static spi_t spi_buses[N_SPI_SELECT];
+
+static void enable_spi_clock(spi_t* spi, int enable)
+{
+  switch (spi->selection) {
+    case SPI_SELECT_SPI1:
+      regset(RCC.apb2en_r, rcc_spi1en, !!enable);
+      break;
+
+    case SPI_SELECT_SPI2:
+      regset(RCC.apb1en1_r, rcc_spi3en, !!enable);
+      break;
+
+    default:
+      break;
+  }
+}
+
+static spi_t* configure_spi(spi_t* spi, spi_opts_t* opts, int* ec)
+{
+  enable_spi_clock(spi, 1);
+
+  uint32_t reg = 0;
+  regset(reg, spi_ldma_tx, opts->number_of_data_parity_tx);
+  regset(reg, spi_ldma_rx, opts->number_of_data_parity_rx);
+  regset(reg, spi_frxth, opts->rx_interrupt_fifo_threshold);
+  regset(reg, spi_ds, opts->data_size);
+  regset(reg, spi_txeie, opts->enable_tx_buffer_empty_interrupt);
+  regset(reg, spi_rxneie, opts->enable_rx_buffer_not_empty_interrupt);
+  regset(reg, spi_errie, opts->enable_error_interrupt);
+  regset(reg, spi_frf, opts->frame_format);
+  regset(reg, spi_nssp, opts->enable_nss_pulse);
+  regset(reg, spi_ssoe, opts->enable_ss_output);
+  regset(reg, spi_txdmaen, opts->enable_tx_dma);
+  regset(reg, spi_rxdmaen, opts->enable_rx_dma);
+
+  spi->regs->c_r2 = reg;
+
+  reg = 0;
+  regset(reg, spi_bidimode, opts->enable_bidirectional_data_mode);
+  regset(reg, spi_crcen, opts->enable_crc);
+  regset(reg, spi_crcnext, 0);
+  regset(reg, spi_crcl, opts->crc_length);
+  regset(reg, spi_rxonly, opts->receieve_only);
+  regset(reg, spi_ssm, opts->enable_software_slave_management);
+  regset(reg, spi_ssi, opts->internal_slave_select);
+  regset(reg, spi_lsbfirst, !opts->endianness);
+  regset(reg, spi_spe, 1);
+  regset(reg, spi_br, opts->baud);
+  regset(reg, spi_mstr, !opts->spi_mode);
+  regset(reg, spi_cpol, opts->polarity);
+  regset(reg, spi_cpha, opts->clock_phase);
+
+  spi->regs->c_r1 = reg;
+
+  return spi;
+}
+
+static int try_reserve_spi(spi_t* spi)
+{
+  return !__sync_fetch_and_or(&spi->reserved, 1);
+}
+
+void spi_start(spi_t* spi)
+{
+  regset(spi->regs->c_r1, spi_spe, 1);
+}
+
+void release_spi(spi_t* spi)
+{
+  enable_spi_clock(spi, 0);
+  regset(spi->regs->c_r1, spi_spe, 0);
+  spi->reserved = 0;
+}
+
+void spi_set_crc_next(spi_t* spi)
+{
+  regset(spi->regs->c_r1, spi_crcnext, 1);
+}
+
+spi_t* reserve_spi(spi_select_t spi_select, spi_opts_t* opts, int* ec)
+{
+  *ec = 0;
+
+  if (spi_select < 0 || spi_select >= N_SPI_SELECT) {
+    *ec = SPI_ERROR_SELECTION_NOT_VALID;
+    return NULL;
+  }
+
+  spi_t* ret = &spi_buses[spi_select];
+
+  if (!try_reserve_spi(ret)) {
+    *ec = SPI_ERROR_ALREADY_IN_USE;
+    return NULL;
+  }
+
+  ret->selection = spi_select;
+  switch (spi_select) {
+#define SPI(sp, ptr)    \
+  case SPI_SELECT_##sp: \
+    ret->regs = &ptr;   \
+    break;
+#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc"
+#undef SPI
+    default:
+      *ec = SPI_ERROR_SELECTION_NOT_VALID;
+      return NULL;
+  }
+
+  return configure_spi(ret, opts, ec);
+}
+
+void spi_write_8_sync(spi_t* spi, uint8_t data)
+{
+  while (!regget(spi->regs->s_r, spi_txe))
+    ;
+  spi->regs->dl_r = data;
+}
+
+void spi_write_16_sync(spi_t* spi, uint16_t data)
+{
+  while (!regget(spi->regs->s_r, spi_txe))
+    ;
+  spi->regs->d_r = data;
+}
+
+uint8_t spi_read_8_sync(spi_t* spi)
+{
+  while (!regget(spi->regs->s_r, spi_rxne))
+    ;
+  return spi->regs->dl_r;
+}
+
+uint16_t spi_read_16_sync(spi_t* spi)
+{
+  while (!regget(spi->regs->s_r, spi_rxne))
+    ;
+  return spi->regs->d_r;
+}