diff options
Diffstat (limited to '01-system-clock/src')
| -rw-r--r-- | 01-system-clock/src/clock.c | 106 | ||||
| -rw-r--r-- | 01-system-clock/src/delay.c | 9 | ||||
| -rw-r--r-- | 01-system-clock/src/gpio.c | 37 | ||||
| -rw-r--r-- | 01-system-clock/src/isr_vector.c | 165 | ||||
| -rw-r--r-- | 01-system-clock/src/main.c | 36 | ||||
| -rw-r--r-- | 01-system-clock/src/spin.c | 49 | ||||
| -rw-r--r-- | 01-system-clock/src/vector.c | 0 |
7 files changed, 402 insertions, 0 deletions
diff --git a/01-system-clock/src/clock.c b/01-system-clock/src/clock.c new file mode 100644 index 0000000..75bac97 --- /dev/null +++ b/01-system-clock/src/clock.c @@ -0,0 +1,106 @@ +/* + * This file sets the system clock to its full glory of 80Mhz + */ + +#include "clock.h" +#include <stdint.h> +#include "flash.h" +#include "gpio.h" +#include "spin.h" + +#define TIMEOUT 10000 + +int pll_off() +{ + uint32_t c; + + RCC.c_r &= ~BIT(24); /* Turn off pll. */ + for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c) + ; /* Wait for OFF. */ + + if (c == TIMEOUT) { + return E_TIMEOUT; + } + + return 0; +} + +int pll_on() +{ + uint32_t c; + + RCC.c_r |= BIT(24); /* Turn on PLL. */ + for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c) + ; /* Wait for RDY. */ + + if (c == TIMEOUT) { + return E_TIMEOUT; + } + + return 0; +} + +int configure_pll( + uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */) +{ + if (RCC.c_r & BIT(25)) { + /* PLL must be off to configure it. */ + return E_NOT_OFF; + } + + /* Make sure inputs are valid. */ + if (pllp_div_factor == 1 || pllp_div_factor > 31) { + return E_BADPLLP_DIV; + } + if (plln < 8 || plln > 86) { + return E_BADPLLN; + } + + RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | + (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); + + return 0; +} + +int set_system_clock_MHz(uint8_t mhz) +{ + /* Set the source of the system colck to MSI temporarily. */ + set_system_clock_src(SYSTEM_CLOCK_SRC_MSI); + + if (mhz <= 8 || mhz > 80) { + return E_BAD_ARG; + } + + pll_off(); + + configure_pll( + 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, + PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, + + /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. + */ + mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, + PLL_SRC_MSI /* pll src | 04 Mhz */); + + pll_on(); + + /* Configure the flash to have 4 wait states. This is required at + * 80 MHz. */ + FLASH.ac_r &= ~0x07; + FLASH.ac_r |= 0x04; + + /* Set the source of the system colck to PLL. */ + set_system_clock_src(SYSTEM_CLOCK_SRC_PLL); + return 0; +} + +int set_system_clock_src(system_clock_src_t src) +{ + uint8_t value = RCC.cfg_r & ~0x03; + RCC.cfg_r = value | src; +} diff --git a/01-system-clock/src/delay.c b/01-system-clock/src/delay.c new file mode 100644 index 0000000..2a16d47 --- /dev/null +++ b/01-system-clock/src/delay.c @@ -0,0 +1,9 @@ +#include "delay.h" + +void delay(uint32_t delay) +{ + while (delay--) { + /* needed to keep the compiler from optimizing away the loop. */ + asm volatile(""); + } +} diff --git a/01-system-clock/src/gpio.c b/01-system-clock/src/gpio.c new file mode 100644 index 0000000..2404398 --- /dev/null +++ b/01-system-clock/src/gpio.c @@ -0,0 +1,37 @@ +#include "gpio.h" +#include "rcc.h" + +/* + * Sets the mode of a pin on a gpio por. + */ +void set_gpio_pin_mode( + __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode) +{ + /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */ + gpio_port->mode_r &= ~(0x03 << pin * 2); + gpio_port->mode_r |= mode << pin * 2; +} + +gpio_output_pin_t set_gpio_pin_output( + __IO gpio_port_t* gpio_port, gpio_pin_t pin) +{ + set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT); + + return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin}; +} + +void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff) +{ + if (onoff) { + pin.gpio_port->output_r |= 1 << pin.pin; + } else { + pin.gpio_port->output_r &= ~(1 << pin.pin); + } +} + +#define GPIO_PORTS_BASE_ADDR ((uint32_t)0x48000000) +__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) +{ + RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ + return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); +} diff --git a/01-system-clock/src/isr_vector.c b/01-system-clock/src/isr_vector.c new file mode 100644 index 0000000..674a6bb --- /dev/null +++ b/01-system-clock/src/isr_vector.c @@ -0,0 +1,165 @@ +#include "isr_vector.h" +#include "delay.h" +#include "gpio.h" + +/* Forward-declare the main function. This is implemented in main.c. */ +void main(); + +/* These are defined in the linker script. */ +extern uint32_t INIT_DATA_VALUES; +extern uint32_t DATA_SEGMENT_START; +extern uint32_t DATA_SEGMENT_STOP; +extern uint32_t BSS_START; +extern uint32_t BSS_END; + +/* + * Runs before main. Initializes the data and bss segments by loading them + * into memory. + */ +void init() +{ + uint32_t* src; + uint32_t* dest; + + src = &INIT_DATA_VALUES; + dest = &DATA_SEGMENT_START; + + /* Copy the values from flash into the data segment. */ + while (dest != &DATA_SEGMENT_STOP) { + *(dest++) = *(src++); + } + + /* Everything in the BSS segment is set to zero. */ + dest = &BSS_START; + while (dest != &BSS_END) { + *(dest++) = 0; + } + + /* Jump to main. */ + main(); +} + +const void* vectors[] __attribute__((section(".vectors"))) = { + (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ + init, /* Reset handler */ + unhandled_isr, /* NMI */ + unhandled_isr, /* Hard Fault */ + unhandled_isr, /* MemManage */ + unhandled_isr, /* BusFault */ + unhandled_isr, /* UsageFault */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* SVCall */ + unhandled_isr, /* Debug */ + unhandled_isr, /* Reserved */ + unhandled_isr, /* PendSV */ + unhandled_isr, /* SysTick */ + + /* External interrupt handlers follow */ + unhandled_isr, /* 0 WWDG */ + unhandled_isr, /* 1 PVD */ + unhandled_isr, /* 2 TAMP_SAMP */ + unhandled_isr, /* 3 RTC_WKUP */ + unhandled_isr, /* 4 FLASH */ + unhandled_isr, /* 5 RCC */ + unhandled_isr, /* 6 EXTI0 */ + unhandled_isr, /* 7 EXTI1 */ + unhandled_isr, /* 8 EXTI2 */ + unhandled_isr, /* 9 EXTI3 */ + unhandled_isr, /* 10 EXTI4 */ + unhandled_isr, /* 11 DMA_CH1 */ + unhandled_isr, /* 12 DMA_CH2 */ + unhandled_isr, /* 13 DMA_CH3 */ + unhandled_isr, /* 14 DMA_CH4 */ + unhandled_isr, /* 15 DMA_CH5 */ + unhandled_isr, /* 16 DMA_CH6 */ + unhandled_isr, /* 17 DMA_CH7 */ + unhandled_isr, /* 18 ADC1 */ + unhandled_isr, /* 19 CAN_TX */ + unhandled_isr, /* 20 CAN_RX0 */ + unhandled_isr, /* 21 CAN_RX1 */ + unhandled_isr, /* 22 CAN_SCE */ + unhandled_isr, /* 23 EXTI9_5 */ + unhandled_isr, /* 24 TIM1_BRK/TIM15 */ + unhandled_isr, /* 25 TIM1_UP/TIM16 */ + unhandled_isr, /* 26 TIM1_TRG_COM */ + unhandled_isr, /* 27 TIM1_CC */ + unhandled_isr, /* 28 TIM2 */ + unhandled_isr, /* 29 Reserved */ + unhandled_isr, /* 30 Reserved */ + unhandled_isr, /* 31 I2C1_EV */ + unhandled_isr, /* 32 I2C1_ER */ + unhandled_isr, /* 33 I2C2_EV */ + unhandled_isr, /* 34 I2C2_ER */ + unhandled_isr, /* 35 SPI1 */ + unhandled_isr, /* 36 SPI2 */ + unhandled_isr, /* 37 USART1 */ + unhandled_isr, /* 38 USART2 */ + unhandled_isr, /* 39 USART3 */ + unhandled_isr, /* 40 EXTI15_10 */ + unhandled_isr, /* 41 RTCAlarm */ + unhandled_isr, /* 42 Reserved */ + unhandled_isr, /* 43 Reserved */ + unhandled_isr, /* 44 Reserved */ + unhandled_isr, /* 45 Reserved */ + unhandled_isr, /* 46 Reserved */ + unhandled_isr, /* 47 Reserved */ + unhandled_isr, /* 48 Reserved */ + unhandled_isr, /* 49 SDMMC1 */ + unhandled_isr, /* 50 Reserved */ + unhandled_isr, /* 51 SPI3 */ + unhandled_isr, /* 52 Reserved */ + unhandled_isr, /* 53 Reserved */ + unhandled_isr, /* 54 TIM6_DACUNDER */ + unhandled_isr, /* 55 TIM7 */ + unhandled_isr, /* 56 DMA2_CH1 */ + unhandled_isr, /* 57 DMA2_CH2 */ + unhandled_isr, /* 58 DMA2_CH3 */ + unhandled_isr, /* 59 DMA2_CH4 */ + unhandled_isr, /* 60 DMA2_CH5 */ + unhandled_isr, /* 61 Reserved */ + unhandled_isr, /* 62 Reserved */ + unhandled_isr, /* 63 Reserved*/ + unhandled_isr, /* 64 COMP */ + unhandled_isr, /* 65 LPTIM1 */ + unhandled_isr, /* 66 LPTIM2 */ + unhandled_isr, /* 67 USB_FS */ + unhandled_isr, /* 68 DMA_CH6 */ + unhandled_isr, /* 69 DMA_CH7 */ + unhandled_isr, /* 70 LPUART1 */ + unhandled_isr, /* 71 QUADSPI */ + unhandled_isr, /* 72 I2C3_EV */ + unhandled_isr, /* 73 I2C3_ER */ + unhandled_isr, /* 74 SAI1 */ + unhandled_isr, /* 75 Reserved */ + unhandled_isr, /* 76 SWPMI1 */ + unhandled_isr, /* 77 TSC */ + unhandled_isr, /* 78 Reserved */ + unhandled_isr, /* 79 AES */ + unhandled_isr, /* 80 RNG */ + unhandled_isr, /* 81 FPU */ + unhandled_isr /* 82 CRS */ +}; + +/* + * Does nothing ... forever. + */ +void unhandled_isr() +{ + __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); + gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); + for (;;) { + /* Flash in a distinct pattern to know that something went wrong. */ + + pin_off(pin3); + delay(100000); + pin_on(pin3); + delay(100000); + pin_off(pin3); + delay(100000); + pin_on(pin3); + delay(500000); + } +} diff --git a/01-system-clock/src/main.c b/01-system-clock/src/main.c new file mode 100644 index 0000000..7912bf2 --- /dev/null +++ b/01-system-clock/src/main.c @@ -0,0 +1,36 @@ +#include "clock.h" +#include "delay.h" +#include "gpio.h" +#include "spin.h" + +volatile uint32_t delay_amt = 20000000 / 4; + +/* Main function. This gets executed from the interrupt vector defined above. */ +int main() +{ + /* Enable the GPIO port B. */ + + __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); + gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); + gpio_output_pin_t pin1 = set_gpio_pin_output(port_b, PIN_1); + + /* Enable a higher clock frequency. */ + set_system_clock_MHz(80); + + uint32_t count = 0; + while (1) { + /* Set the GPIO pin to high. */ + pin_off(pin1); + pin_off(pin3); + delay(delay_amt); + + /* Set the GPIO pin to low. */ + if (count % 4 == 0) { + pin_on(pin1); + } + pin_on(pin3); + delay(delay_amt); + + ++count; + } +} diff --git a/01-system-clock/src/spin.c b/01-system-clock/src/spin.c new file mode 100644 index 0000000..fbd16b6 --- /dev/null +++ b/01-system-clock/src/spin.c @@ -0,0 +1,49 @@ +#include "spin.h" +#include "delay.h" +#include "gpio.h" + +#define SHORT_DELAY 200000 +#define LONG_DELAY (SHORT_DELAY * 2) + +static void flash_bit( + uint32_t base, gpio_output_pin_t out_pin, + uint8_t bit /* 0 => 0, non-zero => 1 */) +{ + pin_on(out_pin); + if (bit) { + delay(base * 2); + } else { + delay(base); + } + pin_off(out_pin); + delay(base); +} + +void spin(uint32_t base, uint8_t c) +{ + uint8_t code; + __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); + gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); + + for (;;) { + code = c; + flash_bit(base, pin3, code & 0x80); + code <<= 1; + flash_bit(base, pin3, code & 0x80); + code <<= 1; + flash_bit(base, pin3, code & 0x80); + code <<= 1; + flash_bit(base, pin3, code & 0x80); + + code <<= 1; + flash_bit(base, pin3, code & 0x80); + code <<= 1; + flash_bit(base, pin3, code & 0x80); + code <<= 1; + flash_bit(base, pin3, code & 0x80); + code <<= 1; + flash_bit(base, pin3, code & 0x80); + + delay(base * 4); + } +} diff --git a/01-system-clock/src/vector.c b/01-system-clock/src/vector.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/01-system-clock/src/vector.c |