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Diffstat (limited to '02-usart/include/arch/stm32l4xxx/peripherals/gpio.h')
| -rw-r--r-- | 02-usart/include/arch/stm32l4xxx/peripherals/gpio.h | 326 |
1 files changed, 326 insertions, 0 deletions
diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h b/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h new file mode 100644 index 0000000..20acf71 --- /dev/null +++ b/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h @@ -0,0 +1,326 @@ +#ifndef CORE_GPIO_H__ +#define CORE_GPIO_H__ + +#include "kern/common.h" +#include "arch/stm32l4xxx/peripherals/rcc.h" + +#include <stdint.h> + +/* + * Possible GPIO ports. + */ +typedef enum { + GPIO_PORT_A = 0, + GPIO_PORT_B = 1, + GPIO_PORT_C = 2, + GPIO_PORT_D = 3 +} gpio_port_number_t; + +/* + * Structure defining the layout of the layout of the GPIO registers on the + * stm32l432 development board. + */ +typedef struct GPIO_PORT_STR { + /* Mode of each GPIO pin for this GPIO port. */ +#define gpio_mode0 (3 << 0) +#define gpio_mode1 (3 << 2) +#define gpio_mode2 (3 << 4) +#define gpio_mode3 (3 << 6) +#define gpio_mode4 (3 << 8) +#define gpio_mode5 (3 << 10) +#define gpio_mode6 (3 << 12) +#define gpio_mode7 (3 << 14) +#define gpio_mode8 (3 << 16) +#define gpio_mode9 (3 << 18) +#define gpio_mode10 (3 << 20) +#define gpio_mode11 (3 << 22) +#define gpio_mode12 (3 << 24) +#define gpio_mode13 (3 << 26) +#define gpio_mode14 (3 << 28) +#define gpio_mode15 (3 << 30) + __IO uint32_t mode_r; /* Mode register */ + + /* Output type for each gpio pin in this port. */ +#define gpio_otype0 (1 << 0) +#define gpio_otype1 (1 << 1) +#define gpio_otype2 (1 << 2) +#define gpio_otype3 (1 << 3) +#define gpio_otype4 (1 << 4) +#define gpio_otype5 (1 << 5) +#define gpio_otype6 (1 << 6) +#define gpio_otype7 (1 << 7) +#define gpio_otype8 (1 << 8) +#define gpio_otype9 (1 << 9) +#define gpio_otype10 (1 << 10) +#define gpio_otype11 (1 << 11) +#define gpio_otype12 (1 << 12) +#define gpio_otype13 (1 << 13) +#define gpio_otype14 (1 << 14) +#define gpio_otype15 (1 << 15) + __IO uint32_t otype_r; + + /* GPIO port output speed. */ +#define gpio_ospeed0 (3 << 0) +#define gpio_ospeed1 (3 << 2) +#define gpio_ospeed2 (3 << 4) +#define gpio_ospeed3 (3 << 6) +#define gpio_ospeed4 (3 << 8) +#define gpio_ospeed5 (3 << 10) +#define gpio_ospeed6 (3 << 12) +#define gpio_ospeed7 (3 << 14) +#define gpio_ospeed8 (3 << 16) +#define gpio_ospeed9 (3 << 18) +#define gpio_ospeed10 (3 << 20) +#define gpio_ospeed11 (3 << 22) +#define gpio_ospeed12 (3 << 24) +#define gpio_ospeed13 (3 << 26) +#define gpio_ospeed14 (3 << 28) +#define gpio_ospeed15 (3 << 30) + __IO uint32_t ospeed_r; + + /* GPIO port pull-up/pull-down register */ +#define gpio_pupd0 (3 << 0) +#define gpio_pupd1 (3 << 2) +#define gpio_pupd2 (3 << 4) +#define gpio_pupd3 (3 << 6) +#define gpio_pupd4 (3 << 8) +#define gpio_pupd5 (3 << 10) +#define gpio_pupd6 (3 << 12) +#define gpio_pupd7 (3 << 14) +#define gpio_pupd8 (3 << 16) +#define gpio_pupd9 (3 << 18) +#define gpio_pupd10 (3 << 20) +#define gpio_pupd11 (3 << 22) +#define gpio_pupd12 (3 << 24) +#define gpio_pupd13 (3 << 26) +#define gpio_pupd14 (3 << 28) +#define gpio_pupd15 (3 << 30) + __IO uint32_t pupd_r; + + /* GPIO port input data register. */ +#define gpio_idr0 (1 << 0) +#define gpio_idr1 (1 << 1) +#define gpio_idr2 (1 << 2) +#define gpio_idr3 (1 << 3) +#define gpio_idr4 (1 << 4) +#define gpio_idr5 (1 << 5) +#define gpio_idr6 (1 << 6) +#define gpio_idr7 (1 << 7) +#define gpio_idr8 (1 << 8) +#define gpio_idr9 (1 << 9) +#define gpio_idr10 (1 << 10) +#define gpio_idr11 (1 << 11) +#define gpio_idr12 (1 << 12) +#define gpio_idr13 (1 << 13) +#define gpio_idr14 (1 << 14) +#define gpio_idr15 (1 << 15) + __IO uint32_t id_r; + + /* GPIO port output data register. */ +#define gpio_odr0 (1 << 0) +#define gpio_odr1 (1 << 1) +#define gpio_odr2 (1 << 2) +#define gpio_odr3 (1 << 3) +#define gpio_odr4 (1 << 4) +#define gpio_odr5 (1 << 5) +#define gpio_odr6 (1 << 6) +#define gpio_odr7 (1 << 7) +#define gpio_odr8 (1 << 8) +#define gpio_odr9 (1 << 9) +#define gpio_odr10 (1 << 10) +#define gpio_odr11 (1 << 11) +#define gpio_odr12 (1 << 12) +#define gpio_odr13 (1 << 13) +#define gpio_odr14 (1 << 14) +#define gpio_odr15 (1 << 15) + __IO uint32_t output_r; + + /* GPIO port bit set/reset register. */ +#define gpio_bs0 (1 << 0) +#define gpio_bs1 (1 << 1) +#define gpio_bs2 (1 << 2) +#define gpio_bs3 (1 << 3) +#define gpio_bs4 (1 << 4) +#define gpio_bs5 (1 << 5) +#define gpio_bs6 (1 << 6) +#define gpio_bs7 (1 << 7) +#define gpio_bs8 (1 << 8) +#define gpio_bs9 (1 << 9) +#define gpio_bs10 (1 << 10) +#define gpio_bs11 (1 << 11) +#define gpio_bs12 (1 << 12) +#define gpio_bs13 (1 << 13) +#define gpio_bs14 (1 << 14) +#define gpio_bs15 (1 << 15) +#define gpio_br0 (1 << 16) +#define gpio_br1 (1 << 17) +#define gpio_br2 (1 << 18) +#define gpio_br3 (1 << 19) +#define gpio_br4 (1 << 20) +#define gpio_br5 (1 << 21) +#define gpio_br6 (1 << 22) +#define gpio_br7 (1 << 23) +#define gpio_br8 (1 << 24) +#define gpio_br9 (1 << 25) +#define gpio_br10 (1 << 26) +#define gpio_br11 (1 << 27) +#define gpio_br12 (1 << 28) +#define gpio_br13 (1 << 29) +#define gpio_br14 (1 << 30) +#define gpio_br15 (1 << 31) + __IO uint32_t bsr_r; + + /* GPIO port configuration lock register. */ +#define gpio_lck0 (1 << 0) +#define gpio_lck1 (1 << 1) +#define gpio_lck2 (1 << 2) +#define gpio_lck3 (1 << 3) +#define gpio_lck4 (1 << 4) +#define gpio_lck5 (1 << 5) +#define gpio_lck6 (1 << 6) +#define gpio_lck7 (1 << 7) +#define gpio_lck8 (1 << 8) +#define gpio_lck9 (1 << 9) +#define gpio_lck10 (1 << 10) +#define gpio_lck11 (1 << 11) +#define gpio_lck12 (1 << 12) +#define gpio_lck13 (1 << 13) +#define gpio_lck14 (1 << 14) +#define gpio_lck15 (1 << 15) +#define gpio_lckk (1 << 16) + __IO uint32_t lck_r; + + /* Alternate function low-register. */ +#define gpio_afsel0 (0xF << 0) +#define gpio_afsel1 (0xF << 4) +#define gpio_afsel2 (0xF << 8) +#define gpio_afsel3 (0xF << 12) +#define gpio_afsel4 (0xF << 16) +#define gpio_afsel5 (0xF << 20) +#define gpio_afsel6 (0xF << 24) +#define gpio_afsel7 (0xF << 28) + __IO uint32_t af_rl; + + /* Alternate function high-register. */ +#define gpio_afsel8 (0xF << 0) +#define gpio_afsel9 (0xF << 4) +#define gpio_afsel10 (0xF << 8) +#define gpio_afsel11 (0xF << 12) +#define gpio_afsel12 (0xF << 16) +#define gpio_afsel13 (0xF << 20) +#define gpio_afsel14 (0xF << 24) +#define gpio_afsel15 (0xF << 28) + __IO uint32_t af_rh; +} PACKED gpio_port_t; + +/* + * Enum defining the PINs in a GPIO port. Each port has 16 pins to use in + * the stm32l432. + */ +typedef enum GPIO_PIN_ENUM { + PIN_0 = 0, + PIN_1 = 1, + PIN_2 = 2, + PIN_3 = 3, + PIN_4 = 4, + PIN_5 = 5, + PIN_6 = 6, + PIN_7 = 7, + PIN_8 = 8, + PIN_9 = 9, + PIN_10 = 10, + PIN_11 = 11, + PIN_12 = 12, + PIN_13 = 13, + PIN_14 = 14, + PIN_15 = 15 +} gpio_pin_t; + +/* Alternate function number. */ +typedef enum { + AFN_0 = 0, + AFN_1 = 1, + AFN_2 = 2, + AFN_3 = 3, + AFN_4 = 4, + AFN_5 = 5, + AFN_6 = 6, + AFN_7 = 7, + AFN_8 = 8, + AFN_9 = 9, + AFN_10 = 10, + AFN_11 = 11, + AFN_12 = 12, + AFN_13 = 13, + AFN_14 = 14, + AFN_15 = 15 +} alternate_function_t; + +/* + * Enum defining the pin modes that are possible. + */ +typedef enum { + MODE_INPUT = 0, + MODE_OUTPUT = 1, + MODE_ALTERNATE = 2, + MODE_ANALOG = 3 +} gpio_pin_mode_t; + +/* + * Enum defining the pin speeds that are possible. + */ +typedef enum { + SPEED_2MHZ = 0, + SPEED_10MHZ = 1, + SPEED_50MHZ = 3, +} speed_t; + +/* + * Structure defining an OUTPUT pin. Structurally equivalent to the input pin, + * but can be used in a slightly type-safe manner. + */ +typedef struct { + __IO gpio_port_t* gpio_port; + gpio_pin_t pin; +} gpio_output_pin_t; + +/* + * Sets the mode on a GPIO pin. + * + * gpio_port: the gpio port to use. + * pin: the pin number to set. + * pin_mode: the mode to set the pin to. + */ +void set_gpio_pin_mode( + __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode); + +/* + * Sets the given GPIO pin to be an output pin. Returns an output_pin struct + * corresponding to + */ +gpio_output_pin_t set_gpio_pin_output( + __IO gpio_port_t* gpio_port, gpio_pin_t pin); + +/* + * Sets an output pin on or off. + * + * pin: the pin to toggle. + * onoff: 0 for off, non-zero of on. + */ +void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff); + +#define pin_on(p) set_gpio_output_pin(p, 1) + +#define pin_off(p) set_gpio_output_pin(p, 0) + +/* + * Enables a GPIO port and returns a reference to the register definition + * of that GPIO port. + */ +__IO gpio_port_t* enable_gpio(gpio_port_number_t number); + +/* Sets the alternate function for a GPIO pin. */ +void set_gpio_alternate_function( + __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn); + +#endif /* CORE_GPIO_H__ */ |