diff options
Diffstat (limited to '02-usart/include/core/rcc.h')
| -rw-r--r-- | 02-usart/include/core/rcc.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/02-usart/include/core/rcc.h b/02-usart/include/core/rcc.h index 23f1bd9..9c82501 100644 --- a/02-usart/include/core/rcc.h +++ b/02-usart/include/core/rcc.h @@ -27,6 +27,30 @@ typedef struct { __IO uint32_t reserved_3; /* Not used. offset 0x34. */ +#define rcc_lptim1rst (1 << 31) // Low Power Timer 1 reset +#define rcc_opamprst (1 << 30) // OPAMP interface reset +#define rcc_dac1rst (1 << 29) // DAC1 interface reset +#define rcc_pwrrst (1 << 28) // Power interface reset +#define rcc_can2rst (1 << 26) // CAN2 reset (this bit is reserved for STM32L47x/L48x devices) +#define rcc_can1rst (1 << 25) // CAN1 reset +#define rcc_crsrst (1 << 24) // CRS reset (this bit is reserved for STM32L47x/L48x devices) +#define rcc_i2c3rst (1 << 23) // I2C3 reset +#define rcc_i2c2rst (1 << 22) // I2C2 reset +#define rcc_i2c1rst (1 << 21) // I2C1 reset +#define rcc_uart5rst (1 << 20) // UART5 reset +#define rcc_uart4rst (1 << 19) // UART4 reset +#define rcc_usart3rst (1 << 18) // USART3 reset +#define rcc_usart2rst (1 << 17) // USART2 reset +#define rcc_reserved (1 << 16) // must be kept at reset value. +#define rcc_spi3rst (1 << 15) // SPI3 reset +#define rcc_spi2rst (1 << 14) // SPI2 reset +#define rcc_lcdrst (1 << 9) // interface reset (this bit is reserved for STM32L471/L4x5 devices) +#define rcc_tim7rst (1 << 5) // timer reset +#define rcc_tim6rst (1 << 4) // timer reset +#define rcc_tim5rst (1 << 3) // timer reset +#define rcc_tim4rst (1 << 2) // timer reset +#define rcc_tim3rst (1 << 1) // timer reset +#define rcc_tim2rst (1 << 0) // timer reset __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */ __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */ __IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */ |