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Diffstat (limited to '02-usart/include/dma.h')
-rw-r--r--02-usart/include/dma.h27
1 files changed, 16 insertions, 11 deletions
diff --git a/02-usart/include/dma.h b/02-usart/include/dma.h
index 57462f9..229b732 100644
--- a/02-usart/include/dma.h
+++ b/02-usart/include/dma.h
@@ -30,9 +30,14 @@ typedef enum {
DMA_PRIORITY_LEVEL_VERY_HIGH = 3
} dma_priority_level;
+typedef enum {
+ READ_FROM_PERIPHERAL = 0,
+ READ_FROM_MEMORY = 1,
+} dma_dir_t;
+
typedef struct {
union {
- uint32_t cc_r;
+ __IO uint32_t cc_r;
struct {
bits_t en:1; // channel enable
bits_t tcie:1; // transfer complete interrupt enable
@@ -52,28 +57,28 @@ typedef struct {
/* Number of data to transfer. */
union {
- uint32_t cndt_r;
+ __IO uint32_t cndt_r;
struct {
- uint16_t ndt; // Number of data to transfer.
- uint16_t reserved;
+ bits_t ndt:16; // Number of data to transfer.
+ bits_t reserved:16;
} cndt_bf;
};
/* DMA channel peripheral address register.
* Defines a memory address if mem2mem is set. */
- uint32_t cpa_r;
+ __IO uint32_t cpa_r;
/* DMA channel memory address register.
* Defines another perpipheral address if peripheral-periphal mode is set. */
- uint32_t cma_r;
+ __IO uint32_t cma_r;
- uint32_t reserved;
+ __IO uint32_t reserved;
} dma_channel_config_t;
typedef struct {
// DMA Interrupt status register.
union {
- uint32_t is_r;
+ __IO uint32_t is_r;
struct {
bits_t gif1:1; // global interrupt flag for channel 1
bits_t tcif1:1; // transfer complete (TC) flag for channel 1
@@ -109,7 +114,7 @@ typedef struct {
// DMA Interrupt flag clear register
union {
- uint32_t ifc_r;
+ __IO uint32_t ifc_r;
struct {
bits_t cgif1:1; // global interrupt flag clear for channel 1
bits_t ctcif1:1; // transfer complete flag clear for channel 1
@@ -144,11 +149,11 @@ typedef struct {
dma_channel_config_t channel_config[7];
- uint32_t reserved[5];
+ __IO uint32_t reserved[5];
/* DMA channel selection register. */
union {
- uint32_t csel_r;
+ __IO uint32_t csel_r;
struct {
bits_t c1s:4; // DMA channel 1 selection.
bits_t c2s:4; // DMA channel 2 selection.