diff options
| -rw-r--r-- | 02-usart/include/core/rcc.h | 24 | ||||
| -rw-r--r-- | 02-usart/include/core/usart.h | 196 | ||||
| -rw-r--r-- | 02-usart/src/core/usart.c | 16 | ||||
| -rw-r--r-- | 02-usart/src/main.c | 38 |
4 files changed, 151 insertions, 123 deletions
diff --git a/02-usart/include/core/rcc.h b/02-usart/include/core/rcc.h index 23f1bd9..9c82501 100644 --- a/02-usart/include/core/rcc.h +++ b/02-usart/include/core/rcc.h @@ -27,6 +27,30 @@ typedef struct { __IO uint32_t reserved_3; /* Not used. offset 0x34. */ +#define rcc_lptim1rst (1 << 31) // Low Power Timer 1 reset +#define rcc_opamprst (1 << 30) // OPAMP interface reset +#define rcc_dac1rst (1 << 29) // DAC1 interface reset +#define rcc_pwrrst (1 << 28) // Power interface reset +#define rcc_can2rst (1 << 26) // CAN2 reset (this bit is reserved for STM32L47x/L48x devices) +#define rcc_can1rst (1 << 25) // CAN1 reset +#define rcc_crsrst (1 << 24) // CRS reset (this bit is reserved for STM32L47x/L48x devices) +#define rcc_i2c3rst (1 << 23) // I2C3 reset +#define rcc_i2c2rst (1 << 22) // I2C2 reset +#define rcc_i2c1rst (1 << 21) // I2C1 reset +#define rcc_uart5rst (1 << 20) // UART5 reset +#define rcc_uart4rst (1 << 19) // UART4 reset +#define rcc_usart3rst (1 << 18) // USART3 reset +#define rcc_usart2rst (1 << 17) // USART2 reset +#define rcc_reserved (1 << 16) // must be kept at reset value. +#define rcc_spi3rst (1 << 15) // SPI3 reset +#define rcc_spi2rst (1 << 14) // SPI2 reset +#define rcc_lcdrst (1 << 9) // interface reset (this bit is reserved for STM32L471/L4x5 devices) +#define rcc_tim7rst (1 << 5) // timer reset +#define rcc_tim6rst (1 << 4) // timer reset +#define rcc_tim5rst (1 << 3) // timer reset +#define rcc_tim4rst (1 << 2) // timer reset +#define rcc_tim3rst (1 << 1) // timer reset +#define rcc_tim2rst (1 << 0) // timer reset __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */ __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */ __IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */ diff --git a/02-usart/include/core/usart.h b/02-usart/include/core/usart.h index 9ed6dbb..667b931 100644 --- a/02-usart/include/core/usart.h +++ b/02-usart/include/core/usart.h @@ -23,63 +23,56 @@ typedef enum { typedef struct { /* USART configuration registers 0x04 - 0x0c. */ - union { - __IO uint32_t c_r1; - struct { - bits_t ue:1; /* UART enable */ - bits_t uesm:1; /* UART enabled in stop mode. */ - bits_t re:1; /* reciever enabled. */ - bits_t te:1; /* transmitter enabled. */ - bits_t idleie:1; /* Idle interrupt enabled. */ - bits_t rxneie:1; /* RXNEIE RXNE interrupt enable. */ - bits_t tcie:1; - bits_t txeie:1; - bits_t peie:1; - bits_t ps:1; - bits_t pce:1; - bits_t wake:1; - bits_t m0:1; - bits_t mme:1; - bits_t cmie:1; - bits_t over8:1; - bits_t dedt:4; - bits_t deat:4; - bits_t rtoie:1; - bits_t eobie:1; - bits_t m1:1; - bits_t reserved:3; - } PACKED c1_bf; /* c1_bf = c1 bit field */ - }; /* USART Control Register 1. */ +#define usart_ue (1 << 0) /* UART enable */ +#define usart_uesm (1 << 1) /* UART enabled in stop mode. */ +#define usart_re (1 << 2) /* reciever enabled. */ +#define usart_te (1 << 3) /* transmitter enabled. */ +#define usart_idleie (1 << 4) /* Idle interrupt enabled. */ +#define usart_rxneie (1 << 5) /* RXNEIE RXNE interrupt enable. */ +#define usart_tcie (1 << 6) +#define usart_txeie (1 << 7) +#define usart_peie (1 << 8) +#define usart_ps (1 << 9) +#define usart_pce (1 << 10) +#define usart_wake (1 << 11) +#define usart_m0 (1 << 12) +#define usart_mme (1 << 13) +#define usart_cmie (1 << 14) +#define usart_over8 (1 << 15) +#define usart_dedt (0xF << 16) +#define usart_deat (0xF << 21) +#define usart_rtoie (1 << 26) +#define usart_eobie (1 << 27) +#define usart_m1 (1 << 28) + __IO uint32_t c_r1; __IO uint32_t c_r2; - union { - __IO uint32_t c_r3; - struct { - bits_t eie:1; // Error interrupt enable. - bits_t iren:1; // IrDA mode enabled - bits_t irlp:1; // IrDA low power - bits_t hdsel:1; // Half duplex selection - bits_t nack:1; // Smartcard NACK enable - bits_t scen:1; // Smartocard mode enable - bits_t dmar:1; // DMA enable reciever - bits_t dmat:1; // DMA enable transmitter - bits_t rtse:1; // RTS enable - bits_t ctse:1; // CTS enable - bits_t ctsie:1; // CTS interrupt enable - bits_t onebit:1; // One sample bit method enable - bits_t ovrdis:1; // Overrun disable - bits_t ddre:1; // DMA Disable on reception error - bits_t dem:1; // Driver enable mode - bits_t dep:1; // Driver enable polarity selection - bits_t reserved0:1; - bits_t scarcnt:3; // Smartcard auto-retry count. - bits_t wus:2; // Wakeup from STOP mode interrept flag selection - bits_t wufie:1; // Wakeup from STOP mode interrup enable - bits_t ucesm:1; // USART clock enable in STOP mode. - bits_t tcbgtie:1; // Transmission complete before guard time interrupt - bits_t reserved1:7; - } PACKED c3_bf; - }; + +#define usart_eie (1 << 0) // Error interrupt enable. +#define usart_iren (1 << 1) // IrDA mode enabled +#define usart_irlp (1 << 2) // IrDA low power +#define usart_hdsel (1 << 3) // Half duplex selection +#define usart_nack (1 << 4) // Smartcard NACK enable +#define usart_scen (1 << 5) // Smartocard mode enable +#define usart_dmar (1 << 6) // DMA enable reciever +#define usart_dmat (1 << 7) // DMA enable transmitter +#define usart_rtse (1 << 8) // RTS enable +#define usart_ctse (1 << 9) // CTS enable +#define usart_ctsie (1 << 10) // CTS interrupt enable +#define usart_onebit (1 << 11) // One sample bit method enable +#define usart_ovrdis (1 << 12) // Overrun disable +#define usart_ddre (1 << 13) // DMA Disable on reception error +#define usart_dem (1 << 14) // Driver enable mode +#define usart_dep (1 << 15) // Driver enable polarity selection +#define usart_scarcnt0 (1 << 17) +#define usart_scarcnt1 (1 << 18) +#define usart_scarcnt2 (1 << 19) +#define usart_wus0 (1 << 20) // Wakeup from STOP mode interrept flag selection +#define usart_wus1 (1 << 21) // Wakeup from STOP mode interrept flag selection +#define usart_wufie (1 << 22) // Wakeup from STOP mode interrup enable +#define usart_ucesm (1 << 23) // USART clock enable in STOP mode. +#define usart_tcbgtie (1 << 24) // Transmission complete before guard time interrupt + __IO uint32_t c_r3; /* USART baud rate register. */ uint32_t br_r; @@ -88,60 +81,45 @@ typedef struct { uint32_t rq_r; /* USART ISR register. Offset = 0x1c*/ - union { - __IO uint32_t is_r; /* Interrupt service register. */ - struct { - bits_t pe:1; // Parity error - bits_t fe:1; // Framing error - bits_t nf:1; // START bit noise detection flag. - bits_t ore:1; // Overrun error - bits_t dlie:1; // Idle line detected - bits_t rxne:1; // Read data register not empty - bits_t tc:1; // Transmission complete - bits_t txe:1; // Transmit data register empty - bits_t lbdf:1; // LIN break detection flag - bits_t ctsif:1; // CTS interrupt flag - bits_t cts:1; // CTS flag. - bits_t rtof:1; // Receiever timeout - bits_t eobf:1; // End of block flag - bits_t reserved0:1; - bits_t abre:1; // Auto baud rate error - bits_t abrf:1; // Auto baud rate flag - bits_t busy:1; // Busy flag - bits_t cmf:1; // Character match flag - bits_t sbkf:1; // send break flag - bits_t rwu:1; // receiver wakeup frlom mute mode. - bits_t wuf:1; // Wakeup from stop mode flag - bits_t teack:1; // Transmit enable acknowledge flag. - bits_t reack:1; // Receieve enable acknowledge flag. - bits_t reserved1:2; - bits_t tcbgt:1; // Transmission completer before guard time completion. - bits_t reserved2:6; - } PACKED is_bf; /* Interrupt servite bit field. */ - }; - union { - __IO uint32_t ic_r; - struct { - bits_t pecf:1; // Parity error clear flag - bits_t fecf:1; // Framing error clear flag - bits_t ncf:1; // Noise detected clear flag - bits_t orecf:1; // Overrun error clear flag - bits_t idlecf:1; // Idle line detected clear flag - bits_t reserved0:1; - bits_t tccf:1; // Transmission complete clear flag - bits_t tcbgtcf:1; // Transmission completed before guard time clear flag - bits_t lbdcf:1; // LIN break detection clear flag - bits_t ctscf:1; // CTS clear flag - bits_t reserved1:1; - bits_t rtocf:1; // Receiver timeout clear flag - bits_t eobcf:1; // End of block clear flag - bits_t reserved2:4; - bits_t cmcf:1; // Character match clear flag - bits_t reserved3:2; // Character match clear flag - bits_t wucf:1; // Wakeup from Stop mode clear flag. - bits_t reserved4:11; - } PACKED ic_bf; - }; +#define usart_pe (1 << 0) // Parity error +#define usart_fe (1 << 1) // Framing error +#define usart_nf (1 << 2) // START bit noise detection flag. +#define usart_ore (1 << 3) // Overrun error +#define usart_dlie (1 << 4) // Idle line detected +#define usart_rxne (1 << 5) // Read data register not empty +#define usart_tc (1 << 6) // Transmission complete +#define usart_txe (1 << 7) // Transmit data register empty +#define usart_lbdf (1 << 8) // LIN break detection flag +#define usart_ctsif (1 << 9) // CTS interrupt flag +#define usart_cts (1 << 10) // CTS flag. +#define usart_rtof (1 << 11) // Receiever timeout +#define usart_eobf (1 << 12) // End of block flag +#define usart_abre (1 << 14) // Auto baud rate error +#define usart_abrf (1 << 15) // Auto baud rate flag +#define usart_busy (1 << 16) // Busy flag +#define usart_cmf (1 << 17) // Character match flag +#define usart_sbkf (1 << 18) // send break flag +#define usart_rwu (1 << 19) // receiver wakeup frlom mute mode. +#define usart_wuf (1 << 20) // Wakeup from stop mode flag +#define usart_teack (1 << 21) // Transmit enable acknowledge flag. +#define usart_reack (1 << 22) // Receieve enable acknowledge flag. +#define usart_tcbgt (1 << 25) // Transmission completer before guard time completion. + __IO uint32_t is_r; /* Interrupt service register. */ + +#define usart_pecf (1 << 0) // Parity error clear flag +#define usart_fecf (1 << 1) // Framing error clear flag +#define usart_ncf (1 << 2) // Noise detected clear flag +#define usart_orecf (1 << 3) // Overrun error clear flag +#define usart_idlecf (1 << 4) // Idle line detected clear flag +#define usart_tccf (1 << 6) // Transmission complete clear flag +#define usart_tcbgtcf (1 << 7) // Transmission completed before guard time clear flag +#define usart_lbdcf (1 << 8) // LIN break detection clear flag +#define usart_ctscf (1 << 9) // CTS clear flag +#define usart_rtocf (1 << 11) // Receiver timeout clear flag +#define usart_eobcf (1 << 12) // End of block clear flag +#define usart_cmcf (1 << 17) // Character match clear flag +#define usart_wucf (1 << 20) // Wakeup from Stop mode clear flag. + __IO uint32_t ic_r; uint32_t rd_r; uint32_t td_r; } usart_t; diff --git a/02-usart/src/core/usart.c b/02-usart/src/core/usart.c index 8f58d8b..dc15e57 100644 --- a/02-usart/src/core/usart.c +++ b/02-usart/src/core/usart.c @@ -44,12 +44,12 @@ void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled) uint32_t c_r1 = usart->c_r1; if (!enabled) { - usart->c1_bf.ue = 0; + regset(usart->c_r1, usart_ue, 0); } else { /* Set the rx enabled. */ - usart->c1_bf.re = !!(enabled & USART_ENABLE_RX); - usart->c1_bf.te = !!(enabled & USART_ENABLE_TX); - usart->c1_bf.ue = 1; + regset(usart->c_r1, usart_re, !!(enabled & USART_ENABLE_RX)); + regset(usart->c_r1, usart_te, !!(enabled & USART_ENABLE_TX)); + regset(usart->c_r1, usart_ue, 1); } } @@ -85,16 +85,16 @@ void usart_enable_dma(__IO usart_t* usart, usart_enable_t enabled) { switch(enabled) { case USART_ENABLE_DISABLED: - usart->c3_bf.dmar = 0; - usart->c3_bf.dmat = 0; + regset(usart->c_r3, usart_dmar, 0); + regset(usart->c_r3, usart_dmat, 0); break; case USART_ENABLE_TX: - usart->c3_bf.dmat = 1; + regset(usart->c_r3, usart_dmat, 1); break; case USART_ENABLE_RX: - usart->c3_bf.dmar = 1; + regset(usart->c_r3, usart_dmar, 1); break; }; } diff --git a/02-usart/src/main.c b/02-usart/src/main.c index 73ccb17..72b3fe7 100644 --- a/02-usart/src/main.c +++ b/02-usart/src/main.c @@ -3,19 +3,13 @@ #include "core/clock.h" #include "core/dma.h" #include "core/gpio.h" -#include "core/isr_vector.h" #include "core/system.h" #include "core/usart.h" - #include "delay.h" -#include "lib.h" #include "mem.h" #include "spin.h" #include "string.h" - -#ifdef ARCH_STM32L4 - /** Overrides the default systick irq handler. */ void on_systick() { @@ -33,12 +27,42 @@ void on_systick() is_on = ! is_on; } +void setup_usart2(uint32_t baud_rate) +{ + __IO gpio_port_t* port_a = enable_gpio(GPIO_PORT_A); + enable_hsi(&RCC, true); + + set_usart2_clock_src(&RCC, USART_CLK_SRC_HSI16); + set_usart2_clock_enabled(&RCC, USART_CLK_SRC_HSI16); + + set_gpio_pin_mode(port_a, PIN_2, MODE_ALTERNATE); + set_gpio_pin_mode(port_a, PIN_15, MODE_ALTERNATE); + set_gpio_alternate_function(port_a, PIN_2, AFN_7); + set_gpio_alternate_function(port_a, PIN_15, AFN_3); + + /* De-assert reset of USART2 */ + regset(RCC.apb1rst1_r, rcc_usart2rst, 0); + + USART2.c_r1 = 0; + USART2.c_r2 = 0; + USART2.c_r3 = 0; + + usart_set_divisor(&USART2, 16000000 / baud_rate); +} + +#ifdef ARCH_STM32L4 + /* Main function. This gets executed from the interrupt vector defined above. */ int main() { /* Enable a higher clock frequency. */ set_system_clock_MHz(80); + setup_usart2(115200); + usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX); + + usart_printf(&USART2, "Start Configuring Countdown!\n"); + /* Set the countdown to start from 1,000,0000. */ SCB.strv_r = 10000000; @@ -47,6 +71,8 @@ int main() /* Start the systick. */ SCB.stcs_bf.enable = 1; + + usart_printf(&USART2, "Start Countdown Started!\n"); } #endif |