diff options
| -rw-r--r-- | 02-usart/include/core/irq.h (renamed from 02-usart/include/core/isr_vector.h) | 15 | ||||
| -rw-r--r-- | 02-usart/include/core/isrs.i | 112 | ||||
| -rw-r--r-- | 02-usart/include/core/isrs.inc | 112 | ||||
| -rw-r--r-- | 02-usart/src/core/irq.c (renamed from 02-usart/src/core/isr_vector.c) | 40 |
4 files changed, 132 insertions, 147 deletions
diff --git a/02-usart/include/core/isr_vector.h b/02-usart/include/core/irq.h index 78763cd..ae1126d 100644 --- a/02-usart/include/core/isr_vector.h +++ b/02-usart/include/core/irq.h @@ -1,5 +1,5 @@ -#ifndef CORE_h__ISR_VECTOR_H__ -#define CORE_h__ISR_VECTOR_H__ +#ifndef CORE_IRQ_H__ +#define CORE_IRQ_H__ #include <stdint.h> @@ -7,6 +7,15 @@ * Include file for interrupt service routines. */ +typedef enum { +#define IRQ_RESERVED(n) +#define IRQ(name_, uname, num) \ + IRQ_##uname = num, +#include "core/isrs.inc" +#undef IRQ +#undef IRQ_RESERVED +} interrupt_t; + /* * The interrupt service routines. These link in the function `main` as the * main function. @@ -21,4 +30,4 @@ void unhandled_isr(uint8_t val); void isr_simple_pin_on(); -#endif /* CORE_h___ISR_VECTOR_H__ */ +#endif /* CORE_IRQ_H_ */ diff --git a/02-usart/include/core/isrs.i b/02-usart/include/core/isrs.i deleted file mode 100644 index cdb3889..0000000 --- a/02-usart/include/core/isrs.i +++ /dev/null @@ -1,112 +0,0 @@ -/* - * The following is a list of interrupts listed in a way - * that makes it easy to macro-process them by defining - * macro definitions for IRQ and IRQ_RESERVED alike followed - * by including this file. - */ -IRQ(on_reset, 1) -IRQ(on_nmi, 2) -IRQ(on_hard_fault, 3) -IRQ(on_mem_manage, 4) -IRQ(on_bus_fault, 5) -IRQ(on_usage_fault, 6) -IRQ_RESERVED(7) -IRQ_RESERVED(8) -IRQ_RESERVED(9) -IRQ_RESERVED(10) -IRQ(on_svc, 11) -IRQ(on_debug_mon, 12) -IRQ_RESERVED(13) -IRQ(on_pendsv, 14) -IRQ(on_systick, 15) -IRQ(on_wwdg_irq, 16) -IRQ(on_pvd_irq, 17) -IRQ(on_tamper_stamp_irq, 18) -IRQ(on_rtc_wkup_irq, 19) -IRQ(on_flash_irq, 20) -IRQ(on_rcc_irq, 21) -IRQ(on_exti0_irq, 22) -IRQ(on_exti1_irq, 23) -IRQ(on_exti2_irq, 24) -IRQ(on_exti3_irq, 25) -IRQ(on_exti4_irq, 26) -IRQ(on_dma1_channel1_irq, 27) -IRQ(on_dma1_channel2_irq, 28) -IRQ(on_dma1_channel3_irq, 29) -IRQ(on_dma1_channel4_irq, 30) -IRQ(on_dma1_channel5_irq, 31) -IRQ(on_dma1_channel6_irq, 32) -IRQ(on_dma1_channel7_irq, 33) -IRQ(on_adc1_irq, 34) -IRQ(on_can1_tx, 35) -IRQ(on_can1_rx0, 36) -IRQ(on_can1_rx1, 37) -IRQ(on_can1_sce, 38) -IRQ(on_exti9_5, 39) -IRQ(on_tim1_brk, 40) -IRQ(on_tim1_up, 41) -IRQ(on_tim1_trg_com, 42) -IRQ(on_tim1_cc, 43) -IRQ(on_tim2, 44) -IRQ(on_tim3, 45) -IRQ(on_tim4, 46) -IRQ(on_i2c1_ev, 47) -IRQ(on_i2c1_er, 48) -IRQ(on_i2c2_ev, 49) -IRQ(on_i2c2_er, 50) -IRQ(on_spi1, 51) -IRQ(on_spi2, 52) -IRQ(on_usart1, 53) -IRQ(on_usart2, 54) -IRQ(on_usart3, 55) -IRQ(on_exti15_10, 56) -IRQ(on_rtc_alarm, 57) -IRQ(on_dfsdm1_flt3, 58) -IRQ(on_tim8_brk, 59) -IRQ(on_tim8_up, 60) -IRQ(on_tim8_trg_com, 61) -IRQ(on_tim8_cc, 62) -IRQ(on_adc3, 63) -IRQ(on_fmc, 64) -IRQ(on_sdmmc1, 65) -IRQ(on_tim5, 66) -IRQ(on_spi3, 67) -IRQ(on_uart4, 68) -IRQ(on_uart5, 69) -IRQ(on_tim6_dacunder, 70) -IRQ(on_tim7, 71) -IRQ(on_dma2_channel1, 72) -IRQ(on_dma2_channel2, 73) -IRQ(on_dma2_channel3, 74) -IRQ(on_dma2_channel4, 75) -IRQ(on_dma2_channel5, 76) -IRQ(on_dfsdm1_flt0, 77) -IRQ(on_dfsdm1_flt1, 78) -IRQ(on_dfsdm1_flt2, 79) -IRQ(on_comp, 80) -IRQ(on_lptim1, 81) -IRQ(on_lptim2, 82) -IRQ(on_otg_fs, 83) -IRQ(on_dma2_channel6, 84) -IRQ(on_dma2_channel7, 85) -IRQ(on_lpuart1, 86) -IRQ(on_quadspi, 87) -IRQ(on_i2c3_ev, 88) -IRQ(on_i2c3_er, 89) -IRQ(on_sai1, 90) -IRQ(on_sai2, 91) -IRQ(on_swpmi1, 92) -IRQ(on_tsc, 93) -IRQ(on_lcd, 94) -IRQ(on_aes, 95) -IRQ(on_rng, 96) -IRQ(on_fpu, 97) -IRQ(on_hash, 98) -IRQ(on_i2c4_ev, 99) -IRQ(on_i2c4_er, 100) -IRQ(on_dcmi, 101) -IRQ(on_can2_tx, 102) -IRQ(on_can2_rx0, 103) -IRQ(on_can2_rx1, 104) -IRQ(on_can2_sce, 105) -IRQ(on_dma2d, 106) diff --git a/02-usart/include/core/isrs.inc b/02-usart/include/core/isrs.inc new file mode 100644 index 0000000..e45e216 --- /dev/null +++ b/02-usart/include/core/isrs.inc @@ -0,0 +1,112 @@ +/* + * The following is a list of interrupts listed in a way + * that makes it easy to macro-process them by defining + * macro definitions for IRQ and IRQ_RESERVED alike followed + * by including this file. + */ +IRQ(on_reset, RESET, 1) +IRQ(on_nmi, NMI, 2) +IRQ(on_hard_fault, HARD_FAULT, 3) +IRQ(on_mem_manage, MEM_MANAGE, 4) +IRQ(on_bus_fault, BUS_FAULT, 5) +IRQ(on_usage_fault, USAGE_FAULT, 6) +IRQ_RESERVED(7) +IRQ_RESERVED(8) +IRQ_RESERVED(9) +IRQ_RESERVED(10) +IRQ(on_svc, SVC, 11) +IRQ(on_debug_mon, DEBUG_MON, 12) +IRQ_RESERVED(13) +IRQ(on_pendsv, PENDSV, 14) +IRQ(on_systick, SYSTICK, 15) +IRQ(on_wwdg_irq, WWDG_IRQ, 16) +IRQ(on_pvd_irq, PVD_IRQ, 17) +IRQ(on_tamper_stamp_irq, TAMPER_STAMP_IRQ, 18) +IRQ(on_rtc_wkup_irq, RTC_WKUP_IRQ, 19) +IRQ(on_flash_irq, FLASH_IRQ, 20) +IRQ(on_rcc_irq, RCC_IRQ, 21) +IRQ(on_exti0_irq, EXTI0_IRQ, 22) +IRQ(on_exti1_irq, EXTI1_IRQ, 23) +IRQ(on_exti2_irq, EXTI2_IRQ, 24) +IRQ(on_exti3_irq, EXTI3_IRQ, 25) +IRQ(on_exti4_irq, EXTI4_IRQ, 26) +IRQ(on_dma1_channel1_irq, DMA1_CHANNEL1_IRQ, 27) +IRQ(on_dma1_channel2_irq, DMA1_CHANNEL2_IRQ, 28) +IRQ(on_dma1_channel3_irq, DMA1_CHANNEL3_IRQ, 29) +IRQ(on_dma1_channel4_irq, DMA1_CHANNEL4_IRQ, 30) +IRQ(on_dma1_channel5_irq, DMA1_CHANNEL5_IRQ, 31) +IRQ(on_dma1_channel6_irq, DMA1_CHANNEL6_IRQ, 32) +IRQ(on_dma1_channel7_irq, DMA1_CHANNEL7_IRQ, 33) +IRQ(on_adc1_irq, ADC1_IRQ, 34) +IRQ(on_can1_tx, CAN1_TX, 35) +IRQ(on_can1_rx0, CAN1_RX0, 36) +IRQ(on_can1_rx1, CAN1_RX1, 37) +IRQ(on_can1_sce, CAN1_SCE, 38) +IRQ(on_exti9_5, EXTI9_5, 39) +IRQ(on_tim1_brk, TIM1_BRK, 40) +IRQ(on_tim1_up, TIM1_UP, 41) +IRQ(on_tim1_trg_com, TIM1_TRG_COM, 42) +IRQ(on_tim1_cc, TIM1_CC, 43) +IRQ(on_tim2, TIM2, 44) +IRQ(on_tim3, TIM3, 45) +IRQ(on_tim4, TIM4, 46) +IRQ(on_i2c1_ev, I2C1_EV, 47) +IRQ(on_i2c1_er, I2C1_ER, 48) +IRQ(on_i2c2_ev, I2C2_EV, 49) +IRQ(on_i2c2_er, I2C2_ER, 50) +IRQ(on_spi1, SPI1, 51) +IRQ(on_spi2, SPI2, 52) +IRQ(on_usart1, USART1, 53) +IRQ(on_usart2, USART2, 54) +IRQ(on_usart3, USART3, 55) +IRQ(on_exti15_10, EXTI15_10, 56) +IRQ(on_rtc_alarm, RTC_ALARM, 57) +IRQ(on_dfsdm1_flt3, DFSDM1_FLT3, 58) +IRQ(on_tim8_brk, TIM8_BRK, 59) +IRQ(on_tim8_up, TIM8_UP, 60) +IRQ(on_tim8_trg_com, TIM8_TRG_COM, 61) +IRQ(on_tim8_cc, TIM8_CC, 62) +IRQ(on_adc3, ADC3, 63) +IRQ(on_fmc, FMC, 64) +IRQ(on_sdmmc1, SDMMC1, 65) +IRQ(on_tim5, TIM5, 66) +IRQ(on_spi3, SPI3, 67) +IRQ(on_uart4, UART4, 68) +IRQ(on_uart5, UART5, 69) +IRQ(on_tim6_dacunder, TIM6_DACUNDER, 70) +IRQ(on_tim7, TIM7, 71) +IRQ(on_dma2_channel1, DMA2_CHANNEL1, 72) +IRQ(on_dma2_channel2, DMA2_CHANNEL2, 73) +IRQ(on_dma2_channel3, DMA2_CHANNEL3, 74) +IRQ(on_dma2_channel4, DMA2_CHANNEL4, 75) +IRQ(on_dma2_channel5, DMA2_CHANNEL5, 76) +IRQ(on_dfsdm1_flt0, DFSDM1_FLT0, 77) +IRQ(on_dfsdm1_flt1, DFSDM1_FLT1, 78) +IRQ(on_dfsdm1_flt2, DFSDM1_FLT2, 79) +IRQ(on_comp, COMP, 80) +IRQ(on_lptim1, LPTIM1, 81) +IRQ(on_lptim2, LPTIM2, 82) +IRQ(on_otg_fs, OTG_FS, 83) +IRQ(on_dma2_channel6, DMA2_CHANNEL6, 84) +IRQ(on_dma2_channel7, DMA2_CHANNEL7, 85) +IRQ(on_lpuart1, LPUART1, 86) +IRQ(on_quadspi, QUADSPI, 87) +IRQ(on_i2c3_ev, I2C3_EV, 88) +IRQ(on_i2c3_er, I2C3_ER, 89) +IRQ(on_sai1, SAI1, 90) +IRQ(on_sai2, SAI2, 91) +IRQ(on_swpmi1, SWPMI1, 92) +IRQ(on_tsc, TSC, 93) +IRQ(on_lcd, LCD, 94) +IRQ(on_aes, AES, 95) +IRQ(on_rng, RNG, 96) +IRQ(on_fpu, FPU, 97) +IRQ(on_hash, HASH, 98) +IRQ(on_i2c4_ev, I2C4_EV, 99) +IRQ(on_i2c4_er, I2C4_ER, 100) +IRQ(on_dcmi, DCMI, 101) +IRQ(on_can2_tx, CAN2_TX, 102) +IRQ(on_can2_rx0, CAN2_RX0, 103) +IRQ(on_can2_rx1, CAN2_RX1, 104) +IRQ(on_can2_sce, CAN2_SCE, 105) +IRQ(on_dma2d, DMA2D, 106) diff --git a/02-usart/src/core/isr_vector.c b/02-usart/src/core/irq.c index 9f3f560..c9b93c2 100644 --- a/02-usart/src/core/isr_vector.c +++ b/02-usart/src/core/irq.c @@ -1,4 +1,4 @@ -#include "core/isr_vector.h" +#include "core/irq.h" #include "core/gpio.h" #include "arch.h" @@ -7,15 +7,14 @@ #ifdef ARCH_STM32L4 #define IRQ_RESERVED(n) -#define IRQ(name, n) \ +#define IRQ(name, uname_, n) \ void WEAK name () { \ unhandled_isr(n); \ } -#include "core/isrs.i" +#include "core/isrs.inc" #undef IRQ_RESERVED #undef IRQ - void isr_simple_pin_on() { __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); @@ -24,34 +23,11 @@ void isr_simple_pin_on() pin_on(pin3); } -#define DEFINE_UNHANDLED_ISR(n) \ - int unhandled_isr_##n() \ - { \ - unhandled_isr(n); \ - } - - -/* Flashes wildly. */ -void super_flash() -{ - static int pin_on = 0; - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - - if (pin_on) { - pin_off(pin3); - } else { - pin_on(pin3); - } - - pin_on = !pin_on; -} - #define IRQ_RESERVED(n) 0, -#define IRQ(name, n) name, +#define IRQ(name, uname_, n) name, const void* vectors[] __attribute__((section(".vectors"))) = { (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ -#include "core/isrs.i" +#include "core/isrs.inc" }; #undef IRQ_RESERVED #undef IRQ @@ -63,9 +39,9 @@ const void* vectors[] __attribute__((section(".vectors"))) = { * followed by a pause will occur indicating that the next 8 flashes indicate * the bits of the provided code. * - * The next eight flashes are indicate either a 1 or 0 depending on the length - * of the light being on. The first flash is the least-significant bit, the next - * the second least, the third third least, etc. + * Eoch of the next eight flashes indicate either a 1 or 0 depending on the + * length of flash. The first flash is the least-significant bit, the next the + * second least, the third third least, etc. * * - A quick flash followed by a long pause indicates a 0 bit. * - A "long" flash followed by a equally long pause indicates a 1 bit. |