diff options
Diffstat (limited to 'include/arch/stm32l4xxx/peripherals/rcc.h')
| -rw-r--r-- | include/arch/stm32l4xxx/peripherals/rcc.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/include/arch/stm32l4xxx/peripherals/rcc.h b/include/arch/stm32l4xxx/peripherals/rcc.h index 65b2e86..cb04b94 100644 --- a/include/arch/stm32l4xxx/peripherals/rcc.h +++ b/include/arch/stm32l4xxx/peripherals/rcc.h @@ -80,8 +80,39 @@ typedef struct { __IO uint32_t reserved_5; /* Not used. offset 0x54. */ +#define rcc_lptim1en (1 << 31) /* Low power timer 1 clock enable */ +#define rcc_opampen (1 << 30) /* OPAMP interface clock enable */ +#define rcc_dac1en (1 << 29) /* DAC1 interface clock enable */ +#define rcc_pwren (1 << 28) /* Power interface clock enable */ +#define rcc_can2en (1 << 26) /* CAN2 clock enable (this bit is reserved for STM32L47x/L48x devices) */ +#define rcc_can1en (1 << 25) /* CAN1 clock enable */ +#define rcc_crsen (1 << 24) /* Clock Recovery System clock enable (this bit is reserved for STM32L47x/L48x */ +#define rcc_i2c3en (1 << 23) /* I2C3 clock enable */ +#define rcc_i2c2en (1 << 22) /* I2C2 clock enable */ +#define rcc_i2c1en (1 << 21) /* I2C1 clock enable */ +#define rcc_uart5en (1 << 20) /* UART5 clock enable */ +#define rcc_uart4en (1 << 19) /* UART4 clock enable */ +#define rcc_usart3en (1 << 18) /* USART3 clock enable */ +#define rcc_usart2en (1 << 17) /* USART2 clock enable */ +#define rcc_spi3en (1 << 15) /* SPI3 clock enable */ +#define rcc_spi2en (1 << 14) /* SPI2 clock enable */ +#define rcc_wwdgen (1 << 11) /* Window watchdog clock enable */ +#define rcc_rtcapben (1 << 10) /* RTC APB clock enable (this bit is reserved for STM32L47x/L48x devices) */ +#define rcc_lcden (1 << 9) /* LCD clock enable (this bit is reserved for STM32L471/L4x5 devices) */ +#define rcc_tim7en (1 << 5) /* TIM7 timer clock enable */ +#define rcc_tim6en (1 << 4) /* TIM6 timer clock enable */ +#define rcc_tim5en (1 << 3) /* TIM5 timer clock enable */ +#define rcc_tim4en (1 << 2) /* TIM4 timer clock enable */ +#define rcc_tim3en (1 << 1) /* TIM3 timer clock enable */ +#define rcc_tim2en (1 << 0) /* TIM2 timer clock enable */ __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ + +#define lptim2en (1 << 5) /*Low power timer 2 clock enable */ +#define swpmi1en (1 << 2) /* Single wire protocol clock enable */ +#define i2c4en (1 << 1) /* I2C4 clock enable (this bit is reserved for STM32L47x/L48x devices) */ +#define lpuart1en (1 << 0) /* Low power UART 1 clock enable */ __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ + #define rcc_syscfgen (1 << 0) #define rcc_fwen (1 << 7) #define rcc_sdmmc1en (1 << 10) |