3 files changed, 62 insertions, 29 deletions
diff --git a/include/arch/stm32l4xxx/peripherals/rcc.h b/include/arch/stm32l4xxx/peripherals/rcc.h
index 65b2e86..cb04b94 100644
--- a/include/arch/stm32l4xxx/peripherals/rcc.h
+++ b/include/arch/stm32l4xxx/peripherals/rcc.h
@@ -80,8 +80,39 @@ typedef struct {
 
   __IO uint32_t reserved_5; /* Not used. offset 0x54. */
 
+#define rcc_lptim1en (1 << 31) /* Low power timer 1 clock enable */
+#define rcc_opampen (1 << 30) /* OPAMP interface clock enable */
+#define rcc_dac1en (1 << 29) /* DAC1 interface clock enable */
+#define rcc_pwren (1 << 28) /* Power interface clock enable */
+#define rcc_can2en (1 << 26) /* CAN2 clock enable (this bit is reserved for STM32L47x/L48x devices) */
+#define rcc_can1en (1 << 25) /* CAN1 clock enable */
+#define rcc_crsen (1 << 24) /* Clock Recovery System clock enable (this bit is reserved for STM32L47x/L48x */
+#define rcc_i2c3en (1 << 23) /* I2C3 clock enable */
+#define rcc_i2c2en (1 << 22) /* I2C2 clock enable */
+#define rcc_i2c1en (1 << 21) /* I2C1 clock enable */
+#define rcc_uart5en (1 << 20) /* UART5 clock enable */
+#define rcc_uart4en (1 << 19) /* UART4 clock enable */
+#define rcc_usart3en (1 << 18) /* USART3 clock enable */
+#define rcc_usart2en (1 << 17) /* USART2 clock enable */
+#define rcc_spi3en (1 << 15) /* SPI3 clock enable */
+#define rcc_spi2en (1 << 14) /* SPI2 clock enable */
+#define rcc_wwdgen (1 << 11) /* Window watchdog clock enable */
+#define rcc_rtcapben (1 << 10) /* RTC APB clock enable (this bit is reserved for STM32L47x/L48x devices) */
+#define rcc_lcden (1 << 9) /* LCD clock enable (this bit is reserved for STM32L471/L4x5 devices) */
+#define rcc_tim7en (1 << 5) /* TIM7 timer clock enable */
+#define rcc_tim6en (1 << 4) /* TIM6 timer clock enable */
+#define rcc_tim5en (1 << 3) /* TIM5 timer clock enable */
+#define rcc_tim4en (1 << 2) /* TIM4 timer clock enable */
+#define rcc_tim3en (1 << 1) /* TIM3 timer clock enable */
+#define rcc_tim2en (1 << 0) /* TIM2 timer clock enable */
   __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */
+
+#define lptim2en (1 << 5) /*Low power timer 2 clock enable */
+#define swpmi1en (1 << 2) /* Single wire protocol clock enable */
+#define i2c4en (1 << 1) /* I2C4 clock enable (this bit is reserved for STM32L47x/L48x devices) */
+#define lpuart1en (1 << 0) /* Low power UART 1 clock enable */
   __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */
+
 #define rcc_syscfgen (1 << 0)
 #define rcc_fwen (1 << 7)
 #define rcc_sdmmc1en (1 << 10)
diff --git a/include/arch/stm32l4xxx/peripherals/spi.h b/include/arch/stm32l4xxx/peripherals/spi.h
index 478664e..eb9741e 100644
--- a/include/arch/stm32l4xxx/peripherals/spi.h
+++ b/include/arch/stm32l4xxx/peripherals/spi.h
@@ -4,38 +4,38 @@
 #include "kern/common.h"
 #include "arch.h"
 
-#define SPI1 (*((spi_t*)(SPI1_BASE)))
-#define SPI3 (*((spi_t*)(SPI3_BASE)))
+#define SPI1 (*((spi_regs_t*)(SPI1_BASE)))
+#define SPI3 (*((spi_regs_t*)(SPI3_BASE)))
 
 typedef enum {
-  SPI_BAUD_FPCLK_DIV_2   = 0,
-  SPI_BAUD_FPCLK_DIV_4   = 1,
-  SPI_BAUD_FPCLK_DIV_8   = 2,
-  SPI_BAUD_FPCLK_DIV_16  = 3,
-  SPI_BAUD_FPCLK_DIV_32  = 4,
-  SPI_BAUD_FPCLK_DIV_64  = 5,
-  SPI_BAUD_FPCLK_DIV_128 = 6,
-  SPI_BAUD_FPCLK_DIV_256 = 7,
+  SPI_BAUD_RATE_FPCLK_DIV_2   = 0,
+  SPI_BAUD_RATE_FPCLK_DIV_4   = 1,
+  SPI_BAUD_RATE_FPCLK_DIV_8   = 2,
+  SPI_BAUD_RATE_FPCLK_DIV_16  = 3,
+  SPI_BAUD_RATE_FPCLK_DIV_32  = 4,
+  SPI_BAUD_RATE_FPCLK_DIV_64  = 5,
+  SPI_BAUD_RATE_FPCLK_DIV_128 = 6,
+  SPI_BAUD_RATE_FPCLK_DIV_256 = 7,
 } spi_baud_rate_t;
 
 typedef enum {
-  SPI_DATA_SIZE_NOT_USED_0  = 0,
-  SPI_DATA_SIZE_NOT_USED_1  = 1,
-  SPI_DATA_SIZE_NOT_USED_2  = 2,
-  SPI_DATA_SIZE_4_BITS      = 3,
-  SPI_DATA_SIZE_5_BITS      = 4,
-  SPI_DATA_SIZE_6_BITS      = 5,
-  SPI_DATA_SIZE_7_BITS      = 6,
-  SPI_DATA_SIZE_8_BITS      = 7,
-  SPI_DATA_SIZE_9_BITS      = 8,
-  SPI_DATA_SIZE_10_BITS     = 9,
-  SPI_DATA_SIZE_11_BITS     = 10,
-  SPI_DATA_SIZE_12_BITS     = 11,
-  SPI_DATA_SIZE_13_BITS     = 12,
-  SPI_DATA_SIZE_14_BITS     = 13,
-  SPI_DATA_SIZE_15_BITS     = 14,
-  SPI_DATA_SIZE_16_BITS     = 15,
-} spi_data_size_t;
+  SPI_REG_DATA_SIZE_NOT_USED_0  = 0,
+  SPI_REG_DATA_SIZE_NOT_USED_1  = 1,
+  SPI_REG_DATA_SIZE_NOT_USED_2  = 2,
+  SPI_REG_DATA_SIZE_4_BITS      = 3,
+  SPI_REG_DATA_SIZE_5_BITS      = 4,
+  SPI_REG_DATA_SIZE_6_BITS      = 5,
+  SPI_REG_DATA_SIZE_7_BITS      = 6,
+  SPI_REG_DATA_SIZE_8_BITS      = 7,
+  SPI_REG_DATA_SIZE_9_BITS      = 8,
+  SPI_REG_DATA_SIZE_10_BITS     = 9,
+  SPI_REG_DATA_SIZE_11_BITS     = 10,
+  SPI_REG_DATA_SIZE_12_BITS     = 11,
+  SPI_REG_DATA_SIZE_13_BITS     = 12,
+  SPI_REG_DATA_SIZE_14_BITS     = 13,
+  SPI_REG_DATA_SIZE_15_BITS     = 14,
+  SPI_REG_DATA_SIZE_16_BITS     = 15,
+} spi_reg_data_size_t;
 
 typedef enum {
   SPI_FIFO_STATUS_EMPTY = 0,
@@ -110,8 +110,8 @@ typedef __IO struct {
 
   /* spi tx CRC register. */
   uint32_t txcrc_r;
-} spi_t;
+} spi_regs_t;
 
-static_assert(offsetof(spi_t, txcrc_r) == 0x18, "Offset check failed.");
+static_assert(offsetof(spi_regs_t, txcrc_r) == 0x18, "Offset check failed.");
 
 #endif /* CORE_SPI_H_ */
diff --git a/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc
new file mode 100644
index 0000000..5a91e8b
--- /dev/null
+++ b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/spi/buses.inc
@@ -0,0 +1,2 @@
+SPI(SPI1, SPI1)
+SPI(SPI2, SPI3) /* Stm32l432 doesn't have a SPI2. */