diff options
Diffstat (limited to 'system-clock/include')
| -rw-r--r-- | system-clock/include/clock.h | 49 | ||||
| -rw-r--r-- | system-clock/include/flash.h | 4 | ||||
| -rw-r--r-- | system-clock/include/gpio.h | 44 | ||||
| -rw-r--r-- | system-clock/include/isr_vector.h | 1 | ||||
| -rw-r--r-- | system-clock/include/rcc.h | 71 | ||||
| -rw-r--r-- | system-clock/include/spin.h | 2 |
6 files changed, 78 insertions, 93 deletions
diff --git a/system-clock/include/clock.h b/system-clock/include/clock.h index 98574d1..de4fb96 100644 --- a/system-clock/include/clock.h +++ b/system-clock/include/clock.h @@ -4,12 +4,11 @@ #include <stdint.h> #include "rcc.h" -#define PERIPH_BASE ((uint32_t) 0x40000000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) -#define PWR_BASE (PERIPH_BASE + 0x7000) -#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ - +#define PERIPH_BASE ((uint32_t)0x40000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) +#define PWR_BASE (PERIPH_BASE + 0x7000) +#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ #ifndef __IO #define __IO volatile @@ -29,26 +28,25 @@ typedef struct { // __IO uint32_t optkeyr; // __IO uint32_t sr; // __IO uint32_t obr; -// __IO uint32_t wrpr; +// __IO uint32_t wrpr; // } flash_t; // #define FLASH (*(flash_t*) (FLASH_R_BASE)) -#define PWR (*(pwr_t*) (PWR_BASE)) - +#define PWR (*(pwr_t*)(PWR_BASE)) /* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */ typedef enum { - PLL_DIVISOR_2 = 1, - PLL_DIVISOR_4 = 3, - PLL_DIVISOR_6 = 5, - PLL_DIVISOR_8 = 7, + PLL_DIVISOR_2 = 1, + PLL_DIVISOR_4 = 3, + PLL_DIVISOR_6 = 5, + PLL_DIVISOR_8 = 7, PLL_DIVISOR_OFF = 0, } pll_divisor_t; /* Valid values for the PLLP bits off the PLLCFG register. */ -typedef enum { - PLLP_DIVISOR_7 = 1, - PLLP_DIVISOR_17 = 3, +typedef enum { + PLLP_DIVISOR_7 = 1, + PLLP_DIVISOR_17 = 3, PLLP_DIVISOR_OFF = 0, } pllp_divisor_t; @@ -67,9 +65,9 @@ typedef enum { /* Possible sources for the input clock. */ typedef enum { PLL_SRC_NONE = 0, - PLL_SRC_MSI = 1, - PLL_SRC_HSI = 2, - PLL_SRC_HSE = 3, + PLL_SRC_MSI = 1, + PLL_SRC_HSI = 2, + PLL_SRC_HSE = 3, } pll_src_t; /* Valid sources for the system clock. */ @@ -110,12 +108,11 @@ int set_system_clock_src(system_clock_src_t src); * Configure the PLL. */ int configure_pll( - uint8_t pllp_div_factor, - pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */ ); + uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */); #endif /* CLOCK_H__ */ diff --git a/system-clock/include/flash.h b/system-clock/include/flash.h index ac63bf9..a163a25 100644 --- a/system-clock/include/flash.h +++ b/system-clock/include/flash.h @@ -7,7 +7,7 @@ * Header file for dealing with flash. */ -#define FLASH_BASE 0x40022000 +#define FLASH_BASE 0x40022000 typedef struct { __IO uint32_t ac_r; /* Flash access control register. */ @@ -15,6 +15,6 @@ typedef struct { /* TODO fill out the rest. */ } PACKED flash_t; -#define FLASH (*(__IO flash_t*) FLASH_BASE) +#define FLASH (*(__IO flash_t*)FLASH_BASE) #endif /* H__FLASH_ */ diff --git a/system-clock/include/gpio.h b/system-clock/include/gpio.h index 53ece32..a8f06e2 100644 --- a/system-clock/include/gpio.h +++ b/system-clock/include/gpio.h @@ -36,16 +36,16 @@ typedef struct GPIO_PORT_STR { * the stm32l432. */ typedef enum GPIO_PIN_ENUM { - PIN_0 = 0, - PIN_1 = 1, - PIN_2 = 2, - PIN_3 = 3, - PIN_4 = 4, - PIN_5 = 5, - PIN_6 = 6, - PIN_7 = 7, - PIN_8 = 8, - PIN_9 = 9, + PIN_0 = 0, + PIN_1 = 1, + PIN_2 = 2, + PIN_3 = 3, + PIN_4 = 4, + PIN_5 = 5, + PIN_6 = 6, + PIN_7 = 7, + PIN_8 = 8, + PIN_9 = 9, PIN_10 = 10, PIN_11 = 11, PIN_12 = 12, @@ -58,10 +58,10 @@ typedef enum GPIO_PIN_ENUM { * Enum defining the pin modes that are possible. */ typedef enum { - MODE_INPUT = 0, - MODE_OUTPUT = 1, + MODE_INPUT = 0, + MODE_OUTPUT = 1, MODE_ALTERNATE = 2, - MODE_ANALOG = 3 + MODE_ANALOG = 3 } gpio_pin_mode_t; /* @@ -90,17 +90,14 @@ typedef struct { * pin_mode: the mode to set the pin to. */ void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, - gpio_pin_t pin, - gpio_pin_mode_t pin_mode); + __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode); /* * Sets the given GPIO pin to be an output pin. Returns an output_pin struct * corresponding to */ gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, - gpio_pin_t pin); + __IO gpio_port_t* gpio_port, gpio_pin_t pin); /* * Sets an output pin on or off. @@ -108,15 +105,11 @@ gpio_output_pin_t set_gpio_pin_output( * pin: the pin to toggle. * onoff: 0 for off, non-zero of on. */ -void set_gpio_output_pin( - gpio_output_pin_t pin, - bool onoff); +void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff); -#define pin_on(p) \ - set_gpio_output_pin(p, 1) +#define pin_on(p) set_gpio_output_pin(p, 1) -#define pin_off(p) \ - set_gpio_output_pin(p, 0) +#define pin_off(p) set_gpio_output_pin(p, 0) /* * Enables a GPIO port and returns a reference to the register definition @@ -124,5 +117,4 @@ void set_gpio_output_pin( */ __IO gpio_port_t* enable_gpio(gpio_port_number_t number); - #endif /* GPIO_H__ */ diff --git a/system-clock/include/isr_vector.h b/system-clock/include/isr_vector.h index eee1a51..3e55f52 100644 --- a/system-clock/include/isr_vector.h +++ b/system-clock/include/isr_vector.h @@ -11,7 +11,6 @@ */ extern const void* isr_vector[]; - /* * Defines an error state. This loops forever and defines a distinct flashing * pattern to let the user know an unhandled ISR happened. diff --git a/system-clock/include/rcc.h b/system-clock/include/rcc.h index 4206dc1..4eeb26b 100644 --- a/system-clock/include/rcc.h +++ b/system-clock/include/rcc.h @@ -3,26 +3,26 @@ #include "common.h" -#define RCC_BASE ((uint32_t) 0x40021000) +#define RCC_BASE ((uint32_t)0x40021000) typedef struct { - __IO uint32_t c_r; /* Clock control register. 0x00 */ - __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ - __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ - __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ - __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ + __IO uint32_t c_r; /* Clock control register. 0x00 */ + __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ + __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ + __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ + __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ __IO uint32_t reserved_1; /* Not used. offset 0x14. */ - __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ - __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ - __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ + __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ + __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ + __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ __IO uint32_t reserved_2; /* Not used. offset 0x24. */ - __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ - __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ - __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ + __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ + __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ + __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ __IO uint32_t reserved_3; /* Not used. offset 0x34. */ @@ -32,15 +32,15 @@ typedef struct { __IO uint32_t reserved_4; /* Not used. offset 0x44. */ - __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ - __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ - __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ + __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ + __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ + __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ __IO uint32_t reserved_5; /* Not used. offset 0x54. */ - __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ - __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ - __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ + __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ + __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ + __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ __IO uint32_t reserved_6; /* Not used. offset 0x64. */ @@ -48,30 +48,29 @@ typedef struct { } PACKED rcc_t; -#define RCC (*(__IO rcc_t*) RCC_BASE) +#define RCC (*(__IO rcc_t*)RCC_BASE) /* Macros to operate on the RCC registers. */ /* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hse(rcc, e) do \ -{ \ - if (e) { \ - (rcc).c_r |= 1 << 16; \ - } else { \ - (rcc).c_r &= ~(1 << 16); \ - } \ -} while(0) +#define set_hse(rcc, e) \ + do { \ + if (e) { \ + (rcc).c_r |= 1 << 16; \ + } else { \ + (rcc).c_r &= ~(1 << 16); \ + } \ + } while (0) /* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hsi(rcc, e) do \ -{ \ - if (e) { \ - (rcc).c_r |= 1 << 8; \ - } else { \ - (rcc).c_r &= ~(1 << 8); \ - } \ -} while(0) - +#define set_hsi(rcc, e) \ + do { \ + if (e) { \ + (rcc).c_r |= 1 << 8; \ + } else { \ + (rcc).c_r &= ~(1 << 8); \ + } \ + } while (0) /* Checks to see if the hse is ready. */ #define hse_ready(rcc) ((rcc).c_r & (1 << 17)) diff --git a/system-clock/include/spin.h b/system-clock/include/spin.h index a88d2f8..a23d25b 100644 --- a/system-clock/include/spin.h +++ b/system-clock/include/spin.h @@ -12,6 +12,4 @@ */ void spin(uint32_t base_delay, uint8_t code); - - #endif /* H__SPIN_ */ |