diff options
Diffstat (limited to 'system-clock/src/clock.c')
| -rw-r--r-- | system-clock/src/clock.c | 53 |
1 files changed, 23 insertions, 30 deletions
diff --git a/system-clock/src/clock.c b/system-clock/src/clock.c index dd37684..75bac97 100644 --- a/system-clock/src/clock.c +++ b/system-clock/src/clock.c @@ -3,10 +3,10 @@ */ #include "clock.h" +#include <stdint.h> +#include "flash.h" #include "gpio.h" #include "spin.h" -#include "flash.h" -#include <stdint.h> #define TIMEOUT 10000 @@ -15,8 +15,9 @@ int pll_off() uint32_t c; RCC.c_r &= ~BIT(24); /* Turn off pll. */ - for(c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++ c); /* Wait for OFF. */ - + for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c) + ; /* Wait for OFF. */ + if (c == TIMEOUT) { return E_TIMEOUT; } @@ -29,7 +30,8 @@ int pll_on() uint32_t c; RCC.c_r |= BIT(24); /* Turn on PLL. */ - for(c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++ c); /* Wait for RDY. */ + for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c) + ; /* Wait for RDY. */ if (c == TIMEOUT) { return E_TIMEOUT; @@ -39,13 +41,12 @@ int pll_on() } int configure_pll( - uint8_t pllp_div_factor, - pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */ ) + uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */) { if (RCC.c_r & BIT(25)) { /* PLL must be off to configure it. */ @@ -60,18 +61,12 @@ int configure_pll( return E_BADPLLN; } - RCC.pllcfg_r = - (pllp_div_factor << 27) | - (pllr << 24) | - (pllq << 20) | - (pllp << 16) | - (plln << 8) | - (pllm << 4) | - (pllsrc << 0); + RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | + (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); return 0; } - + int set_system_clock_MHz(uint8_t mhz) { /* Set the source of the system colck to MSI temporarily. */ @@ -84,15 +79,13 @@ int set_system_clock_MHz(uint8_t mhz) pll_off(); configure_pll( - 0 /* pllp_div_factor */, - PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, - PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, - PLLP_DIVISOR_7 /* pllp */, - - /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. */ - mhz /* plln | mhz */, - PLLM_DIVISOR_1 /* pllm | 01 */, - PLL_SRC_MSI /* pll src | 04 Mhz */); + 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, + PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, + + /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. + */ + mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, + PLL_SRC_MSI /* pll src | 04 Mhz */); pll_on(); |