1 files changed, 64 insertions, 0 deletions
diff --git a/usart/src/usart.c b/usart/src/usart.c
new file mode 100644
index 0000000..23dbd95
--- /dev/null
+++ b/usart/src/usart.c
@@ -0,0 +1,64 @@
+#include "usart.h"
+#include "delay.h"
+
+void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src)
+{
+  rcc->ccip_r = rcc->ccip_r & (~0x03) | usart_clk_src;
+}
+
+void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src)
+{
+  rcc->ccip_r = rcc->ccip_r & ~(0x03 << 2) | (usart_clk_src << 2);
+}
+
+void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable)
+{
+  if (enable) {
+    rcc->apb1en1_r |= BIT(17);
+  } else {
+    rcc->apb1en1_r &= ~BIT(17);
+  }
+}
+
+void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable)
+{
+  if (enable) {
+    rcc->apb2en_r |= BIT(14);
+  } else {
+    rcc->apb2en_r &= ~BIT(14);
+  }
+}
+
+void usart_set_parity(__IO usart_t* usart, usart_parity_t parity)
+{
+  uint32_t c_r1 = usart->c_r1;
+  c_r1 &= ~(0x3 << 9);
+  c_r1 |= parity;
+  usart->c_r1 = c_r1;
+}
+
+void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled)
+{
+  uint32_t c_r1 = usart->c_r1;
+  /* Clear relevant bits. */
+  c_r1 &= ~USART_ENABLE_TX_RX;
+
+  /* Set TX/RX enabled, but not actually USART enabled. */
+  c_r1 |= (enabled & ~1);
+
+  /* Set usart enabled bit separately. */
+  c_r1 |= enabled & 1;
+
+  usart->c_r1 = c_r1;
+}
+
+void usart_transmit_byte(__IO usart_t* usart, uint8_t byte)
+{
+  usart->td_r = byte;
+  /* Per the manual, when bit 7 of the IS register is set, then the usart
+   * data has been sent to the shift register.
+   *
+   * This bit is cleared by writing to the TD register. */
+  while (!(usart->is_r & BIT(7)))
+    ;
+}