From 9f28e53c71d28d04e2775c59944d2887a99f1e86 Mon Sep 17 00:00:00 2001
From: Josh Rahm <joshuarahm@gmail.com>
Date: Sun, 22 Nov 2020 01:06:30 -0700
Subject: Large reorganization.

What was in core/ is now moved to arch/stm34l4xxx/peripherals.  This new
directory is *supposed to* to contain raw header files defining just the
pertinent register structures for the various peripherals.  Peripheral
management belongs somewhere in the new `kern/..` directories. This is
not completely the case at the moment, so more refactoring needs to be
done.

What was sitting in the root has now been moved into the kern/
directory. The kern/ directory is to contain everything else
other than raw device register definitions. The root of the kern/
tree is reserved for standard library-esque headers.

The kern/<peripheral> directory contains management systems for that
peripheral. (At the moment DMA is the only peripheral with a decent
management system.) Preferably these peripheral systems should only
include their correlating header in arch/stm34l4xxx/peripherals, and
use other management systems for handling other peripherals rather
than manipulating their raw registers directly. (Though this ideal
will require much more critical mass of management systems.)
---
 02-usart/include/core/clock.h | 126 ------------------------------------------
 1 file changed, 126 deletions(-)
 delete mode 100644 02-usart/include/core/clock.h

(limited to '02-usart/include/core/clock.h')

diff --git a/02-usart/include/core/clock.h b/02-usart/include/core/clock.h
deleted file mode 100644
index c3c58d7..0000000
--- a/02-usart/include/core/clock.h
+++ /dev/null
@@ -1,126 +0,0 @@
-#ifndef CORE_CLOCK_H__
-#define CORE_CLOCK_H__
-
-#include <stdint.h>
-#include "rcc.h"
-
-#define PERIPH_BASE ((uint32_t)0x40000000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00)
-#define PWR_BASE (PERIPH_BASE + 0x7000)
-#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
-
-#ifndef __IO
-#define __IO volatile
-#endif
-
-typedef struct {
-  __IO uint32_t cr;
-  __IO uint32_t csr;
-} pwr_t;
-
-// typedef struct {
-//   __IO uint32_t acr;
-//   __IO uint32_t pecr;
-//   __IO uint32_t pdkeyr;
-//   __IO uint32_t pekeyr;
-//   __IO uint32_t prgkeyr;
-//   __IO uint32_t optkeyr;
-//   __IO uint32_t sr;
-//   __IO uint32_t obr;
-//   __IO uint32_t wrpr;
-// } flash_t;
-
-// #define FLASH (*(flash_t*) (FLASH_R_BASE))
-#define PWR (*(pwr_t*)(PWR_BASE))
-
-/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */
-typedef enum {
-  PLL_DIVISOR_2 = 1,
-  PLL_DIVISOR_4 = 3,
-  PLL_DIVISOR_6 = 5,
-  PLL_DIVISOR_8 = 7,
-  PLL_DIVISOR_OFF = 0,
-} pll_divisor_t;
-
-/* Valid values for the PLLP bits off the PLLCFG register. */
-typedef enum {
-  PLLP_DIVISOR_7 = 1,
-  PLLP_DIVISOR_17 = 3,
-  PLLP_DIVISOR_OFF = 0,
-} pllp_divisor_t;
-
-/* Valid values for the PLLM bits of the PLLCFG register. */
-typedef enum {
-  PLLM_DIVISOR_1 = 0,
-  PLLM_DIVISOR_2 = 1,
-  PLLM_DIVISOR_3 = 2,
-  PLLM_DIVISOR_4 = 3,
-  PLLM_DIVISOR_5 = 4,
-  PLLM_DIVISOR_6 = 5,
-  PLLM_DIVISOR_7 = 6,
-  PLLM_DIVISOR_8 = 7,
-} pllm_divisor_t;
-
-/* Possible sources for the input clock. */
-typedef enum {
-  PLL_SRC_NONE = 0,
-  PLL_SRC_MSI = 1,
-  PLL_SRC_HSI = 2,
-  PLL_SRC_HSE = 3,
-} pll_src_t;
-
-/* Valid sources for the system clock. */
-typedef enum {
-  SYSTEM_CLOCK_SRC_MSI = 0,
-  SYSTEM_CLOCK_SRC_HSI = 1,
-  SYSTEM_CLOCK_SRC_HSE = 2,
-  SYSTEM_CLOCK_SRC_PLL = 3,
-} system_clock_src_t;
-
-#define E_BADPLLN (-2)
-#define E_BADPLLP_DIV (-1)
-#define E_TIMEOUT (-3)
-#define E_NOT_OFF (-4)
-#define E_BAD_ARG (-5)
-
-#define enable_hsi(rcc, enabled) do { \
-  if (enabled) { \
-    (rcc)->c_r |= BIT(8); \
-  } else { \
-    (rcc)->c_r &= ~BIT(8); \
-  } \
-} while(0)
-
-/*
- * Sets the system clock to a full 80Mhz.
- */
-int set_system_clock_MHz(uint8_t mhz);
-
-/*
- * Set the PLL on.
- */
-int pll_on();
-
-/*
- * Set the PLL off.
- */
-int pll_off();
-
-/*
- * Sets the source of the system clock.
- */
-int set_system_clock_src(system_clock_src_t src);
-
-/*
- * Configure the PLL.
- */
-int configure_pll(
-    uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */
-    pll_divisor_t pllq,  /* Divison factor for PLL48M1CLK. */
-    pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */
-    uint8_t plln,        /* PLL numerator. */
-    pllm_divisor_t pllm, /* PLL denominator. */
-    pll_src_t pllsrc /* PLL source */);
-
-#endif /* CORE_CLOCK_H__ */
-- 
cgit