From 9f28e53c71d28d04e2775c59944d2887a99f1e86 Mon Sep 17 00:00:00 2001
From: Josh Rahm <joshuarahm@gmail.com>
Date: Sun, 22 Nov 2020 01:06:30 -0700
Subject: Large reorganization.

What was in core/ is now moved to arch/stm34l4xxx/peripherals.  This new
directory is *supposed to* to contain raw header files defining just the
pertinent register structures for the various peripherals.  Peripheral
management belongs somewhere in the new `kern/..` directories. This is
not completely the case at the moment, so more refactoring needs to be
done.

What was sitting in the root has now been moved into the kern/
directory. The kern/ directory is to contain everything else
other than raw device register definitions. The root of the kern/
tree is reserved for standard library-esque headers.

The kern/<peripheral> directory contains management systems for that
peripheral. (At the moment DMA is the only peripheral with a decent
management system.) Preferably these peripheral systems should only
include their correlating header in arch/stm34l4xxx/peripherals, and
use other management systems for handling other peripherals rather
than manipulating their raw registers directly. (Though this ideal
will require much more critical mass of management systems.)
---
 02-usart/src/core/irq.c | 92 -------------------------------------------------
 1 file changed, 92 deletions(-)
 delete mode 100644 02-usart/src/core/irq.c

(limited to '02-usart/src/core/irq.c')

diff --git a/02-usart/src/core/irq.c b/02-usart/src/core/irq.c
deleted file mode 100644
index 47ad924..0000000
--- a/02-usart/src/core/irq.c
+++ /dev/null
@@ -1,92 +0,0 @@
-#include "core/irq.h"
-#include "core/gpio.h"
-#include "core/nvic.h"
-
-#include "arch.h"
-#include "delay.h"
-
-#define IRQ_RESERVED(n)
-#define IRQ(name, uname_, n) \
-  void WEAK name () { \
-    unhandled_isr(n); \
-  }
-#include "core/isrs.inc"
-#undef IRQ_RESERVED
-#undef IRQ
-
-void isr_simple_pin_on()
-{
-  __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B);
-  gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3);
-
-  pin_on(pin3);
-}
-
-#define IRQ_RESERVED(n) 0,
-#define IRQ(name, uname_, n) name,
-const void* vectors[] __attribute__((section(".vectors"))) = {
-    (void*)0x2000c000, /* Top of stack at top of sram1. 48k */
-#include "core/isrs.inc"
-};
-#undef IRQ_RESERVED
-#undef IRQ
-
-/* Encodes the provided number as a series of flashes on the on-board
- * LED. The flashes follow as such:
- *
- * Before the bits of the code are flashed, a rapid succession of 20 flashes
- * followed by a pause will occur indicating that the next 8 flashes indicate
- * the bits of the provided code.
- *
- * Eoch of the next eight flashes indicate either a 1 or 0 depending on the
- * length of flash. The first flash is the least-significant bit, the next the
- * second least, the third third least, etc.
- *
- * - A quick flash followed by a long pause indicates a 0 bit.
- * - A "long" flash followed by a equally long pause indicates a 1 bit.
- */
-void unhandled_isr(uint8_t number)
-{
-  __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B);
-  gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3);
-  for (;;) {
-    for (int i = 0; i < 20; ++ i) {
-       pin_on(pin3);
-       delay(1000000);
-       pin_off(pin3);
-       delay(1000000);
-    }
-    delay(50000000);
-
-    int n = number;
-    for (int i = 0; i < 8; ++ i) {
-      if (n & 1) {
-       // LSB is a 1
-       pin_on(pin3);
-       delay(15000000);
-       pin_off(pin3);
-       delay(15000000);
-      } else {
-       // LSB is a 0
-       pin_on(pin3);
-       delay(1000000);
-       pin_off(pin3);
-       delay(29000000);
-      }
-
-      n >>= 1;
-    }
-  }
-}
-
-void enable_interrupts(interrupt_set_t* interrupts)
-{
-  for (int i = 0; i < sizeof(NVIC.ise_r) / sizeof(uint32_t); ++ i)
-    NVIC.ise_r[i] = interrupts->irqs[i];
-}
-
-void disable_interrupts(interrupt_set_t* interrupts)
-{
-  for (int i = 0; i < sizeof(NVIC.ise_r) / sizeof(uint32_t); ++ i)
-    NVIC.ice_r[i] = interrupts->irqs[i];
-}
-- 
cgit