From 9f28e53c71d28d04e2775c59944d2887a99f1e86 Mon Sep 17 00:00:00 2001 From: Josh Rahm Date: Sun, 22 Nov 2020 01:06:30 -0700 Subject: Large reorganization. What was in core/ is now moved to arch/stm34l4xxx/peripherals. This new directory is *supposed to* to contain raw header files defining just the pertinent register structures for the various peripherals. Peripheral management belongs somewhere in the new `kern/..` directories. This is not completely the case at the moment, so more refactoring needs to be done. What was sitting in the root has now been moved into the kern/ directory. The kern/ directory is to contain everything else other than raw device register definitions. The root of the kern/ tree is reserved for standard library-esque headers. The kern/ directory contains management systems for that peripheral. (At the moment DMA is the only peripheral with a decent management system.) Preferably these peripheral systems should only include their correlating header in arch/stm34l4xxx/peripherals, and use other management systems for handling other peripherals rather than manipulating their raw registers directly. (Though this ideal will require much more critical mass of management systems.) --- 02-usart/tests/test_irq.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to '02-usart/tests/test_irq.c') diff --git a/02-usart/tests/test_irq.c b/02-usart/tests/test_irq.c index 89eea11..3c4ee9c 100644 --- a/02-usart/tests/test_irq.c +++ b/02-usart/tests/test_irq.c @@ -1,7 +1,7 @@ #include "test_harness.h" -#include "core/irq.h" -#include "core/nvic.h" +#include "arch/stm32l4xxx/peripherals/irq.h" +#include "arch/stm32l4xxx/peripherals/nvic.h" TEST(irq, nvic) { @@ -14,6 +14,8 @@ TEST(irq, nvic) ASSERT_EQ(is.irqs[1], 0xC0); ASSERT_EQ(NVIC.ise_r[1], 0xC0); + + return 0; } TEST(irq, nvic_edgecase) @@ -28,10 +30,14 @@ TEST(irq, nvic_edgecase) ASSERT_EQ(NVIC.ise_r[0], 1); ASSERT_EQ(is.irqs[1], 1); ASSERT_EQ(NVIC.ise_r[1], 1); + + return 0; } TEST(irq, enable_single_interrupt) { enable_interrupt(IRQ_USART2); ASSERT_EQ(NVIC.ise_r[1], 0x40); + + return 0; } -- cgit