From 93b063fedfcf7409a67df035170ea5670cad22e1 Mon Sep 17 00:00:00 2001 From: Josh Rahm Date: Tue, 24 Nov 2020 13:46:41 -0700 Subject: Moved action to top level. Removed old iterations of the project and moved the files from 02-usart to the root directory since that's the sole place where the action is and that subproject has outgrown its initial title. --- .gdbinit | 1 + .ycm_extra_conf.py | 21 ++ 00-hello/Makefile | 17 - 00-hello/README | 19 - 00-hello/linker_script.ld | 14 - 00-hello/main.c | 354 ------------------ 01-system-clock/Makefile.preamble | 21 -- 01-system-clock/README | 17 - 01-system-clock/genmake.pl | 70 ---- 01-system-clock/include/clock.h | 118 ------ 01-system-clock/include/common.h | 14 - 01-system-clock/include/delay.h | 12 - 01-system-clock/include/flash.h | 20 - 01-system-clock/include/gpio.h | 120 ------ 01-system-clock/include/isr_vector.h | 20 - 01-system-clock/include/rcc.h | 81 ----- 01-system-clock/include/spin.h | 15 - 01-system-clock/linker/linker_script.ld | 36 -- 01-system-clock/src/clock.c | 106 ------ 01-system-clock/src/delay.c | 9 - 01-system-clock/src/gpio.c | 37 -- 01-system-clock/src/isr_vector.c | 165 --------- 01-system-clock/src/main.c | 36 -- 01-system-clock/src/spin.c | 49 --- 01-system-clock/src/vector.c | 0 02-usart/.gdbinit | 1 - 02-usart/.ycm_extra_conf.py | 21 -- 02-usart/Makefile.preamble | 25 -- 02-usart/genmake.pl | 128 ------- 02-usart/include/arch/arm/arch.h | 43 --- 02-usart/include/arch/stm32l4xxx/peripherals/apb.h | 4 - .../include/arch/stm32l4xxx/peripherals/clock.h | 128 ------- 02-usart/include/arch/stm32l4xxx/peripherals/dma.h | 149 -------- .../include/arch/stm32l4xxx/peripherals/flash.h | 20 - .../include/arch/stm32l4xxx/peripherals/gpio.h | 66 ---- 02-usart/include/arch/stm32l4xxx/peripherals/irq.h | 89 ----- .../include/arch/stm32l4xxx/peripherals/isrs.inc | 112 ------ .../include/arch/stm32l4xxx/peripherals/nvic.h | 46 --- 02-usart/include/arch/stm32l4xxx/peripherals/rcc.h | 132 ------- 02-usart/include/arch/stm32l4xxx/peripherals/spi.h | 102 ------ .../include/arch/stm32l4xxx/peripherals/system.h | 76 ---- .../tables/stm32l432xx/gpio/afn_table.inc | 100 ----- .../tables/stm32l432xx/gpio/port_table.inc | 26 -- .../include/arch/stm32l4xxx/peripherals/usart.h | 204 ----------- 02-usart/include/arch/x86_64/arch.h | 37 -- 02-usart/include/kern/common.h | 50 --- 02-usart/include/kern/delay.h | 12 - 02-usart/include/kern/dma/dma_manager.h | 279 -------------- 02-usart/include/kern/gpio/gpio_manager.h | 187 ---------- 02-usart/include/kern/gpio/sysled.h | 11 - 02-usart/include/kern/init.h | 67 ---- 02-usart/include/kern/lib.h | 10 - 02-usart/include/kern/log.h | 12 - 02-usart/include/kern/mem.h | 32 -- 02-usart/include/kern/string.h | 6 - 02-usart/linker/linker_script.ld | 55 --- 02-usart/src/arch/stm32l4xxx/peripherals/clock.c | 117 ------ 02-usart/src/arch/stm32l4xxx/peripherals/irq.c | 96 ----- 02-usart/src/arch/stm32l4xxx/peripherals/usart.c | 152 -------- 02-usart/src/kern/delay.c | 9 - 02-usart/src/kern/dma/dma_manager.c | 311 ---------------- 02-usart/src/kern/gpio/gpio_manager.c | 402 --------------------- 02-usart/src/kern/gpio/sysled.c | 14 - 02-usart/src/kern/init.c | 82 ----- 02-usart/src/kern/lib.c | 56 --- 02-usart/src/kern/log.c | 55 --- 02-usart/src/kern/main.c | 29 -- 02-usart/src/kern/mem.c | 280 -------------- 02-usart/src/kern/stdlibrepl.c | 13 - 02-usart/src/kern/string.c | 9 - 02-usart/src/kern/vector.c | 0 02-usart/test_harness/Makefile | 9 - 02-usart/test_harness/fake_env.c | 63 ---- 02-usart/test_harness/fake_env.h | 20 - 02-usart/test_harness/test_harness.c | 181 ---------- 02-usart/test_harness/test_harness.h | 101 ------ 02-usart/tests/metatest.c | 22 -- 02-usart/tests/test_dma.c | 189 ---------- 02-usart/tests/test_gpio.c | 194 ---------- 02-usart/tests/test_irq.c | 43 --- 02-usart/tests/test_lib.c | 21 -- 02-usart/tests/test_memory.c | 378 ------------------- 02-usart/tests/test_spi.c | 11 - 02-usart/tests/test_usart.c | 22 -- 02.5-collatz/Makefile.preamble | 21 -- 02.5-collatz/genmake.pl | 70 ---- 02.5-collatz/include/apb.h | 4 - 02.5-collatz/include/clock.h | 126 ------- 02.5-collatz/include/common.h | 30 -- 02.5-collatz/include/delay.h | 12 - 02.5-collatz/include/flash.h | 20 - 02.5-collatz/include/gpio.h | 146 -------- 02.5-collatz/include/isr_vector.h | 20 - 02.5-collatz/include/rcc.h | 93 ----- 02.5-collatz/include/spin.h | 15 - 02.5-collatz/include/usart.h | 131 ------- 02.5-collatz/linker/linker_script.ld | 36 -- 02.5-collatz/src/clock.c | 106 ------ 02.5-collatz/src/delay.c | 9 - 02.5-collatz/src/gpio.c | 52 --- 02.5-collatz/src/isr_vector.c | 165 --------- 02.5-collatz/src/main.c | 93 ----- 02.5-collatz/src/spin.c | 49 --- 02.5-collatz/src/usart.c | 80 ---- 02.5-collatz/src/vector.c | 0 03-refactor/Makefile.preamble | 21 -- 03-refactor/genmake.pl | 70 ---- 03-refactor/include/apb.h | 4 - 03-refactor/include/clock.h | 112 ------ 03-refactor/include/common.h | 30 -- 03-refactor/include/delay.h | 12 - 03-refactor/include/flash.h | 20 - 03-refactor/include/gpio.h | 146 -------- 03-refactor/include/isr_vector.h | 20 - 03-refactor/include/printf.h | 15 - 03-refactor/include/rcc.h | 181 ---------- 03-refactor/include/spin.h | 15 - 03-refactor/include/usart.h | 219 ----------- 03-refactor/linker/linker_script.ld | 36 -- 03-refactor/src/clock.c | 131 ------- 03-refactor/src/delay.c | 9 - 03-refactor/src/gpio.c | 52 --- 03-refactor/src/isr_vector.c | 275 -------------- 03-refactor/src/main.c | 103 ------ 03-refactor/src/printf.c | 152 -------- 03-refactor/src/spin.c | 49 --- 03-refactor/src/usart.c | 131 ------- 03-refactor/src/vector.c | 0 Makefile.preamble | 25 ++ genmake.pl | 128 +++++++ include/arch/arm/arch.h | 43 +++ include/arch/stm32l4xxx/peripherals/apb.h | 4 + include/arch/stm32l4xxx/peripherals/clock.h | 128 +++++++ include/arch/stm32l4xxx/peripherals/dma.h | 149 ++++++++ include/arch/stm32l4xxx/peripherals/flash.h | 20 + include/arch/stm32l4xxx/peripherals/gpio.h | 66 ++++ include/arch/stm32l4xxx/peripherals/irq.h | 89 +++++ include/arch/stm32l4xxx/peripherals/isrs.inc | 112 ++++++ include/arch/stm32l4xxx/peripherals/nvic.h | 46 +++ include/arch/stm32l4xxx/peripherals/rcc.h | 132 +++++++ include/arch/stm32l4xxx/peripherals/spi.h | 102 ++++++ include/arch/stm32l4xxx/peripherals/system.h | 76 ++++ .../tables/stm32l432xx/gpio/afn_table.inc | 100 +++++ .../tables/stm32l432xx/gpio/port_table.inc | 26 ++ include/arch/stm32l4xxx/peripherals/usart.h | 204 +++++++++++ include/arch/x86_64/arch.h | 37 ++ include/kern/common.h | 50 +++ include/kern/delay.h | 12 + include/kern/dma/dma_manager.h | 279 ++++++++++++++ include/kern/gpio/gpio_manager.h | 187 ++++++++++ include/kern/gpio/sysled.h | 11 + include/kern/init.h | 67 ++++ include/kern/lib.h | 10 + include/kern/log.h | 12 + include/kern/mem.h | 32 ++ include/kern/string.h | 6 + linker/linker_script.ld | 55 +++ src/arch/stm32l4xxx/peripherals/clock.c | 117 ++++++ src/arch/stm32l4xxx/peripherals/irq.c | 96 +++++ src/arch/stm32l4xxx/peripherals/usart.c | 152 ++++++++ src/kern/delay.c | 9 + src/kern/dma/dma_manager.c | 311 ++++++++++++++++ src/kern/gpio/gpio_manager.c | 402 +++++++++++++++++++++ src/kern/gpio/sysled.c | 14 + src/kern/init.c | 82 +++++ src/kern/lib.c | 56 +++ src/kern/log.c | 55 +++ src/kern/main.c | 29 ++ src/kern/mem.c | 280 ++++++++++++++ src/kern/stdlibrepl.c | 13 + src/kern/string.c | 9 + src/kern/vector.c | 0 test_harness/Makefile | 9 + test_harness/fake_env.c | 63 ++++ test_harness/fake_env.h | 20 + test_harness/test_harness.c | 181 ++++++++++ test_harness/test_harness.h | 101 ++++++ tests/metatest.c | 22 ++ tests/test_dma.c | 189 ++++++++++ tests/test_gpio.c | 194 ++++++++++ tests/test_irq.c | 43 +++ tests/test_lib.c | 21 ++ tests/test_memory.c | 378 +++++++++++++++++++ tests/test_spi.c | 11 + tests/test_usart.c | 22 ++ 185 files changed, 5109 insertions(+), 9540 deletions(-) create mode 100644 .gdbinit create mode 100644 .ycm_extra_conf.py delete mode 100644 00-hello/Makefile delete mode 100644 00-hello/README delete mode 100644 00-hello/linker_script.ld delete mode 100644 00-hello/main.c delete mode 100644 01-system-clock/Makefile.preamble delete mode 100644 01-system-clock/README delete mode 100755 01-system-clock/genmake.pl delete mode 100644 01-system-clock/include/clock.h delete mode 100644 01-system-clock/include/common.h delete mode 100644 01-system-clock/include/delay.h delete mode 100644 01-system-clock/include/flash.h delete mode 100644 01-system-clock/include/gpio.h delete mode 100644 01-system-clock/include/isr_vector.h delete mode 100644 01-system-clock/include/rcc.h delete mode 100644 01-system-clock/include/spin.h delete mode 100644 01-system-clock/linker/linker_script.ld delete mode 100644 01-system-clock/src/clock.c delete mode 100644 01-system-clock/src/delay.c delete mode 100644 01-system-clock/src/gpio.c delete mode 100644 01-system-clock/src/isr_vector.c delete mode 100644 01-system-clock/src/main.c delete mode 100644 01-system-clock/src/spin.c delete mode 100644 01-system-clock/src/vector.c delete mode 100644 02-usart/.gdbinit delete mode 100644 02-usart/.ycm_extra_conf.py delete mode 100644 02-usart/Makefile.preamble delete mode 100755 02-usart/genmake.pl delete mode 100644 02-usart/include/arch/arm/arch.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/apb.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/clock.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/dma.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/flash.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/gpio.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/irq.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/isrs.inc delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/nvic.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/rcc.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/spi.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/system.h delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc delete mode 100644 02-usart/include/arch/stm32l4xxx/peripherals/usart.h delete mode 100644 02-usart/include/arch/x86_64/arch.h delete mode 100644 02-usart/include/kern/common.h delete mode 100644 02-usart/include/kern/delay.h delete mode 100644 02-usart/include/kern/dma/dma_manager.h delete mode 100644 02-usart/include/kern/gpio/gpio_manager.h delete mode 100644 02-usart/include/kern/gpio/sysled.h delete mode 100644 02-usart/include/kern/init.h delete mode 100644 02-usart/include/kern/lib.h delete mode 100644 02-usart/include/kern/log.h delete mode 100644 02-usart/include/kern/mem.h delete mode 100644 02-usart/include/kern/string.h delete mode 100644 02-usart/linker/linker_script.ld delete mode 100644 02-usart/src/arch/stm32l4xxx/peripherals/clock.c delete mode 100644 02-usart/src/arch/stm32l4xxx/peripherals/irq.c delete mode 100644 02-usart/src/arch/stm32l4xxx/peripherals/usart.c delete mode 100644 02-usart/src/kern/delay.c delete mode 100644 02-usart/src/kern/dma/dma_manager.c delete mode 100644 02-usart/src/kern/gpio/gpio_manager.c delete mode 100644 02-usart/src/kern/gpio/sysled.c delete mode 100644 02-usart/src/kern/init.c delete mode 100644 02-usart/src/kern/lib.c delete mode 100644 02-usart/src/kern/log.c delete mode 100644 02-usart/src/kern/main.c delete mode 100644 02-usart/src/kern/mem.c delete mode 100644 02-usart/src/kern/stdlibrepl.c delete mode 100644 02-usart/src/kern/string.c delete mode 100644 02-usart/src/kern/vector.c delete mode 100644 02-usart/test_harness/Makefile delete mode 100644 02-usart/test_harness/fake_env.c delete mode 100644 02-usart/test_harness/fake_env.h delete mode 100644 02-usart/test_harness/test_harness.c delete mode 100644 02-usart/test_harness/test_harness.h delete mode 100644 02-usart/tests/metatest.c delete mode 100644 02-usart/tests/test_dma.c delete mode 100644 02-usart/tests/test_gpio.c delete mode 100644 02-usart/tests/test_irq.c delete mode 100644 02-usart/tests/test_lib.c delete mode 100644 02-usart/tests/test_memory.c delete mode 100644 02-usart/tests/test_spi.c delete mode 100644 02-usart/tests/test_usart.c delete mode 100644 02.5-collatz/Makefile.preamble delete mode 100755 02.5-collatz/genmake.pl delete mode 100644 02.5-collatz/include/apb.h delete mode 100644 02.5-collatz/include/clock.h delete mode 100644 02.5-collatz/include/common.h delete mode 100644 02.5-collatz/include/delay.h delete mode 100644 02.5-collatz/include/flash.h delete mode 100644 02.5-collatz/include/gpio.h delete mode 100644 02.5-collatz/include/isr_vector.h delete mode 100644 02.5-collatz/include/rcc.h delete mode 100644 02.5-collatz/include/spin.h delete mode 100644 02.5-collatz/include/usart.h delete mode 100644 02.5-collatz/linker/linker_script.ld delete mode 100644 02.5-collatz/src/clock.c delete mode 100644 02.5-collatz/src/delay.c delete mode 100644 02.5-collatz/src/gpio.c delete mode 100644 02.5-collatz/src/isr_vector.c delete mode 100644 02.5-collatz/src/main.c delete mode 100644 02.5-collatz/src/spin.c delete mode 100644 02.5-collatz/src/usart.c delete mode 100644 02.5-collatz/src/vector.c delete mode 100644 03-refactor/Makefile.preamble delete mode 100755 03-refactor/genmake.pl delete mode 100644 03-refactor/include/apb.h delete mode 100644 03-refactor/include/clock.h delete mode 100644 03-refactor/include/common.h delete mode 100644 03-refactor/include/delay.h delete mode 100644 03-refactor/include/flash.h delete mode 100644 03-refactor/include/gpio.h delete mode 100644 03-refactor/include/isr_vector.h delete mode 100644 03-refactor/include/printf.h delete mode 100644 03-refactor/include/rcc.h delete mode 100644 03-refactor/include/spin.h delete mode 100644 03-refactor/include/usart.h delete mode 100644 03-refactor/linker/linker_script.ld delete mode 100644 03-refactor/src/clock.c delete mode 100644 03-refactor/src/delay.c delete mode 100644 03-refactor/src/gpio.c delete mode 100644 03-refactor/src/isr_vector.c delete mode 100644 03-refactor/src/main.c delete mode 100644 03-refactor/src/printf.c delete mode 100644 03-refactor/src/spin.c delete mode 100644 03-refactor/src/usart.c delete mode 100644 03-refactor/src/vector.c create mode 100644 Makefile.preamble create mode 100755 genmake.pl create mode 100644 include/arch/arm/arch.h create mode 100644 include/arch/stm32l4xxx/peripherals/apb.h create mode 100644 include/arch/stm32l4xxx/peripherals/clock.h create mode 100644 include/arch/stm32l4xxx/peripherals/dma.h create mode 100644 include/arch/stm32l4xxx/peripherals/flash.h create mode 100644 include/arch/stm32l4xxx/peripherals/gpio.h create mode 100644 include/arch/stm32l4xxx/peripherals/irq.h create mode 100644 include/arch/stm32l4xxx/peripherals/isrs.inc create mode 100644 include/arch/stm32l4xxx/peripherals/nvic.h create mode 100644 include/arch/stm32l4xxx/peripherals/rcc.h create mode 100644 include/arch/stm32l4xxx/peripherals/spi.h create mode 100644 include/arch/stm32l4xxx/peripherals/system.h create mode 100644 include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc create mode 100644 include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc create mode 100644 include/arch/stm32l4xxx/peripherals/usart.h create mode 100644 include/arch/x86_64/arch.h create mode 100644 include/kern/common.h create mode 100644 include/kern/delay.h create mode 100644 include/kern/dma/dma_manager.h create mode 100644 include/kern/gpio/gpio_manager.h create mode 100644 include/kern/gpio/sysled.h create mode 100644 include/kern/init.h create mode 100644 include/kern/lib.h create mode 100644 include/kern/log.h create mode 100644 include/kern/mem.h create mode 100644 include/kern/string.h create mode 100644 linker/linker_script.ld create mode 100644 src/arch/stm32l4xxx/peripherals/clock.c create mode 100644 src/arch/stm32l4xxx/peripherals/irq.c create mode 100644 src/arch/stm32l4xxx/peripherals/usart.c create mode 100644 src/kern/delay.c create mode 100644 src/kern/dma/dma_manager.c create mode 100644 src/kern/gpio/gpio_manager.c create mode 100644 src/kern/gpio/sysled.c create mode 100644 src/kern/init.c create mode 100644 src/kern/lib.c create mode 100644 src/kern/log.c create mode 100644 src/kern/main.c create mode 100644 src/kern/mem.c create mode 100644 src/kern/stdlibrepl.c create mode 100644 src/kern/string.c create mode 100644 src/kern/vector.c create mode 100644 test_harness/Makefile create mode 100644 test_harness/fake_env.c create mode 100644 test_harness/fake_env.h create mode 100644 test_harness/test_harness.c create mode 100644 test_harness/test_harness.h create mode 100644 tests/metatest.c create mode 100644 tests/test_dma.c create mode 100644 tests/test_gpio.c create mode 100644 tests/test_irq.c create mode 100644 tests/test_lib.c create mode 100644 tests/test_memory.c create mode 100644 tests/test_spi.c create mode 100644 tests/test_usart.c diff --git a/.gdbinit b/.gdbinit new file mode 100644 index 0000000..87932b3 --- /dev/null +++ b/.gdbinit @@ -0,0 +1 @@ +set follow-fork-mode child diff --git a/.ycm_extra_conf.py b/.ycm_extra_conf.py new file mode 100644 index 0000000..8203412 --- /dev/null +++ b/.ycm_extra_conf.py @@ -0,0 +1,21 @@ +import os +import ycm_core + +flags = [ + '-Wall', + '-DFOR_TESTING', + '-Iinclude', + '-Iinclude/arch/arm', + '-Itest_harness/', + '-DARCH_STMT32L4', + '-DDRY_RUN', + # -Iinclude/arch/arm -Itest_harness/ -DARCH_STM32L4 -DDRY_RUN -Wall -DFOR_TESTINGk + ] + +SOURCE_EXTENSIONS = [ '.cpp', '.cxx', '.cc', '.c', ] + +def FlagsForFile( filename, **kwargs ): + return { + 'flags': flags, + 'do_cache': True + } diff --git a/00-hello/Makefile b/00-hello/Makefile deleted file mode 100644 index 9c62c90..0000000 --- a/00-hello/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -OPT?=-O3 -all: main.bin - -main.s: main.c - arm-unknown-eabi-gcc $(OPT) -S main.c -mcpu=cortex-m4 -mthumb -g - -main.elf: main.c - arm-unknown-eabi-gcc $(OPT) main.c -mcpu=cortex-m4 -mthumb -g -lgcc -T linker_script.ld -Xlinker --cref -Xlinker -Map -Xlinker main.map -nostartfiles -o main.elf - -main.bin: main.elf - arm-unknown-eabi-objcopy -O binary main.elf main.bin - -flash: main.bin - st-flash write main.bin 0x8000000 - -clean: - rm -f *.elf *.bin diff --git a/00-hello/README b/00-hello/README deleted file mode 100644 index b9d0788..0000000 --- a/00-hello/README +++ /dev/null @@ -1,19 +0,0 @@ -Welcome to Level 1 ------------------- - -This is a VERY simple program for the STM32L432 Nucleo-32 board. It simply -iterates turning on the status led (LD3) and the pin D6. - -There is NO clock setting or anything, everything is the default bootup. - -There is a single source file, main.c, which defines all the code needed. - -There is a linker script which sets up the binary format properly ready to -be flashed. - -This code can be flashed with - - $ make flash - -this requires the program `st-flash` which is a part of the stlink programmer, -which can be found at https://github.com/texane/stlink.git. diff --git a/00-hello/linker_script.ld b/00-hello/linker_script.ld deleted file mode 100644 index fe0c14b..0000000 --- a/00-hello/linker_script.ld +++ /dev/null @@ -1,14 +0,0 @@ -MEMORY -{ - flash : org = 0x08000000, len = 256k -} - -SECTIONS -{ - /* This is where the code goes. */ - . = ORIGIN(flash); - .text : { - *(.vectors); /* All .vector sections go here. */ - *(.text); /* All .text sections go here. */ - } >flash -} diff --git a/00-hello/main.c b/00-hello/main.c deleted file mode 100644 index fe2b9d5..0000000 --- a/00-hello/main.c +++ /dev/null @@ -1,354 +0,0 @@ -#define __IO volatile - -#include -#define RCC_BASE_2 0x40021000 - -int main(); -void spin(); - -/* - * Interrupt service routine handlers. - */ -const void* vectors[] __attribute__((section(".vectors"))) = { - (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ - main, /* Reset handler */ - spin, /* NMI */ - spin, /* Hard Fault */ - spin, /* MemManage */ - spin, /* BusFault */ - spin, /* UsageFault */ - spin, /* Reserved */ - spin, /* Reserved */ - spin, /* Reserved */ - spin, /* Reserved */ - spin, /* SVCall */ - spin, /* Debug */ - spin, /* Reserved */ - spin, /* PendSV */ - spin, /* SysTick */ - - /* External interrupt handlers follow */ - spin, /* 0 WWDG */ - spin, /* 1 PVD */ - spin, /* 2 TAMP_SAMP */ - spin, /* 3 RTC_WKUP */ - spin, /* 4 FLASH */ - spin, /* 5 RCC */ - spin, /* 6 EXTI0 */ - spin, /* 7 EXTI1 */ - spin, /* 8 EXTI2 */ - spin, /* 9 EXTI3 */ - spin, /* 10 EXTI4 */ - spin, /* 11 DMA_CH1 */ - spin, /* 12 DMA_CH2 */ - spin, /* 13 DMA_CH3 */ - spin, /* 14 DMA_CH4 */ - spin, /* 15 DMA_CH5 */ - spin, /* 16 DMA_CH6 */ - spin, /* 17 DMA_CH7 */ - spin, /* 18 ADC1 */ - spin, /* 19 CAN_TX */ - spin, /* 20 CAN_RX0 */ - spin, /* 21 CAN_RX1 */ - spin, /* 22 CAN_SCE */ - spin, /* 23 EXTI9_5 */ - spin, /* 24 TIM1_BRK/TIM15 */ - spin, /* 25 TIM1_UP/TIM16 */ - spin, /* 26 TIM1_TRG_COM */ - spin, /* 27 TIM1_CC */ - spin, /* 28 TIM2 */ - spin, /* 29 Reserved */ - spin, /* 30 Reserved */ - spin, /* 31 I2C1_EV */ - spin, /* 32 I2C1_ER */ - spin, /* 33 I2C2_EV */ - spin, /* 34 I2C2_ER */ - spin, /* 35 SPI1 */ - spin, /* 36 SPI2 */ - spin, /* 37 USART1 */ - spin, /* 38 USART2 */ - spin, /* 39 USART3 */ - spin, /* 40 EXTI15_10 */ - spin, /* 41 RTCAlarm */ - spin, /* 42 Reserved */ - spin, /* 43 Reserved */ - spin, /* 44 Reserved */ - spin, /* 45 Reserved */ - spin, /* 46 Reserved */ - spin, /* 47 Reserved */ - spin, /* 48 Reserved */ - spin, /* 49 SDMMC1 */ - spin, /* 50 Reserved */ - spin, /* 51 SPI3 */ - spin, /* 52 Reserved */ - spin, /* 53 Reserved */ - spin, /* 54 TIM6_DACUNDER */ - spin, /* 55 TIM7 */ - spin, /* 56 DMA2_CH1 */ - spin, /* 57 DMA2_CH2 */ - spin, /* 58 DMA2_CH3 */ - spin, /* 59 DMA2_CH4 */ - spin, /* 60 DMA2_CH5 */ - spin, /* 61 Reserved */ - spin, /* 62 Reserved */ - spin, /* 63 Reserved*/ - spin, /* 64 COMP */ - spin, /* 65 LPTIM1 */ - spin, /* 66 LPTIM2 */ - spin, /* 67 USB_FS */ - spin, /* 68 DMA_CH6 */ - spin, /* 69 DMA_CH7 */ - spin, /* 70 LPUART1 */ - spin, /* 71 QUADSPI */ - spin, /* 72 I2C3_EV */ - spin, /* 73 I2C3_ER */ - spin, /* 74 SAI1 */ - spin, /* 75 Reserved */ - spin, /* 76 SWPMI1 */ - spin, /* 77 TSC */ - spin, /* 78 Reserved */ - spin, /* 79 AES */ - spin, /* 80 RNG */ - spin, /* 81 FPU */ - spin /* 82 CRS */ -}; - -typedef struct { - __IO uint32_t value; -} rcc_reg_t; - -#define RCC_AHB2ENR (*((__IO rcc_reg_t*)(RCC_BASE_2 + 0x4c))) - -typedef enum { - GPIO_PORT_A = 0, - GPIO_PORT_B = 1, - GPIO_PORT_C = 2, - GPIO_PORT_D = 3 -} gpio_port_number_t; - -void enable_gpio(gpio_port_number_t port) -{ - RCC_AHB2ENR.value |= 1 << port; -} - -typedef enum { - PIN_0 = 0, - PIN_1 = 1, - PIN_2 = 2, - PIN_3 = 3, - PIN_4 = 4, - PIN_5 = 5, - PIN_6 = 6, - PIN_7 = 7, - PIN_8 = 8, - PIN_9 = 9, - PIN_10 = 10, - PIN_11 = 11, - PIN_12 = 12, - PIN_13 = 13, - PIN_14 = 14, - PIN_15 = 15 -} pin_t; - -typedef enum { - MODE_INPUT = 0, - MODE_OUTPUT = 1, - MODE_ALTERNATE = 2, - MODE_ANALOG = 3 -} pin_mode_t; - -/* GPIO port speed. */ -typedef enum { - SPEED_2MHZ = 0, - SPEED_10MHZ = 1, - SPEED_50MHZ = 3, -} speed_t; - -/* - * Mode register. Input, output, alternate functiont or analog. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) mode_reg_t; - -/* - * Type register. Push/pull or open drain. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) type_reg_t; - -/* - * Speed register. Allows low, meduim, fast or high speed. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) speed_reg_t; - -/* - * Pull up/pull down register. Allows pull up, pull down, or no pull up or - * pull down. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) pull_reg_t; - -/* - * Stores the data for reading from the outside. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) input_data_reg_t; - -/* - * Stores the data for writing to the outside. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) output_data_reg_t; - -/* - * Writing a 1 to a bit in this register allows the user to set or reset a bit - * in the output data register. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) bit_set_reset_reg_t; - -/* - * Lock register. Allows the user to lock a pin so that its value cannot be - * changed. - */ -typedef struct { - __IO uint32_t value; -} __attribute__((packed)) lock_reg_t; - -/* - * Alternate function. - */ -typedef struct { - __IO uint32_t value_high; - __IO uint32_t value_low; -} __attribute__((packed)) alt_function_reg_t; - -/* Structure defining the layout of a GPIO port on the STM32L432. */ -typedef struct { - __IO mode_reg_t mode; /* Mode register */ - __IO pull_reg_t pupd; /* Pull up/pull down/none register */ - __IO speed_reg_t speed; /* Speed register */ - __IO type_reg_t type; /* Type register */ - __IO input_data_reg_t input; /* Input data register */ - __IO output_data_reg_t output; /* Output data register */ - __IO bit_set_reset_reg_t bsr; /* Bit set/reset register */ - __IO lock_reg_t lock; /* Lock register */ - __IO alt_function_reg_t altfn; /* Alternate function registers */ -} __attribute__((packed)) gpio_port_t; - -/* - * Defines for GPIO memory mapped addresses. - */ -#define GPIO_A (*((__IO gpio_port_t*)0x48000000)) -#define GPIO_B (*((__IO gpio_port_t*)0x48000400)) -#define GPIO_C (*((__IO gpio_port_t*)0x48000800)) - -/* - * Delays for `delay` iterations. - */ -void delay(uint32_t delay) -{ - while (delay--) { - // Empty volatile assembly to keep the optimizer from getting - // rid of this loop entirely. - asm volatile(""); - } -} - -/* - * Sets the mode of a pin on a gpio port. - * - * gpio_port: the gpio port. - * pin: the number of the port; - * pin_mode: the mode of the pin. See pin_mode_t enum. - */ -void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, uint32_t pin, pin_mode_t pin_mode) -{ - gpio_port->mode.value &= ~(0x03 << pin * 2); - gpio_port->mode.value |= pin_mode << pin * 2; -} - -/* - * Sets the value on an output GPIO pin. - * - * gpio_port: The gpio port. - * pin: the number of the pin to enable. Values 0-15 - * val: 0 to set the gpio pin to low, non-zero to set to high. - */ -void set_gpio_pin(__IO gpio_port_t* gpio_port, uint32_t pin, int val) -{ - if (val) { - gpio_port->output.value |= 1 << pin; - } else { - gpio_port->output.value &= ~(1 << pin); - } -} - -/* Main function. This gets executed from the interrupt vector defined above. */ -int main() -{ - /* Enable the GPIO port B. */ - enable_gpio(GPIO_PORT_B); - - /* Set pin 3 and pin 1 of GPIO_B to be an output pin. */ - set_gpio_pin_mode(&GPIO_B, /* pin = */ 3, MODE_OUTPUT); - set_gpio_pin_mode(&GPIO_B, /* pin = */ 1, MODE_OUTPUT); - - while (1) { - /* Set the GPIO pin to high. */ - set_gpio_pin(&GPIO_B, /* pin = */ 3, 1); - set_gpio_pin(&GPIO_B, /* pin = */ 1, 0); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - - /* Set the GPIO pin to low. */ - set_gpio_pin(&GPIO_B, /* pin = */ 3, 0); - set_gpio_pin(&GPIO_B, /* pin = */ 1, 1); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - delay(65535); - } -} - -/* - * Does nothing ... forever. - */ -void spin() -{ - for (;;) { - /* Flash in a distinct pattern to know that something went wrong. */ - - set_gpio_pin(&GPIO_B, /* pin = */ 3, 0); - delay(100000); - set_gpio_pin(&GPIO_B, /* pin = */ 3, 1); - delay(100000); - set_gpio_pin(&GPIO_B, /* pin = */ 3, 0); - delay(100000); - set_gpio_pin(&GPIO_B, /* pin = */ 3, 1); - delay(500000); - } -} diff --git a/01-system-clock/Makefile.preamble b/01-system-clock/Makefile.preamble deleted file mode 100644 index 3c8a61b..0000000 --- a/01-system-clock/Makefile.preamble +++ /dev/null @@ -1,21 +0,0 @@ -OPT?=-O -PREFIX?=arm-unknown-eabi- -CC=$(PREFIX)gcc -LD=$(PREFIX)ld -CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude -LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static - - -all: _$(PREFIX)_obs/main.elf - -_$(PREFIX)_obs/main.bin: _$(PREFIX)_obs/main.elf - $(PREFIX)objcopy -O binary _$(PREFIX)_obs/main.elf _$(PREFIX)_obs/main.bin - -flash: _$(PREFIX)_obs/main.bin - st-flash write _$(PREFIX)_obs/main.bin 0x8000000 - -clean: - rm -rf _*_obs - -genmake: - ./genmake.pl > Makefile diff --git a/01-system-clock/README b/01-system-clock/README deleted file mode 100644 index fb9b5df..0000000 --- a/01-system-clock/README +++ /dev/null @@ -1,17 +0,0 @@ -This is much more complex than the simple hello script, but most is boiler plate -designed to make future debugging easier. The first addition is a genmake -system where a Makefile may be generated with the command -`./genmake.pl > Makefile` and subsequently with `make genmake`. This will add -build rules for each `c` file. - -There are some added features as well: - -* This code loads values properly from the data and bss segments into memory so - global variables and global constants may be used. - -* This code can properly set the system clock, and does get a full 80MHz out - of it. - -* This code has a `spin()` function that flashes a "morse code" translation - of a binary error code. (1's are dashes, 0's are dots). Gives minimal feedback - until such a time where USART is implemented. diff --git a/01-system-clock/genmake.pl b/01-system-clock/genmake.pl deleted file mode 100755 index 341db3d..0000000 --- a/01-system-clock/genmake.pl +++ /dev/null @@ -1,70 +0,0 @@ -#!/usr/bin/perl - -# This script is designed to introspect C files and generate a makefile to use. - -sub header_deps { - my $file = @_[0]; - my @headers; - - if (open(my $fh, '<:encoding(UTF-8)', $file)) { - print STDERR "\x1b[35m[Trace] - Reading file $file\x1b[00m\n"; - push(@headers, $file); - - while (<$fh>) { - /#include\s+"(.*)"\s*$/ && push(@headers, header_deps("include/$1")); - } - } - - return @headers; -} - -my @files = glob('src/*.c'); -my @obj_files; - -open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble") - or die "Missing Makefile.preamble"; - -while (<$fh>) { - print "$_"; -} - -# Emit a rule that will rerun genmake if the c files do not match. -my $idempotency_cmd = - "ls src/*.c include/*.h| sha1sum | awk '{print \$1}'"; - -my $idempotency_cmd_make = - "ls src/*.c include/*.h | sha1sum | awk '{print \$\$1}'"; - -print "IDEMPOTENCY_HASH=" . `$idempotency_cmd` . "\n"; - -my $arch_obs_dir = "_\$(PREFIX)_obs"; -print "CHEAT_PRE_MAKE := \$(shell mkdir -p $arch_obs_dir)\n"; - -foreach $file (@files) { - my $c_file = $file; - (my $file_no_ext = $file) =~ s/src\/(.*)\.c$/\1/g; - - my $obj_file = "$arch_obs_dir/${file_no_ext}.o"; - my $s_file = "${file_no_ext}.s"; - - push(@obj_files, $obj_file); - my @deps = header_deps($c_file); - - my $deps_as_join = join(" ", @deps); - - # Emit the rule to make the object file. - print "$obj_file: $deps_as_join\n\t"; - print '$(CC) -c ' . $c_file . ' -o ' . $obj_file . ' $(CFLAGS)' . "\n\n"; - - # Emit the rule to make the assembly file. - print "$s_file: $deps_as_join\n\t"; - print '$(CC) -S ' . $c_file . ' -o ' . $s_file . ' $(CFLAGS)' . "\n\n"; -} - -my $obj_files_deps = join(' ', @obj_files); -print "FORCE:\n\t\n\n"; -print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t"; -print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] " - . "&& ./genmake.pl > Makefile && make main.elf ) " - . "|| " - . "\$(LD) -o $arch_obs_dir/main.elf \$(LD_FLAGS) $obj_files_deps\n\n"; diff --git a/01-system-clock/include/clock.h b/01-system-clock/include/clock.h deleted file mode 100644 index de4fb96..0000000 --- a/01-system-clock/include/clock.h +++ /dev/null @@ -1,118 +0,0 @@ -#ifndef CLOCK_H__ -#define CLOCK_H__ - -#include -#include "rcc.h" - -#define PERIPH_BASE ((uint32_t)0x40000000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) -#define PWR_BASE (PERIPH_BASE + 0x7000) -#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ - -#ifndef __IO -#define __IO volatile -#endif - -typedef struct { - __IO uint32_t cr; - __IO uint32_t csr; -} pwr_t; - -// typedef struct { -// __IO uint32_t acr; -// __IO uint32_t pecr; -// __IO uint32_t pdkeyr; -// __IO uint32_t pekeyr; -// __IO uint32_t prgkeyr; -// __IO uint32_t optkeyr; -// __IO uint32_t sr; -// __IO uint32_t obr; -// __IO uint32_t wrpr; -// } flash_t; - -// #define FLASH (*(flash_t*) (FLASH_R_BASE)) -#define PWR (*(pwr_t*)(PWR_BASE)) - -/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */ -typedef enum { - PLL_DIVISOR_2 = 1, - PLL_DIVISOR_4 = 3, - PLL_DIVISOR_6 = 5, - PLL_DIVISOR_8 = 7, - PLL_DIVISOR_OFF = 0, -} pll_divisor_t; - -/* Valid values for the PLLP bits off the PLLCFG register. */ -typedef enum { - PLLP_DIVISOR_7 = 1, - PLLP_DIVISOR_17 = 3, - PLLP_DIVISOR_OFF = 0, -} pllp_divisor_t; - -/* Valid values for the PLLM bits of the PLLCFG register. */ -typedef enum { - PLLM_DIVISOR_1 = 0, - PLLM_DIVISOR_2 = 1, - PLLM_DIVISOR_3 = 2, - PLLM_DIVISOR_4 = 3, - PLLM_DIVISOR_5 = 4, - PLLM_DIVISOR_6 = 5, - PLLM_DIVISOR_7 = 6, - PLLM_DIVISOR_8 = 7, -} pllm_divisor_t; - -/* Possible sources for the input clock. */ -typedef enum { - PLL_SRC_NONE = 0, - PLL_SRC_MSI = 1, - PLL_SRC_HSI = 2, - PLL_SRC_HSE = 3, -} pll_src_t; - -/* Valid sources for the system clock. */ -typedef enum { - SYSTEM_CLOCK_SRC_MSI = 0, - SYSTEM_CLOCK_SRC_HSI = 1, - SYSTEM_CLOCK_SRC_HSE = 2, - SYSTEM_CLOCK_SRC_PLL = 3, -} system_clock_src_t; - -#define E_BADPLLN (-2) -#define E_BADPLLP_DIV (-1) -#define E_TIMEOUT (-3) -#define E_NOT_OFF (-4) -#define E_BAD_ARG (-5) - -/* - * Sets the system clock to a full 80Mhz. - */ -int set_system_clock_MHz(uint8_t mhz); - -/* - * Set the PLL on. - */ -int pll_on(); - -/* - * Set the PLL off. - */ -int pll_off(); - -/* - * Sets the source of the system clock. - */ -int set_system_clock_src(system_clock_src_t src); - -/* - * Configure the PLL. - */ -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */); - -#endif /* CLOCK_H__ */ diff --git a/01-system-clock/include/common.h b/01-system-clock/include/common.h deleted file mode 100644 index 6fc701c..0000000 --- a/01-system-clock/include/common.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef COMMON__H -#define COMMON__H - -/* Define __IO to be volatile if it's not already. */ -#ifndef __IO -#define __IO volatile -#endif - -#define bool int - -#define PACKED __attribute__((packed)) -#define BIT(n) (1 << (n)) - -#endif /* COMMON_H */ diff --git a/01-system-clock/include/delay.h b/01-system-clock/include/delay.h deleted file mode 100644 index 65a26d6..0000000 --- a/01-system-clock/include/delay.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef H__DELAY__ -#define H__DELAY__ - -#include - -/* - * Loops and count-downs the delay, the time this takes depends on the speed - * of the clock. - */ -void delay(uint32_t delay); - -#endif /* H__DELAY__ */ diff --git a/01-system-clock/include/flash.h b/01-system-clock/include/flash.h deleted file mode 100644 index a163a25..0000000 --- a/01-system-clock/include/flash.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef H__FLASH_ -#define H__FLASH_ - -#include "common.h" - -/* - * Header file for dealing with flash. - */ - -#define FLASH_BASE 0x40022000 - -typedef struct { - __IO uint32_t ac_r; /* Flash access control register. */ - - /* TODO fill out the rest. */ -} PACKED flash_t; - -#define FLASH (*(__IO flash_t*)FLASH_BASE) - -#endif /* H__FLASH_ */ diff --git a/01-system-clock/include/gpio.h b/01-system-clock/include/gpio.h deleted file mode 100644 index a8f06e2..0000000 --- a/01-system-clock/include/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -#ifndef GPIO_H__ -#define GPIO_H__ - -#include "common.h" - -#include - -/* - * Possible GPIO ports. - */ -typedef enum { - GPIO_PORT_A = 0, - GPIO_PORT_B = 1, - GPIO_PORT_C = 2, - GPIO_PORT_D = 3 -} gpio_port_number_t; - -/* - * Structure defining the layout of the layout of the GPIO registers on the - * stm32l432 development board. - */ -typedef struct GPIO_PORT_STR { - __IO uint32_t mode_r; /* Mode register */ - __IO uint32_t pupd_r; /* Pull up/pull down/none register */ - __IO uint32_t speed_r; /* Speed register */ - __IO uint32_t type_r; /* Type register */ - __IO uint32_t input_r; /* Input data register */ - __IO uint32_t output_r; /* Output data register */ - __IO uint32_t bsr_r; /* Bit set/reset register */ - __IO uint32_t lock_r; /* Lock register */ - __IO uint32_t altfn_r; /* Alternate function register */ -} PACKED gpio_port_t; - -/* - * Enum defining the PINs in a GPIO port. Each port has 16 pins to use in - * the stm32l432. - */ -typedef enum GPIO_PIN_ENUM { - PIN_0 = 0, - PIN_1 = 1, - PIN_2 = 2, - PIN_3 = 3, - PIN_4 = 4, - PIN_5 = 5, - PIN_6 = 6, - PIN_7 = 7, - PIN_8 = 8, - PIN_9 = 9, - PIN_10 = 10, - PIN_11 = 11, - PIN_12 = 12, - PIN_13 = 13, - PIN_14 = 14, - PIN_15 = 15 -} gpio_pin_t; - -/* - * Enum defining the pin modes that are possible. - */ -typedef enum { - MODE_INPUT = 0, - MODE_OUTPUT = 1, - MODE_ALTERNATE = 2, - MODE_ANALOG = 3 -} gpio_pin_mode_t; - -/* - * Enum defining the pin speeds that are possible. - */ -typedef enum { - SPEED_2MHZ = 0, - SPEED_10MHZ = 1, - SPEED_50MHZ = 3, -} speed_t; - -/* - * Structure defining an OUTPUT pin. Structurally equivalent to the input pin, - * but can be used in a slightly type-safe manner. - */ -typedef struct { - __IO gpio_port_t* gpio_port; - gpio_pin_t pin; -} gpio_output_pin_t; - -/* - * Sets the mode on a GPIO pin. - * - * gpio_port: the gpio port to use. - * pin: the pin number to set. - * pin_mode: the mode to set the pin to. - */ -void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode); - -/* - * Sets the given GPIO pin to be an output pin. Returns an output_pin struct - * corresponding to - */ -gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, gpio_pin_t pin); - -/* - * Sets an output pin on or off. - * - * pin: the pin to toggle. - * onoff: 0 for off, non-zero of on. - */ -void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff); - -#define pin_on(p) set_gpio_output_pin(p, 1) - -#define pin_off(p) set_gpio_output_pin(p, 0) - -/* - * Enables a GPIO port and returns a reference to the register definition - * of that GPIO port. - */ -__IO gpio_port_t* enable_gpio(gpio_port_number_t number); - -#endif /* GPIO_H__ */ diff --git a/01-system-clock/include/isr_vector.h b/01-system-clock/include/isr_vector.h deleted file mode 100644 index 3e55f52..0000000 --- a/01-system-clock/include/isr_vector.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef h__ISR_VECTOR_H__ -#define h__ISR_VECTOR_H__ - -/* - * Include file for interrupt service routines. - */ - -/* - * The interrupt service routines. These link in the function `main` as the - * main function. - */ -extern const void* isr_vector[]; - -/* - * Defines an error state. This loops forever and defines a distinct flashing - * pattern to let the user know an unhandled ISR happened. - */ -void unhandled_isr(); - -#endif /* h___ISR_VECTOR_H__ */ diff --git a/01-system-clock/include/rcc.h b/01-system-clock/include/rcc.h deleted file mode 100644 index 4eeb26b..0000000 --- a/01-system-clock/include/rcc.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef H__RCC_ -#define H__RCC_ - -#include "common.h" - -#define RCC_BASE ((uint32_t)0x40021000) - -typedef struct { - __IO uint32_t c_r; /* Clock control register. 0x00 */ - __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ - __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ - __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ - __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ - - __IO uint32_t reserved_1; /* Not used. offset 0x14. */ - - __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ - __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ - __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ - - __IO uint32_t reserved_2; /* Not used. offset 0x24. */ - - __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ - __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ - __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ - - __IO uint32_t reserved_3; /* Not used. offset 0x34. */ - - __IO uint32_t abp1rst1_r; /* APB Peripheral reset register 1. 0x38 */ - __IO uint32_t abp1rst2_r; /* APB Peripheral reset register 2. 0x3C */ - __IO uint32_t abp2rst_r; /* APB Peripheral reset register. 0x40 */ - - __IO uint32_t reserved_4; /* Not used. offset 0x44. */ - - __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ - __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ - __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ - - __IO uint32_t reserved_5; /* Not used. offset 0x54. */ - - __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ - __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ - __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ - - __IO uint32_t reserved_6; /* Not used. offset 0x64. */ - - /* TODO add the rest starting at offset 0x68. */ - -} PACKED rcc_t; - -#define RCC (*(__IO rcc_t*)RCC_BASE) - -/* Macros to operate on the RCC registers. */ - -/* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hse(rcc, e) \ - do { \ - if (e) { \ - (rcc).c_r |= 1 << 16; \ - } else { \ - (rcc).c_r &= ~(1 << 16); \ - } \ - } while (0) - -/* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hsi(rcc, e) \ - do { \ - if (e) { \ - (rcc).c_r |= 1 << 8; \ - } else { \ - (rcc).c_r &= ~(1 << 8); \ - } \ - } while (0) - -/* Checks to see if the hse is ready. */ -#define hse_ready(rcc) ((rcc).c_r & (1 << 17)) - -/* Checks to see if the hse is ready. */ -#define hsi_ready(rcc) ((rcc).c_r & (1 << 10)) - -#endif diff --git a/01-system-clock/include/spin.h b/01-system-clock/include/spin.h deleted file mode 100644 index a23d25b..0000000 --- a/01-system-clock/include/spin.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef H__SPIN_ -#define H__SPIN_ - -#include - -/* - * Flash a code on the status LED. - * - * The flash codes a binary from MSB to LSB. A long flash is a 1, a short flash - * is a 0. Each independent flashing is succeced by a break of 4 times that - * of a long flash. - */ -void spin(uint32_t base_delay, uint8_t code); - -#endif /* H__SPIN_ */ diff --git a/01-system-clock/linker/linker_script.ld b/01-system-clock/linker/linker_script.ld deleted file mode 100644 index 348d03b..0000000 --- a/01-system-clock/linker/linker_script.ld +++ /dev/null @@ -1,36 +0,0 @@ -MEMORY -{ - flash : org = 0x08000000, len = 256k - sram1 : org = 0x20000000, len = 48k - sram2 : org = 0x10000000, len = 16k -} - -SECTIONS -{ - /* This is where the code goes. */ - . = ORIGIN(flash); - .text : { - *(.vectors); /* All .vector sections go here. */ - *(.text); /* All .text sections go here. */ - } >flash - - .data : { - /* Data segment as defined in the flash. */ - INIT_DATA_VALUES = LOADADDR(.data); - - /* Data segment where it will be in memory. */ - DATA_SEGMENT_START = .; - *(.data); - DATA_SEGMENT_STOP = .; - - /* Align by 4 so we can optimize the copier to use uint32's. */ - . = ALIGN(0x04); - } >sram1 AT>flash - - BSS_START = .; - .bss : { - *(.bss); - . = ALIGN(0x04); - } > sram1 - BSS_END = .; -} diff --git a/01-system-clock/src/clock.c b/01-system-clock/src/clock.c deleted file mode 100644 index 75bac97..0000000 --- a/01-system-clock/src/clock.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file sets the system clock to its full glory of 80Mhz - */ - -#include "clock.h" -#include -#include "flash.h" -#include "gpio.h" -#include "spin.h" - -#define TIMEOUT 10000 - -int pll_off() -{ - uint32_t c; - - RCC.c_r &= ~BIT(24); /* Turn off pll. */ - for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c) - ; /* Wait for OFF. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int pll_on() -{ - uint32_t c; - - RCC.c_r |= BIT(24); /* Turn on PLL. */ - for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c) - ; /* Wait for RDY. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */) -{ - if (RCC.c_r & BIT(25)) { - /* PLL must be off to configure it. */ - return E_NOT_OFF; - } - - /* Make sure inputs are valid. */ - if (pllp_div_factor == 1 || pllp_div_factor > 31) { - return E_BADPLLP_DIV; - } - if (plln < 8 || plln > 86) { - return E_BADPLLN; - } - - RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | - (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); - - return 0; -} - -int set_system_clock_MHz(uint8_t mhz) -{ - /* Set the source of the system colck to MSI temporarily. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_MSI); - - if (mhz <= 8 || mhz > 80) { - return E_BAD_ARG; - } - - pll_off(); - - configure_pll( - 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, - PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, - - /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. - */ - mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, - PLL_SRC_MSI /* pll src | 04 Mhz */); - - pll_on(); - - /* Configure the flash to have 4 wait states. This is required at - * 80 MHz. */ - FLASH.ac_r &= ~0x07; - FLASH.ac_r |= 0x04; - - /* Set the source of the system colck to PLL. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_PLL); - return 0; -} - -int set_system_clock_src(system_clock_src_t src) -{ - uint8_t value = RCC.cfg_r & ~0x03; - RCC.cfg_r = value | src; -} diff --git a/01-system-clock/src/delay.c b/01-system-clock/src/delay.c deleted file mode 100644 index 2a16d47..0000000 --- a/01-system-clock/src/delay.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "delay.h" - -void delay(uint32_t delay) -{ - while (delay--) { - /* needed to keep the compiler from optimizing away the loop. */ - asm volatile(""); - } -} diff --git a/01-system-clock/src/gpio.c b/01-system-clock/src/gpio.c deleted file mode 100644 index 2404398..0000000 --- a/01-system-clock/src/gpio.c +++ /dev/null @@ -1,37 +0,0 @@ -#include "gpio.h" -#include "rcc.h" - -/* - * Sets the mode of a pin on a gpio por. - */ -void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode) -{ - /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */ - gpio_port->mode_r &= ~(0x03 << pin * 2); - gpio_port->mode_r |= mode << pin * 2; -} - -gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, gpio_pin_t pin) -{ - set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT); - - return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin}; -} - -void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff) -{ - if (onoff) { - pin.gpio_port->output_r |= 1 << pin.pin; - } else { - pin.gpio_port->output_r &= ~(1 << pin.pin); - } -} - -#define GPIO_PORTS_BASE_ADDR ((uint32_t)0x48000000) -__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) -{ - RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ - return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); -} diff --git a/01-system-clock/src/isr_vector.c b/01-system-clock/src/isr_vector.c deleted file mode 100644 index 674a6bb..0000000 --- a/01-system-clock/src/isr_vector.c +++ /dev/null @@ -1,165 +0,0 @@ -#include "isr_vector.h" -#include "delay.h" -#include "gpio.h" - -/* Forward-declare the main function. This is implemented in main.c. */ -void main(); - -/* These are defined in the linker script. */ -extern uint32_t INIT_DATA_VALUES; -extern uint32_t DATA_SEGMENT_START; -extern uint32_t DATA_SEGMENT_STOP; -extern uint32_t BSS_START; -extern uint32_t BSS_END; - -/* - * Runs before main. Initializes the data and bss segments by loading them - * into memory. - */ -void init() -{ - uint32_t* src; - uint32_t* dest; - - src = &INIT_DATA_VALUES; - dest = &DATA_SEGMENT_START; - - /* Copy the values from flash into the data segment. */ - while (dest != &DATA_SEGMENT_STOP) { - *(dest++) = *(src++); - } - - /* Everything in the BSS segment is set to zero. */ - dest = &BSS_START; - while (dest != &BSS_END) { - *(dest++) = 0; - } - - /* Jump to main. */ - main(); -} - -const void* vectors[] __attribute__((section(".vectors"))) = { - (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ - init, /* Reset handler */ - unhandled_isr, /* NMI */ - unhandled_isr, /* Hard Fault */ - unhandled_isr, /* MemManage */ - unhandled_isr, /* BusFault */ - unhandled_isr, /* UsageFault */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* SVCall */ - unhandled_isr, /* Debug */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* PendSV */ - unhandled_isr, /* SysTick */ - - /* External interrupt handlers follow */ - unhandled_isr, /* 0 WWDG */ - unhandled_isr, /* 1 PVD */ - unhandled_isr, /* 2 TAMP_SAMP */ - unhandled_isr, /* 3 RTC_WKUP */ - unhandled_isr, /* 4 FLASH */ - unhandled_isr, /* 5 RCC */ - unhandled_isr, /* 6 EXTI0 */ - unhandled_isr, /* 7 EXTI1 */ - unhandled_isr, /* 8 EXTI2 */ - unhandled_isr, /* 9 EXTI3 */ - unhandled_isr, /* 10 EXTI4 */ - unhandled_isr, /* 11 DMA_CH1 */ - unhandled_isr, /* 12 DMA_CH2 */ - unhandled_isr, /* 13 DMA_CH3 */ - unhandled_isr, /* 14 DMA_CH4 */ - unhandled_isr, /* 15 DMA_CH5 */ - unhandled_isr, /* 16 DMA_CH6 */ - unhandled_isr, /* 17 DMA_CH7 */ - unhandled_isr, /* 18 ADC1 */ - unhandled_isr, /* 19 CAN_TX */ - unhandled_isr, /* 20 CAN_RX0 */ - unhandled_isr, /* 21 CAN_RX1 */ - unhandled_isr, /* 22 CAN_SCE */ - unhandled_isr, /* 23 EXTI9_5 */ - unhandled_isr, /* 24 TIM1_BRK/TIM15 */ - unhandled_isr, /* 25 TIM1_UP/TIM16 */ - unhandled_isr, /* 26 TIM1_TRG_COM */ - unhandled_isr, /* 27 TIM1_CC */ - unhandled_isr, /* 28 TIM2 */ - unhandled_isr, /* 29 Reserved */ - unhandled_isr, /* 30 Reserved */ - unhandled_isr, /* 31 I2C1_EV */ - unhandled_isr, /* 32 I2C1_ER */ - unhandled_isr, /* 33 I2C2_EV */ - unhandled_isr, /* 34 I2C2_ER */ - unhandled_isr, /* 35 SPI1 */ - unhandled_isr, /* 36 SPI2 */ - unhandled_isr, /* 37 USART1 */ - unhandled_isr, /* 38 USART2 */ - unhandled_isr, /* 39 USART3 */ - unhandled_isr, /* 40 EXTI15_10 */ - unhandled_isr, /* 41 RTCAlarm */ - unhandled_isr, /* 42 Reserved */ - unhandled_isr, /* 43 Reserved */ - unhandled_isr, /* 44 Reserved */ - unhandled_isr, /* 45 Reserved */ - unhandled_isr, /* 46 Reserved */ - unhandled_isr, /* 47 Reserved */ - unhandled_isr, /* 48 Reserved */ - unhandled_isr, /* 49 SDMMC1 */ - unhandled_isr, /* 50 Reserved */ - unhandled_isr, /* 51 SPI3 */ - unhandled_isr, /* 52 Reserved */ - unhandled_isr, /* 53 Reserved */ - unhandled_isr, /* 54 TIM6_DACUNDER */ - unhandled_isr, /* 55 TIM7 */ - unhandled_isr, /* 56 DMA2_CH1 */ - unhandled_isr, /* 57 DMA2_CH2 */ - unhandled_isr, /* 58 DMA2_CH3 */ - unhandled_isr, /* 59 DMA2_CH4 */ - unhandled_isr, /* 60 DMA2_CH5 */ - unhandled_isr, /* 61 Reserved */ - unhandled_isr, /* 62 Reserved */ - unhandled_isr, /* 63 Reserved*/ - unhandled_isr, /* 64 COMP */ - unhandled_isr, /* 65 LPTIM1 */ - unhandled_isr, /* 66 LPTIM2 */ - unhandled_isr, /* 67 USB_FS */ - unhandled_isr, /* 68 DMA_CH6 */ - unhandled_isr, /* 69 DMA_CH7 */ - unhandled_isr, /* 70 LPUART1 */ - unhandled_isr, /* 71 QUADSPI */ - unhandled_isr, /* 72 I2C3_EV */ - unhandled_isr, /* 73 I2C3_ER */ - unhandled_isr, /* 74 SAI1 */ - unhandled_isr, /* 75 Reserved */ - unhandled_isr, /* 76 SWPMI1 */ - unhandled_isr, /* 77 TSC */ - unhandled_isr, /* 78 Reserved */ - unhandled_isr, /* 79 AES */ - unhandled_isr, /* 80 RNG */ - unhandled_isr, /* 81 FPU */ - unhandled_isr /* 82 CRS */ -}; - -/* - * Does nothing ... forever. - */ -void unhandled_isr() -{ - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - for (;;) { - /* Flash in a distinct pattern to know that something went wrong. */ - - pin_off(pin3); - delay(100000); - pin_on(pin3); - delay(100000); - pin_off(pin3); - delay(100000); - pin_on(pin3); - delay(500000); - } -} diff --git a/01-system-clock/src/main.c b/01-system-clock/src/main.c deleted file mode 100644 index 7912bf2..0000000 --- a/01-system-clock/src/main.c +++ /dev/null @@ -1,36 +0,0 @@ -#include "clock.h" -#include "delay.h" -#include "gpio.h" -#include "spin.h" - -volatile uint32_t delay_amt = 20000000 / 4; - -/* Main function. This gets executed from the interrupt vector defined above. */ -int main() -{ - /* Enable the GPIO port B. */ - - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - gpio_output_pin_t pin1 = set_gpio_pin_output(port_b, PIN_1); - - /* Enable a higher clock frequency. */ - set_system_clock_MHz(80); - - uint32_t count = 0; - while (1) { - /* Set the GPIO pin to high. */ - pin_off(pin1); - pin_off(pin3); - delay(delay_amt); - - /* Set the GPIO pin to low. */ - if (count % 4 == 0) { - pin_on(pin1); - } - pin_on(pin3); - delay(delay_amt); - - ++count; - } -} diff --git a/01-system-clock/src/spin.c b/01-system-clock/src/spin.c deleted file mode 100644 index fbd16b6..0000000 --- a/01-system-clock/src/spin.c +++ /dev/null @@ -1,49 +0,0 @@ -#include "spin.h" -#include "delay.h" -#include "gpio.h" - -#define SHORT_DELAY 200000 -#define LONG_DELAY (SHORT_DELAY * 2) - -static void flash_bit( - uint32_t base, gpio_output_pin_t out_pin, - uint8_t bit /* 0 => 0, non-zero => 1 */) -{ - pin_on(out_pin); - if (bit) { - delay(base * 2); - } else { - delay(base); - } - pin_off(out_pin); - delay(base); -} - -void spin(uint32_t base, uint8_t c) -{ - uint8_t code; - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - - for (;;) { - code = c; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - - delay(base * 4); - } -} diff --git a/01-system-clock/src/vector.c b/01-system-clock/src/vector.c deleted file mode 100644 index e69de29..0000000 diff --git a/02-usart/.gdbinit b/02-usart/.gdbinit deleted file mode 100644 index 87932b3..0000000 --- a/02-usart/.gdbinit +++ /dev/null @@ -1 +0,0 @@ -set follow-fork-mode child diff --git a/02-usart/.ycm_extra_conf.py b/02-usart/.ycm_extra_conf.py deleted file mode 100644 index 8203412..0000000 --- a/02-usart/.ycm_extra_conf.py +++ /dev/null @@ -1,21 +0,0 @@ -import os -import ycm_core - -flags = [ - '-Wall', - '-DFOR_TESTING', - '-Iinclude', - '-Iinclude/arch/arm', - '-Itest_harness/', - '-DARCH_STMT32L4', - '-DDRY_RUN', - # -Iinclude/arch/arm -Itest_harness/ -DARCH_STM32L4 -DDRY_RUN -Wall -DFOR_TESTINGk - ] - -SOURCE_EXTENSIONS = [ '.cpp', '.cxx', '.cc', '.c', ] - -def FlagsForFile( filename, **kwargs ): - return { - 'flags': flags, - 'do_cache': True - } diff --git a/02-usart/Makefile.preamble b/02-usart/Makefile.preamble deleted file mode 100644 index f6e1370..0000000 --- a/02-usart/Makefile.preamble +++ /dev/null @@ -1,25 +0,0 @@ -OPT?=-O -PREFIX?=arm-unknown-eabi- -CC=$(PREFIX)gcc -LD=$(PREFIX)ld -CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude -Iinclude/arch/arm -LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static - -TEST_PREFIX=x86_64-pc-linux-gnu- -TEST_CFLAGS=-Iinclude -Iinclude/arch/x86_64 -Itest_harness -g3 -ggdb -DFOR_TESTING -Wall - -all: _$(PREFIX)_obs/main.elf - -_$(PREFIX)_obs/main.bin: _$(PREFIX)_obs/main.elf - $(PREFIX)objcopy -O binary _$(PREFIX)_obs/main.elf _$(PREFIX)_obs/main.bin - -flash: _$(PREFIX)_obs/main.bin - st-flash write _$(PREFIX)_obs/main.bin 0x8000000 - -clean: - rm -rf _*_obs - rm -rf tests/build - rm -rf test_harness/*.a test_harness/*.o - -genmake: - ./genmake.pl > Makefile diff --git a/02-usart/genmake.pl b/02-usart/genmake.pl deleted file mode 100755 index c4165a6..0000000 --- a/02-usart/genmake.pl +++ /dev/null @@ -1,128 +0,0 @@ -#!/usr/bin/perl - -use File::Basename; -use File::Find; -use Digest::SHA qw(sha1_hex); - -# This script is designed to introspect C files and generate a makefile to use. - -sub header_deps { - my $file = @_[0]; - my @headers; - - if (open(my $fh, '<:encoding(UTF-8)', $file)) { - print STDERR "\x1b[35m[Trace] - Reading file $file\x1b[00m\n"; - push(@headers, $file); - - while (<$fh>) { - /#include\s+"(.*)"\s*$/ && push(@headers, header_deps("include/$1")); - } - } - - return @headers; -} - -my @files; -find(sub { - push @files, "$File::Find::name" if $_ =~ /.*\.c/ - }, "src/"); - -my @test_files; -find(sub { - push @test_files, "$File::Find::name" if $_ =~ /.*\.c/ - }, "tests/"); - -my @header_files; -find(sub { - push @header_files, "$File::Find::name" if $_ =~ /.*\.h/; - }, "include/" ); - -my $idempotency_hash=sha1_hex("@files @test_files @header_files"); - -if ("$ARGV[0]" eq "hash") { - print "$idempotency_hash\n"; - exit 0 -} - -my @obj_files; - -open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble") - or die "Missing Makefile.preamble"; - -while (<$fh>) { - print "$_"; -} - -# Emit a rule that will rerun genmake if the c files do not match. -my $idempotency_cmd_make = - "/usr/bin/perl ./genmake.pl hash"; - -print "IDEMPOTENCY_HASH=$idempotency_hash\n"; - -my $arch_obs_dir = "_\$(PREFIX)_obs"; -print "CHEAT_PRE_MAKE := \$(shell mkdir -p $arch_obs_dir)\n"; - -foreach $file (@files) { - my $c_file = $file; - (my $file_no_ext = $file) =~ s/src\/(.*)\.c$/\1/g; - - my $obj_file = "$arch_obs_dir/${file_no_ext}.o"; - my $s_file = "${file_no_ext}.s"; - - push(@obj_files, $obj_file); - my @deps = header_deps($c_file); - - my $deps_as_join = join(" ", @deps); - - # Emit the rule to make the object file. - print "$obj_file: $deps_as_join\n\t"; - print "\@mkdir -p " . dirname($obj_file) . "\n\t"; - print '$(CC) -c ' . $c_file . ' -o ' . $obj_file . ' $(CFLAGS)' . "\n\n"; - - # Emit the rule to make the assembly file. - print "$s_file: $deps_as_join\n\t"; - print "\@mkdir -p " . dirname($obj_file) . "\n\t"; - print '$(CC) -S ' . $c_file . ' -o ' . $s_file . ' $(CFLAGS)' . "\n\n"; -} - -my $obj_files_deps = join(' ', @obj_files); - -my @tests_tgts; -foreach $file (@test_files) { - my $c_file = $file; - - my($basename, $directories, $suffix) = fileparse($file, qr/\.[^.]*/); - - my $outdir = $directories . "build/"; - my $outbinary = $outdir . $basename; - - my @deps = header_deps($c_file); - my $deps_as_join = join(" ", @deps); - - push (@test_tgts, "${outbinary}"); - print "${outbinary}: $deps_as_join $obj_files_deps test_harness/test_harness.a\n\t"; - print "mkdir -p " . dirname($outbinary) . "\n\t"; - print '$(CC) $(CFLAGS) -o' . ${outbinary} . ' ' . $c_file . ' ' . $obj_files_deps . " test_harness/test_harness.a\n\n"; - - print "$directories$basename:\n\t"; - print 'mkdir -p ' . $outdir . "\n\t"; - print 'PREFIX=$(TEST_PREFIX) CFLAGS="$(TEST_CFLAGS)" $(MAKE) ' . $outbinary . "\n\t"; - print $outbinary . "\n\n"; -} - -print "test_harness/test_harness.a: test_harness/test_harness.h test_harness/test_harness.c\n\t"; -print 'cd test_harness; $(MAKE) test_harness.a; cd ..' . "\n\n"; - -print "tests_: " . join(" ", @test_tgts) . "\n\t"; -print "" . join("\n\t", @test_tgts) . "\n\n"; - -print ".PHONY: tests\n"; -print "tests:\n\t"; -print 'PREFIX=$(TEST_PREFIX) CFLAGS="$(TEST_CFLAGS)" $(MAKE) tests_' . "\n\n"; - -print "FORCE:\n\t\n\n"; -print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t"; -print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] " - . "&& ./genmake.pl > Makefile && make $arch_obs_dir/main.elf ) " - . "|| " - . "\$(LD) -o $arch_obs_dir/main.elf \$(LD_FLAGS) $obj_files_deps\n\n"; diff --git a/02-usart/include/arch/arm/arch.h b/02-usart/include/arch/arm/arch.h deleted file mode 100644 index 22d0987..0000000 --- a/02-usart/include/arch/arm/arch.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef ARCH_H_ -#define ARCH_H_ - -#ifndef ARCH_STM32L4 -#define ARCH_STM32L4 -#endif - -#define CORTEX_M4 - -#define enable_all_interrupts() \ - asm volatile(" cpsie i ") - - -#define DMA1_BASE (0x40020000) -#define DMA2_BASE (0x40020400) - -#define USART1_BASE (0x40013800) -#define USART2_BASE (0x40004400) - -#define GPIOA_BASE (0x48000000) -#define GPIOB_BASE (0x48000400) -#define GPIOC_BASE (0x48000800) -#define GPIOH_BASE (0x48001C00) - -#define SRAM1_BASE (0x20000000) -#define SRAM2_BASE (0x2000C000) - -#define SYSTEM_CONFIG_BLOCK_BASE (0xE000E008) -#define NVIC_BASE (0xE000E004) -#define RCC_BASE (0x40021000) - -#define SPI1_BASE (0x40013000) -#define SPI3_BASE (0x40003C00) - -#include -#ifndef DRY_RUN -_Static_assert(sizeof(void*) == sizeof(uint32_t), "Pointers must be 32 bits"); -#endif - -extern uint32_t DATA_SEGMENT_START; -extern uint32_t DATA_SEGMENT_STOP; - -#endif /* ARCH_H_ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/apb.h b/02-usart/include/arch/stm32l4xxx/peripherals/apb.h deleted file mode 100644 index 11fa7ab..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/apb.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef H__APB_ -#define H__APB_ - -#endif /* H__APB_ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/clock.h b/02-usart/include/arch/stm32l4xxx/peripherals/clock.h deleted file mode 100644 index 6f628fd..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/clock.h +++ /dev/null @@ -1,128 +0,0 @@ -#ifndef CORE_CLOCK_H__ -#define CORE_CLOCK_H__ - -#include -#include "arch/stm32l4xxx/peripherals/rcc.h" - -#define PERIPH_BASE ((uint32_t)0x40000000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) -#define PWR_BASE (PERIPH_BASE + 0x7000) -#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ - -#ifndef __IO -#define __IO volatile -#endif - -typedef struct { - __IO uint32_t cr; - __IO uint32_t csr; -} pwr_t; - -// typedef struct { -// __IO uint32_t acr; -// __IO uint32_t pecr; -// __IO uint32_t pdkeyr; -// __IO uint32_t pekeyr; -// __IO uint32_t prgkeyr; -// __IO uint32_t optkeyr; -// __IO uint32_t sr; -// __IO uint32_t obr; -// __IO uint32_t wrpr; -// } flash_t; - -// #define FLASH (*(flash_t*) (FLASH_R_BASE)) -#define PWR (*(pwr_t*)(PWR_BASE)) - -/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */ -typedef enum { - PLL_DIVISOR_2 = 1, - PLL_DIVISOR_4 = 3, - PLL_DIVISOR_6 = 5, - PLL_DIVISOR_8 = 7, - PLL_DIVISOR_OFF = 0, -} pll_divisor_t; - -/* Valid values for the PLLP bits off the PLLCFG register. */ -typedef enum { - PLLP_DIVISOR_7 = 1, - PLLP_DIVISOR_17 = 3, - PLLP_DIVISOR_OFF = 0, -} pllp_divisor_t; - -/* Valid values for the PLLM bits of the PLLCFG register. */ -typedef enum { - PLLM_DIVISOR_1 = 0, - PLLM_DIVISOR_2 = 1, - PLLM_DIVISOR_3 = 2, - PLLM_DIVISOR_4 = 3, - PLLM_DIVISOR_5 = 4, - PLLM_DIVISOR_6 = 5, - PLLM_DIVISOR_7 = 6, - PLLM_DIVISOR_8 = 7, -} pllm_divisor_t; - -/* Possible sources for the input clock. */ -typedef enum { - PLL_SRC_NONE = 0, - PLL_SRC_MSI = 1, - PLL_SRC_HSI = 2, - PLL_SRC_HSE = 3, -} pll_src_t; - -/* Valid sources for the system clock. */ -typedef enum { - SYSTEM_CLOCK_SRC_MSI = 0, - SYSTEM_CLOCK_SRC_HSI = 1, - SYSTEM_CLOCK_SRC_HSE = 2, - SYSTEM_CLOCK_SRC_PLL = 3, -} system_clock_src_t; - -#define E_BADPLLN (-2) -#define E_BADPLLP_DIV (-1) -#define E_TIMEOUT (-3) -#define E_NOT_OFF (-4) -#define E_BAD_ARG (-5) - -#define enable_hsi(rcc, enabled) do { \ - if (enabled) { \ - (rcc)->c_r |= BIT(8); \ - } else { \ - (rcc)->c_r &= ~BIT(8); \ - } \ -} while(0) - -/* - * Sets the system clock to a full 80Mhz. - */ -int set_system_clock_MHz(uint8_t mhz); - -/* - * Set the PLL on. - */ -int pll_on(); - -/* - * Set the PLL off. - */ -int pll_off(); - -/* - * Sets the source of the system clock. - */ -int set_system_clock_src(system_clock_src_t src); - -/* - * Configure the PLL. - */ -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */); - -uint8_t get_clock_mhz(); - -#endif /* CORE_CLOCK_H__ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/dma.h b/02-usart/include/arch/stm32l4xxx/peripherals/dma.h deleted file mode 100644 index f62a92b..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/dma.h +++ /dev/null @@ -1,149 +0,0 @@ -#ifndef CORE_DMA_H_ -#define CORE_DMA_H_ - -/* - * Header file for definining the DMA (Direct Memory Access). - * - * A DMA is used to perform data transfers between segments of memory - * or between memory and peripherals. - * - * There are 2 DMA's on the chip. Each with 7 channels. - */ - -#include "kern/common.h" -#include -#include - -#define DMA1 (* (dma_t*) DMA1_BASE) -#define DMA2 (* (dma_t*) DMA2_BASE) - -typedef enum { - DMA_SIZE_8_BITS = 0, - DMA_SIZE_16_BITS = 1, - DMA_SIZE_32_BITS = 2, -} dma_size_t; - -typedef enum { - DMA_PRIORITY_LEVEL_LOW = 0, - DMA_PRIORITY_LEVEL_MEDIUM = 1, - DMA_PRIORITY_LEVEL_HIGH = 2, - DMA_PRIORITY_LEVEL_VERY_HIGH = 3 -} dma_priority_level_t; - -typedef enum { - READ_FROM_PERIPHERAL = 0, - READ_FROM_MEMORY = 1, -} dma_dir_t; - -typedef struct { - -#define dma_cc_en (1 << 0) // channel enable -#define dma_cc_tcie (1 << 1) // transfer complete interrupt enable -#define dma_cc_htie (1 << 2) // half transfer interrupt enable -#define dma_cc_teie (1 << 3) // transfer error interrupt enable -#define dma_cc_dir (1 << 4) // data transfer direction -#define dma_cc_circ (1 << 5) // circular mode -#define dma_cc_pinc (1 << 6) // peripheral increment mode -#define dma_cc_minc (1 << 7) // memory increment mode -#define dma_cc_psize (3 << 8) // Peripheral size -#define dma_cc_msize (3 << 10) // Memory size -#define dma_cc_pl (3 << 12) // Priority level -#define dma_cc_mem2mem (1 << 14) // Memory to memory mode - - __IO uint32_t cc_r; - - /* Number of data to transfer. Can only store a short. */ - __IO uint32_t cndt_r; - - /* DMA channel peripheral address register. - * Defines a memory address if mem2mem is set. */ - __IO uint32_t cpa_r; - - /* DMA channel memory address register. - * Defines another perpipheral address if peripheral-periphal mode is set. */ - __IO uint32_t cma_r; - - __IO uint32_t reserved; -} dma_channel_config_t; - -typedef struct { - // DMA Interrupt status register. -#define dma_gif1 (1 << 0) // global interrupt flag for channel 1 -#define dma_tcif1 (1 << 1) // transfer complete (TC) flag for channel 1 -#define dma_htif1 (1 << 2) // half transfer (HT) flag for channel 1 -#define dma_teif1 (1 << 3) // transfer error (TE) flag for channel 1 -#define dma_gif2 (1 << 4) // global interrupt flag for channel 2 -#define dma_tcif2 (1 << 5) // transfer complete (TC) flag for channel 2 -#define dma_htif2 (1 << 6) // half transfer (HT) flag for channel 2 -#define dma_teif2 (1 << 7) // transfer error (TE) flag for channel 2 -#define dma_gif3 (1 << 8) // global interrupt flag for channel 3 -#define dma_tcif3 (1 << 9) // transfer complete (TC) flag for channel 3 -#define dma_htif3 (1 << 10) // half transfer (HT) flag for channel 3 -#define dma_teif3 (1 << 11) // transfer error (TE) flag for channel 3 -#define dma_gif4 (1 << 12) // global interrupt flag for channel 4 -#define dma_tcif4 (1 << 13) // transfer complete (TC) flag for channel 4 -#define dma_htif4 (1 << 14) // half transfer (HT) flag for channel 4 -#define dma_teif4 (1 << 15) // transfer error (TE) flag for channel 4 -#define dma_gif5 (1 << 16) // global interrupt flag for channel 5 -#define dma_tcif5 (1 << 17) // transfer complete (TC) flag for channel 5 -#define dma_htif5 (1 << 18) // half transfer (HT) flag for channel 5 -#define dma_teif5 (1 << 19) // transfer error (TE) flag for channel 5 -#define dma_gif6 (1 << 20) // global interrupt flag for channel 6 -#define dma_tcif6 (1 << 21) // transfer complete (TC) flag for channel 6 -#define dma_htif6 (1 << 22) // half transfer (HT) flag for channel 6 -#define dma_teif6 (1 << 23) // transfer error (TE) flag for channel 6 -#define dma_gif7 (1 << 24) // global interrupt flag for channel 7 -#define dma_tcif7 (1 << 25) // transfer complete (TC) flag for channel 7 -#define dma_htif7 (1 << 26) // half transfer (HT) flag for channel 7 -#define dma_teif7 (1 << 27) // transfer error (TE) flag for channel 7 - __IO uint32_t is_r; - - // DMA Interrupt flag clear register -#define dma_cgif1 (1 << 0) // global interrupt flag clear for channel 1 -#define dma_ctcif1 (1 << 1) // transfer complete flag clear for channel 1 -#define dma_chtif1 (1 << 2) // half transfer flag clear for channel 1 -#define dma_cteif1 (1 << 3) // transfer error flag clear for channel 1 -#define dma_cgif2 (1 << 4) // global interrupt flag clear for channel 2 -#define dma_ctcif2 (1 << 5) // transfer complete flag clear for channel 2 -#define dma_chtif2 (1 << 6) // half transfer flag clear for channel 2 -#define dma_cteif2 (1 << 7) // transfer error flag clear for channel 2 -#define dma_cgif3 (1 << 8) // global interrupt flag clear for channel 3 -#define dma_ctcif3 (1 << 9) // transfer complete flag clear for channel 3 -#define dma_chtif3 (1 << 10) // half transfer flag clear for channel 3 -#define dma_cteif3 (1 << 11) // transfer error flag clear for channel 3 -#define dma_cgif4 (1 << 12) // global interrupt flag clear for channel 4 -#define dma_ctcif4 (1 << 13) // transfer complete flag clear for channel 4 -#define dma_chtif4 (1 << 14) // half transfer flag clear for channel 4 -#define dma_cteif4 (1 << 15) // transfer error flag clear for channel 4 -#define dma_cgif5 (1 << 16) // global interrupt flag clear for channel 5 -#define dma_ctcif5 (1 << 17) // transfer complete flag clear for channel 5 -#define dma_chtif5 (1 << 18) // half transfer flag clear for channel 5 -#define dma_cteif5 (1 << 19) // transfer error flag clear for channel 5 -#define dma_cgif6 (1 << 20) // global interrupt flag clear for channel 6 -#define dma_ctcif6 (1 << 21) // transfer complete flag clear for channel 6 -#define dma_chtif6 (1 << 22) // half transfer flag clear for channel 6 -#define dma_cteif6 (1 << 23) // transfer error flag clear for channel 6 -#define dma_cgif7 (1 << 24) // global interrupt flag clear for channel 7 -#define dma_ctcif7 (1 << 25) // transfer complete flag clear for channel 7 -#define dma_chtif7 (1 << 26) // half transfer flag clear for channel 7 -#define dma_cteif7 (1 << 27) // transfer error flag clear for channel 7 - __IO uint32_t ifc_r; - - dma_channel_config_t channel_config[7]; - - __IO uint32_t reserved[5]; - - /* DMA channel selection register. */ -#define dma_c1s (0xF << 0) // DMA channel 1 selection. -#define dma_c2s (0xF << 4) // DMA channel 2 selection. -#define dma_c3s (0xF << 8) // DMA channel 3 selection. -#define dma_c4s (0xF << 12) // DMA channel 4 selection. -#define dma_c5s (0xF << 16) // DMA channel 5 selection. -#define dma_c6s (0xF << 20) // DMA channel 6 selection. -#define dma_c7s (0xF << 24) // DMA channel 7 selection. - __IO uint32_t csel_r; -} dma_t; - -static_assert(offsetof(dma_t, csel_r) == 0xA8, "Offset check failed."); - -#endif /* CORE_DMA_H_ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/flash.h b/02-usart/include/arch/stm32l4xxx/peripherals/flash.h deleted file mode 100644 index 28a3d6c..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/flash.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef H__FLASH_ -#define H__FLASH_ - -#include "kern/common.h" - -/* - * Header file for dealing with flash. - */ - -#define FLASH_BASE 0x40022000 - -typedef struct { - __IO uint32_t ac_r; /* Flash access control register. */ - - /* TODO fill out the rest. */ -} PACKED flash_t; - -#define FLASH (*(__IO flash_t*)FLASH_BASE) - -#endif /* H__FLASH_ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h b/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h deleted file mode 100644 index 944d725..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/gpio.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef CORE_GPIO_H__ -#define CORE_GPIO_H__ - -#include "kern/common.h" -#include "arch/stm32l4xxx/peripherals/rcc.h" - -#include - -/* - * Structure defining the layout of the layout of the GPIO registers on the - * stm32l432 development board. - */ -typedef struct GPIO_PORT_STR { - /* Mode of each GPIO pin for this GPIO port. */ -#define gpio_mode_n(off) (3 << ((off) * 2)) - __IO uint32_t mode_r; /* Mode register */ - - /* Output type for each gpio pin in this port. */ -#define gpio_otype_n(off) (1 << (off)) - __IO uint32_t otype_r; - - /* GPIO port output speed. */ -#define gpio_ospeed_n(off) (3 << ((off) * 2)) - __IO uint32_t ospeed_r; - - /* GPIO port pull-up/pull-down register */ -#define gpio_pupd_n(off) (3 << ((off) * 2)) - __IO uint32_t pupd_r; - - /* GPIO port input data register. */ -#define gpio_idr_n(off) (1 << (off)) - __IO uint32_t id_r; - - /* GPIO port output data register. */ -#define gpio_odr_n(off) (1 << (off)) - __IO uint32_t od_r; - - /* GPIO port bit set/reset register. */ -#define gpio_bs_n(off) (1 << (off)) -#define gpio_br_n(off) (1 << (off)) - __IO uint32_t bsr_r; - - /* GPIO port configuration lock register. */ -#define gpio_lck_n(off) (1 << (off)) -#define gpio_lckk (1 << 16) - __IO uint32_t lck_r; - - /* Alternate function low-register. */ -#define gpio_afsel_n(off) (0xf << ((off) * 4)) - __IO uint32_t af_rl; - /* Alternate function high-register. */ - __IO uint32_t af_rh; - - /* GPIO port bit register. */ -#define gpio_br_n(off) (1 << (off)) - __IO uint32_t br_r; - - /* Analog switch control register. */ -#define gpio_asc_n(off) (1 << (off)) - __IO uint32_t asc_r; -} PACKED gpio_port_config_t; - -static_assert( - offsetof(gpio_port_config_t, asc_r) == 0x2C, "Offset check failed"); - -#endif diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/irq.h b/02-usart/include/arch/stm32l4xxx/peripherals/irq.h deleted file mode 100644 index 52878ca..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/irq.h +++ /dev/null @@ -1,89 +0,0 @@ -#ifndef CORE_IRQ_H__ -#define CORE_IRQ_H__ - -#include - -/* - * Include file for interrupt service routines. - */ - -typedef enum { -#define IRQ_RESERVED(n) -#define IRQ(name_, uname, num) \ - IRQ_##uname = num, -#include "arch/stm32l4xxx/peripherals//isrs.inc" -#undef IRQ -#undef IRQ_RESERVED -} interrupt_t; - -/* Defines a set of interrupts so they may be enabled all at once. */ -typedef struct { - uint32_t sysirqs; /* System iterrupts. */ - uint32_t irqs[8]; -} interrupt_set_t; - -inline static void interrupt_set_add( - interrupt_set_t* interrupt_set, interrupt_t interrupt) -{ - if (interrupt < 16) { - interrupt_set->sysirqs |= 1 << interrupt; - return; - } - - interrupt -= 16; - int loc = interrupt / 32; - int off = interrupt % 32; - - interrupt_set->irqs[loc] |= 1 << off; -} - -inline static void interrupt_set_remove( - interrupt_set_t* interrupt_set, interrupt_t interrupt) -{ - if (interrupt < 16) { - interrupt_set->sysirqs &= ~(1 << interrupt); - return; - } - - interrupt -= 16; - int loc = interrupt / 32; - int off = interrupt % 32; - - interrupt_set->irqs[loc] &= ~(1 << off); -} - -/* - * The interrupt service routines. These link in the function `main` as the - * main function. - */ -extern const void* vectors[]; - -/* - * Defines an error state. This loops forever and defines a distinct flashing - * pattern to let the user know an unhandled ISR happened. - */ -void unhandled_isr(uint8_t val); - -#define enable_interrupt(val) \ - {interrupt_set_t itrset = { 0 }; \ - interrupt_set_add(&itrset, val); \ - enable_interrupts(&itrset);} - -#define disable_interrupt(val) \ - {interrupt_set_t itrset = { 0 }; \ - interrupt_set_add(&itrset, val); \ - disable_interrupts(&itrset);} - -/* - * Enables the provided interrupt. Note that if the interrupt is one of the - * system interrupts (first 16) this function has no effect because those - * interrupts are always enabled. - */ -void enable_interrupts(interrupt_set_t* interrupts); - -/* - * Enables the provided interrupt - */ -void disable_interrupts(interrupt_set_t* interrupts); - -#endif /* CORE_IRQ_H_ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/isrs.inc b/02-usart/include/arch/stm32l4xxx/peripherals/isrs.inc deleted file mode 100644 index 0682238..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/isrs.inc +++ /dev/null @@ -1,112 +0,0 @@ -/* - * The following is a list of interrupts listed in a way - * that makes it easy to macro-process them by defining - * macro definitions for IRQ and IRQ_RESERVED alike followed - * by including this file. - */ -IRQ(on_reset, RESET, 1) -IRQ(on_nmi, NMI, 2) -IRQ(on_hard_fault, HARD_FAULT, 3) -IRQ(on_mem_manage, MEM_MANAGE, 4) -IRQ(on_bus_fault, BUS_FAULT, 5) -IRQ(on_usage_fault, USAGE_FAULT, 6) -IRQ_RESERVED(7) -IRQ_RESERVED(8) -IRQ_RESERVED(9) -IRQ_RESERVED(10) -IRQ(on_svc, SVC, 11) -IRQ(on_debug_mon, DEBUG_MON, 12) -IRQ_RESERVED(13) -IRQ(on_pendsv, PENDSV, 14) -IRQ(on_systick, SYSTICK, 15) -IRQ(on_wwdg_irq, WWDG_IRQ, 16) -IRQ(on_pvd_irq, PVD_IRQ, 17) -IRQ(on_tamper_stamp_irq, TAMPER_STAMP_IRQ, 18) -IRQ(on_rtc_wkup_irq, RTC_WKUP_IRQ, 19) -IRQ(on_flash_irq, FLASH_IRQ, 20) -IRQ(on_rcc_irq, RCC_IRQ, 21) -IRQ(on_exti0_irq, EXTI0_IRQ, 22) -IRQ(on_exti1_irq, EXTI1_IRQ, 23) -IRQ(on_exti2_irq, EXTI2_IRQ, 24) -IRQ(on_exti3_irq, EXTI3_IRQ, 25) -IRQ(on_exti4_irq, EXTI4_IRQ, 26) -IRQ(on_dma1_channel1_irq, DMA1_CHANNEL1_IRQ, 27) -IRQ(on_dma1_channel2_irq, DMA1_CHANNEL2_IRQ, 28) -IRQ(on_dma1_channel3_irq, DMA1_CHANNEL3_IRQ, 29) -IRQ(on_dma1_channel4_irq, DMA1_CHANNEL4_IRQ, 30) -IRQ(on_dma1_channel5_irq, DMA1_CHANNEL5_IRQ, 31) -IRQ(on_dma1_channel6_irq, DMA1_CHANNEL6_IRQ, 32) -IRQ(on_dma1_channel7_irq, DMA1_CHANNEL7_IRQ, 33) -IRQ(on_adc1_irq, ADC1_IRQ, 34) -IRQ(on_can1_tx, CAN1_TX, 35) -IRQ(on_can1_rx0, CAN1_RX0, 36) -IRQ(on_can1_rx1, CAN1_RX1, 37) -IRQ(on_can1_sce, CAN1_SCE, 38) -IRQ(on_exti9_5, EXTI9_5, 39) -IRQ(on_tim1_brk, TIM1_BRK, 40) -IRQ(on_tim1_up, TIM1_UP, 41) -IRQ(on_tim1_trg_com, TIM1_TRG_COM, 42) -IRQ(on_tim1_cc, TIM1_CC, 43) -IRQ(on_tim2, TIM2, 44) -IRQ(on_tim3, TIM3, 45) -IRQ(on_tim4, TIM4, 46) -IRQ(on_i2c1_ev, I2C1_EV, 47) -IRQ(on_i2c1_er, I2C1_ER, 48) -IRQ(on_i2c2_ev, I2C2_EV, 49) -IRQ(on_i2c2_er, I2C2_ER, 50) -IRQ(on_spi1, SPI1, 51) -IRQ(on_spi2, SPI2, 52) -IRQ(on_usart1, USART1, 53) -IRQ(on_usart2, USART2, 54) -IRQ(on_usart3, USART3, 55) -IRQ(on_exti15_10, EXTI15_10, 56) -IRQ(on_rtc_alarm, RTC_ALARM, 57) -IRQ(on_dfsdm1_flt3, DFSDM1_FLT3, 58) -IRQ(on_tim8_brk, TIM8_BRK, 59) -IRQ(on_tim8_up, TIM8_UP, 60) -IRQ(on_tim8_trg_com, TIM8_TRG_COM, 61) -IRQ(on_tim8_cc, TIM8_CC, 62) -IRQ(on_adc3, ADC3, 63) -IRQ(on_fmc, FMC, 64) -IRQ(on_sdmmc1, SDMMC1, 65) -IRQ(on_tim5, TIM5, 66) -IRQ(on_spi3, SPI3, 67) -IRQ(on_uart4, UART4, 68) -IRQ(on_uart5, UART5, 69) -IRQ(on_tim6_dacunder, TIM6_DACUNDER, 70) -IRQ(on_tim7, TIM7, 71) -IRQ(on_dma2_channel1, DMA2_CHANNEL1_IRQ, 72) -IRQ(on_dma2_channel2, DMA2_CHANNEL2_IRQ, 73) -IRQ(on_dma2_channel3, DMA2_CHANNEL3_IRQ, 74) -IRQ(on_dma2_channel4, DMA2_CHANNEL4_IRQ, 75) -IRQ(on_dma2_channel5, DMA2_CHANNEL5_IRQ, 76) -IRQ(on_dfsdm1_flt0, DFSDM1_FLT0, 77) -IRQ(on_dfsdm1_flt1, DFSDM1_FLT1, 78) -IRQ(on_dfsdm1_flt2, DFSDM1_FLT2, 79) -IRQ(on_comp, COMP, 80) -IRQ(on_lptim1, LPTIM1, 81) -IRQ(on_lptim2, LPTIM2, 82) -IRQ(on_otg_fs, OTG_FS, 83) -IRQ(on_dma2_channel6, DMA2_CHANNEL6, 84) -IRQ(on_dma2_channel7, DMA2_CHANNEL7, 85) -IRQ(on_lpuart1, LPUART1, 86) -IRQ(on_quadspi, QUADSPI, 87) -IRQ(on_i2c3_ev, I2C3_EV, 88) -IRQ(on_i2c3_er, I2C3_ER, 89) -IRQ(on_sai1, SAI1, 90) -IRQ(on_sai2, SAI2, 91) -IRQ(on_swpmi1, SWPMI1, 92) -IRQ(on_tsc, TSC, 93) -IRQ(on_lcd, LCD, 94) -IRQ(on_aes, AES, 95) -IRQ(on_rng, RNG, 96) -IRQ(on_fpu, FPU, 97) -IRQ(on_hash, HASH, 98) -IRQ(on_i2c4_ev, I2C4_EV, 99) -IRQ(on_i2c4_er, I2C4_ER, 100) -IRQ(on_dcmi, DCMI, 101) -IRQ(on_can2_tx, CAN2_TX, 102) -IRQ(on_can2_rx0, CAN2_RX0, 103) -IRQ(on_can2_rx1, CAN2_RX1, 104) -IRQ(on_can2_sce, CAN2_SCE, 105) -IRQ(on_dma2d, DMA2D, 106) diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/nvic.h b/02-usart/include/arch/stm32l4xxx/peripherals/nvic.h deleted file mode 100644 index 1645a2d..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/nvic.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef NVIC_H_ -#define NVIC_H_ - -#include "arch.h" -#include "kern/common.h" - -typedef __IO struct { -#define nvic_intlinesnum (0x0F << 0) - uint32_t ict_r; /* Interrupt control type register. */ - - uint8_t reserved0[0xF8]; - - uint32_t ise_r[8]; - - uint8_t reserved1[0x60]; - - uint32_t ice_r[8]; - - uint8_t reserved2[0x60]; - - uint32_t isp_r[8]; - - uint8_t reserved3[0x60]; - - uint32_t icp_r[8]; - - uint8_t reserved4[0x60]; - - uint32_t iab_r[8]; - - uint8_t reserved5[0xE0]; - - uint32_t ip_r[60]; -} nvic_t; - -static_assert(offsetof(nvic_t, ise_r) == 0x00FC, "Offset check failed"); -static_assert(offsetof(nvic_t, ice_r) == 0x017C, "Offset check failed"); -static_assert(offsetof(nvic_t, isp_r) == 0x01FC, "Offset check failed"); -static_assert(offsetof(nvic_t, icp_r) == 0x027C, "Offset check failed"); -static_assert(offsetof(nvic_t, iab_r) == 0x02FC, "Offset check failed"); -static_assert(offsetof(nvic_t, ip_r) == 0x03FC, "Offset check failed"); - -#define NVIC (* (nvic_t*) NVIC_BASE) - - -#endif /* NVIC_H_ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/rcc.h b/02-usart/include/arch/stm32l4xxx/peripherals/rcc.h deleted file mode 100644 index de7b568..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/rcc.h +++ /dev/null @@ -1,132 +0,0 @@ -#ifndef H__RCC_ -#define H__RCC_ - -#include "arch.h" -#include "kern/common.h" -#include - -typedef struct { - __IO uint32_t c_r; /* Clock control register. 0x00 */ - __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ - __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ - __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ - __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ - - __IO uint32_t reserved_1; /* Not used. offset 0x14. */ - - __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ - __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ - __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ - - __IO uint32_t reserved_2; /* Not used. offset 0x24. */ - - __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ - __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ - __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ - - __IO uint32_t reserved_3; /* Not used. offset 0x34. */ - -#define rcc_lptim1rst (1 << 31) // Low Power Timer 1 reset -#define rcc_opamprst (1 << 30) // OPAMP interface reset -#define rcc_dac1rst (1 << 29) // DAC1 interface reset -#define rcc_pwrrst (1 << 28) // Power interface reset -#define rcc_can2rst (1 << 26) // CAN2 reset (this bit is reserved for STM32L47x/L48x devices) -#define rcc_can1rst (1 << 25) // CAN1 reset -#define rcc_crsrst (1 << 24) // CRS reset (this bit is reserved for STM32L47x/L48x devices) -#define rcc_i2c3rst (1 << 23) // I2C3 reset -#define rcc_i2c2rst (1 << 22) // I2C2 reset -#define rcc_i2c1rst (1 << 21) // I2C1 reset -#define rcc_uart5rst (1 << 20) // UART5 reset -#define rcc_uart4rst (1 << 19) // UART4 reset -#define rcc_usart3rst (1 << 18) // USART3 reset -#define rcc_usart2rst (1 << 17) // USART2 reset -#define rcc_reserved (1 << 16) // must be kept at reset value. -#define rcc_spi3rst (1 << 15) // SPI3 reset -#define rcc_spi2rst (1 << 14) // SPI2 reset -#define rcc_lcdrst (1 << 9) // interface reset (this bit is reserved for STM32L471/L4x5 devices) -#define rcc_tim7rst (1 << 5) // timer reset -#define rcc_tim6rst (1 << 4) // timer reset -#define rcc_tim5rst (1 << 3) // timer reset -#define rcc_tim4rst (1 << 2) // timer reset -#define rcc_tim3rst (1 << 1) // timer reset -#define rcc_tim2rst (1 << 0) // timer reset - __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */ - __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */ - __IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */ - - __IO uint32_t reserved_4; /* Not used. offset 0x44. */ - -#define rcc_dma1en (1 << 0) /* DMA1 clock enable. */ -#define rcc_dma2en (1 << 1) /* DMA2 clock enable. */ -#define rcc_flashen (1 << 8) /* Flash memory interface clock enable. */ -#define rcc_crcen (1 << 12) /* CRC clock enable. */ -#define rcc_tscen (1 << 16) /* Touch sensing controller clock enable. */ -#define rcc_dmad2en (1 << 17) /* DMA2D clock enabled. */ - __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ - -#define rcc_gpioen(port) (1 << (port)) -#define rcc_otgfsen (1 << 12) -#define rcc_adcen (1 << 13) -#define rcc_dcmien (1 << 14) -#define rcc_assen (1 << 16) -#define rcc_hashen (1 << 17) -#define rcc_rngen (1 << 18) - __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ - __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ - - __IO uint32_t reserved_5; /* Not used. offset 0x54. */ - - __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ - __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ - __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ - - __IO uint32_t reserved_6; /* Not used. offset 0x64. */ - - __IO uint32_t ahb1smen_r; /* 0x68 */ - __IO uint32_t ahb2smen_r; /* 0x6c */ - __IO uint32_t ahb3smen_r; /* 0x70 */ - - __IO uint32_t reserved_7; - - __IO uint32_t apb1smen_r1; /* 0x78 */ - __IO uint32_t apb1smen_r2; /* 0x7c */ - __IO uint32_t apb2smen_r; /* 0x80 */ - - __IO uint32_t reserved_8; - - __IO uint32_t ccip_r; /* 0x88 */ -} PACKED rcc_t; - -static_assert(offsetof(rcc_t, ccip_r) == 0x88, "Offset check failed."); - -#define RCC (*(__IO rcc_t*)RCC_BASE) - -/* Macros to operate on the RCC registers. */ - -/* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hse(rcc, e) \ - do { \ - if (e) { \ - (rcc).c_r |= 1 << 16; \ - } else { \ - (rcc).c_r &= ~(1 << 16); \ - } \ - } while (0) - -/* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hsi(rcc, e) \ - do { \ - if (e) { \ - (rcc).c_r |= 1 << 8; \ - } else { \ - (rcc).c_r &= ~(1 << 8); \ - } \ - } while (0) - -/* Checks to see if the hse is ready. */ -#define hse_ready(rcc) ((rcc).c_r & (1 << 17)) - -/* Checks to see if the hse is ready. */ -#define hsi_ready(rcc) ((rcc).c_r & (1 << 10)) - -#endif diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/spi.h b/02-usart/include/arch/stm32l4xxx/peripherals/spi.h deleted file mode 100644 index a39a0bb..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/spi.h +++ /dev/null @@ -1,102 +0,0 @@ -#ifndef CORE_SPI_H_ -#define CORE_SPI_H_ - -#include "kern/common.h" -#include "arch.h" - -#define SPI1 (*((spi_t*)(SPI1_BASE))) -#define SPI3 (*((spi_t*)(SPI3_BASE))) - -typedef enum { - SPI_BAUD_FPCLK_DIV_2 = 0, - SPI_BAUD_FPCLK_DIV_4 = 1, - SPI_BAUD_FPCLK_DIV_8 = 2, - SPI_BAUD_FPCLK_DIV_16 = 3, - SPI_BAUD_FPCLK_DIV_32 = 4, - SPI_BAUD_FPCLK_DIV_64 = 5, - SPI_BAUD_FPCLK_DIV_128 = 6, - SPI_BAUD_FPCLK_DIV_256 = 7, -} spi_baud_rate_t; - -typedef enum { - SPI_DATA_SIZE_NOT_USED_0 = 0, - SPI_DATA_SIZE_NOT_USED_1 = 1, - SPI_DATA_SIZE_NOT_USED_2 = 2, - SPI_DATA_SIZE_4_BITS = 3, - SPI_DATA_SIZE_5_BITS = 4, - SPI_DATA_SIZE_6_BITS = 5, - SPI_DATA_SIZE_7_BITS = 6, - SPI_DATA_SIZE_8_BITS = 7, - SPI_DATA_SIZE_9_BITS = 8, - SPI_DATA_SIZE_10_BITS = 9, - SPI_DATA_SIZE_11_BITS = 10, - SPI_DATA_SIZE_12_BITS = 11, - SPI_DATA_SIZE_13_BITS = 12, - SPI_DATA_SIZE_14_BITS = 13, - SPI_DATA_SIZE_15_BITS = 14, - SPI_DATA_SIZE_16_BITS = 15, -} spi_data_size_t; - -typedef __IO struct { - /* spi control register. */ -#define spi_bidimode (1 << 15) /* Bidirectional data mode enable. */ -#define spi_bidioe (1 << 14) /* Output enable in bidirectional mode */ -#define spi_crcen (1 << 13) /* Hardware CRC calculation enable */ -#define spi_crcnext (1 << 12) /* Transmit CRC next */ -#define spi_crcl (1 << 11) /* CRC length */ -#define spi_rxonly (1 << 10) /* Receive only mode enabled. */ -#define spi_ssm (1 << 9) /* Software slave management */ -#define spi_ssi (1 << 8) /* Internal slave select */ -#define spi_lsbfirst (1 << 7) /* Frame format */ -#define spi_spe (1 << 6) /* SPI enable */ -#define spi_br (7 << 3) /* SPI enable */ -#define spi_mstr (1 << 2) /* Master selection */ -#define spi_cpol (1 << 1) /* Clock polarity */ -#define spi_cpha (1 << 0) /* Clock phase */ - uint32_t c_r1; - - /* spi control register #2 */ -#define spi_ldma_tx (1 << 14) /* Last DMA transfer for transmission */ -#define spi_ldma_rx (1 << 13) /* Last DMA transfer for reception */ -#define spi_frxth (1 << 12) /* FIFO reception threshold */ -#define spi_ds (0xF << 8) /* Data size */ -#define spi_txeie (1 << 7) /* Tx buffer empty interrupt enable */ -#define spi_rxneie (1 << 6) /* RX buffer not empty interrupt enable */ -#define spi_errie (1 << 5) /* Error interrupt enable */ -#define spi_frf (1 << 4) /* Frame format */ -#define spi_nssp (1 << 3) /*: NSS pulse management */ -#define spi_ssoe (1 << 2) /* SS output enable */ -#define spi_txdmaen (1 << 1) /* Tx buffer DMA enable */ -#define spi_rxdmaen (1 << 0) /* Rx buffer DMA enable */ - uint32_t c_r2; - - /* spi status register. */ -#define spi_ftlvl (3 << 11) /* Transmisison level */ -#define spi_frlvl (3 << 9) /* Reception level */ -#define spi_fre (1 << 8) /* Frame format error */ -#define spi_bsy (1 << 7) /* Busy flag */ -#define spi_ovr (1 << 6) /* Overrun flag */ -#define spi_modf (1 << 5) /* Mode fault */ -#define spi_crcerr (1 << 4) /* CRC error flag */ -#define spi_txe (1 << 1) /* Transmit buffer empty */ -#define spi_rxne (1 << 0) /* Receive buffer not empty */ - uint32_t s_r; - - /* spi data register. Really only the least-significant 16 bits are used. - * reading from this register reads from the Rx FIFO while writing to it - * writes to the Tx FIFO. */ - __IO uint32_t d_r; - - /* spi CRC polynomial register. */ - uint32_t crcp_r; - - /* spi rx CRC register. */ - uint32_t rxcrc_r; - - /* spi tx CRC register. */ - uint32_t txcrc_r; -} spi_t; - -static_assert(offsetof(spi_t, txcrc_r) == 0x18, "Offset check failed."); - -#endif /* CORE_SPI_H_ */ diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/system.h b/02-usart/include/arch/stm32l4xxx/peripherals/system.h deleted file mode 100644 index b6ff0a6..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/system.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef CORE_SYSTEM_H_ -#define CORE_SYSTEM_H_ - -#include -#include "kern/common.h" - -typedef __IO struct { - uint32_t actl_r; /* Auxiliary Control Register, ACTLR on page 4-5 */ - - uint32_t reserved0; - -#define scb_enable (1 << 0) -#define scb_tickint (1 << 1) -#define scb_clksource (1 << 2) -#define scb_countflag (1 << 16) - uint32_t stcs_r; /* SysTick Control and Status Register */ - - uint32_t strv_r; /* SysTick Reload Value Register */ - uint32_t stcv_r; /* SysTick Current Value Register */ - uint32_t stc_r; /* SysTick Calibration Value Register */ - - uint8_t reserved1[3296]; - - uint32_t cpuid; /* CPUID Base Register, CPUID on page 4-5 */ - uint32_t ics_r; /* RO 0x00000000 Interrupt Control and State Register */ - uint32_t vto_r; /* Vector Table Offset Register */ - uint32_t airc_r; /* Application Interrupt and Reset Control Register */ - uint32_t sc_r; /* System Control Register */ - uint32_t cc_r; /* Configuration and Control Register. */ - uint32_t shp_r1; /* System Handler Priority Register 1 */ - uint32_t shp_r2; /* System Handler Priority Register 2 */ - uint32_t shp_r3; /* System Handler Priority Register 3 */ - uint32_t shcs_r; /* System Handler Control and State Register */ - uint32_t cfs_r; /* Configurable Fault Status Registers */ - uint32_t hfs_r; /* HardFault Status register */ - uint32_t dfs_r; /* Debug Fault Status Register */ - uint32_t mmfa_r; /* MemManage Address Registerb */ - uint32_t bfa_r; /* BusFault Address Registerb */ - uint32_t afs_r; /* Auxiliary Fault Status Register, AFSR on page 4-6 */ - uint32_t id_pf_r0; /* Processor Feature Register 0 */ - uint32_t id_pf_r1; /* Processor Feature Register 1 */ - uint32_t id_df_r0; /* Debug Features Register 0 */ - uint32_t id_af_r0; /* Auxiliary Features Register 0 */ - uint32_t id_mmf_r0; /* Memory Model Feature Register 0 */ - uint32_t id_mmf_r1; /* 0x00000000 Memory Model Feature Register 1 */ - uint32_t id_mmf_r2; /* Memory Model Feature Register 2 */ - uint32_t id_mmf_r3; /* Memory Model Feature Register 3 */ - uint32_t id_isa_r0; /* Instruction Set Attributes Register 0 */ - uint32_t id_isa_r1; /* Instruction Set Attributes Register 1 */ - uint32_t id_isa_r2; /* Instruction Set Attributes Register 2 */ - uint32_t id_isa_r3; /* Instruction Set Attributes Register 3 */ - uint32_t id_isa_r4; /* Instruction Set Attributes Register 4 */ - - uint8_t reserved2[20]; - - uint32_t cpac_r; /* Coprocessor Access Control Register */ - - uint8_t reserved3[372]; - - uint32_t sti_r; /* Software Triggered Interrupt Register */ -} system_control_block_t; - -#define ARM_SYSCFG_BASE 0xE000E008 -#define CHECK_OFFSET(member, expected) \ - static_assert(ARM_SYSCFG_BASE + offsetof(system_control_block_t, member) == expected, \ - "Offset check failed") - -CHECK_OFFSET(stcs_r, 0xE000E010); -CHECK_OFFSET(cpuid, 0xE000ED00); -CHECK_OFFSET(cpac_r, 0xE000ED88); -CHECK_OFFSET(id_mmf_r3, 0xE000ED5C); -CHECK_OFFSET(sti_r, 0xE000EF00); - -#define SCB (*(system_control_block_t*)SYSTEM_CONFIG_BLOCK_BASE) - -#endif diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc b/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc deleted file mode 100644 index 66d347c..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc +++ /dev/null @@ -1,100 +0,0 @@ -AFN(CAN1_RX, 9, PA11) -AFN(CAN1_TX, 9, PA12) -AFN(COMP1_OUT, 12, PA0, 12, PB0, 6, PA11, 6, PA6) -AFN(COMP2_OUT, 12, PA2, 12, PA7, 12, PB5) -AFN(I2C1_SCL, 4, PA9, 4, PB6) -AFN(I2C1_SDA, 4, PA10, 4, PB7) -AFN(I2C1_SMBA, 4, PA14, 4, PA1, 4, PB5) -AFN(I2C3_SCL, 4, PA7) -AFN(I2C3_SDA, 4, PB4) -AFN(IR_OUT, 1, PA13) -AFN(JTCK_SWCLK, 0, PA14) -AFN(JTDI, 0, PA15) -AFN(JTDO_TRACESWO, 0, PB3) -AFN(JTMS_SWDIO, 0, PA13) -AFN(LPTIM1_ETR, 1, PB6) -AFN(LPTIM1_IN1, 1, PB5) -AFN(LPTIM1_IN2, 1, PB7) -AFN(LPTIM1_OUT, 1, PA14) -AFN(LPTIM2_ETR, 14, PA5) -AFN(LPTIM2_IN1, 14, PB1) -AFN(LPTIM2_OUT, 14, PA4, 14, PA8) -AFN(LPUART1_CTS, 8, PA6) -AFN(LPUART1_RTS_DE, 8, PB1) -AFN(LPUART1_RX, 8, PA3) -AFN(LPUART1_TX, 8, PA2) -AFN(MCO, 0, PA8) -AFN(NJTRST, 0, PB4) -AFN(QUADSPI_BK1_IO0, 10, PB1) -AFN(QUADSPI_BK1_IO1, 10, PB0) -AFN(QUADSPI_BK1_IO2, 10, PA7) -AFN(QUADSPI_BK1_IO3, 10, PA6) -AFN(QUADSPI_BK1_NCS, 10, PA2) -AFN(QUADSPI_CLK, 10, PA3) -AFN(SAI1_EXTCLK, 13, PA0, 13, PB0) -AFN(SAI1_FS_A, 13, PA9) -AFN(SAI1_FS_B, 13, PA14, 13, PA4, 13, PB6) -AFN(SAI1_MCLK_A, 13, PA3) -AFN(SAI1_MCLK_B, 13, PB4) -AFN(SAI1_SCK_A, 13, PA8) -AFN(SAI1_SCK_B, 13, PB3) -AFN(SAI1_SD_A, 13, PA10) -AFN(SAI1_SD_B, 13, PA13, 13, PB5) -AFN(SPI1_MISO, 5, PA11, 5, PA6, 5, PB4) -AFN(SPI1_MOSI, 5, PA12, 5, PA7, 5, PB5) -AFN(SPI1_NSS, 5, PA15, 5, PA4, 5, PB0) -AFN(SPI1_SCK, 5, PA1, 5, PA5, 5, PB3) -AFN(SPI3_MISO, 6, PB4) -AFN(SPI3_MOSI, 6, PB5) -AFN(SPI3_NSS, 6, PA15, 6, PA4) -AFN(SPI3_SCK, 6, PB3) -AFN(SWPMI1_IO, 12, PA8) -AFN(SWPMI1_RX, 12, PA14) -AFN(SWPMI1_SUSPEND, 12, PA15) -AFN(SWPMI1_TX, 12, PA13) -AFN(TIM15_BKIN, 14, PA9) -AFN(TIM15_CH1, 14, PA2) -AFN(TIM15_CH1N, 14, PA1) -AFN(TIM15_CH2, 14, PA3) -AFN(TIM16_BKIN, 14, PB5) -AFN(TIM16_CH1, 14, PA6) -AFN(TIM16_CH1N, 14, PB6) -AFN(TIM1_BKIN, 1, PA6) -AFN(TIM1_BKIN2, 2, PA11) -AFN(TIM1_BKIN2_COMP1, 12, PA11) -AFN(TIM1_BKIN_COMP2, 12, PA6) -AFN(TIM1_CH1, 1, PA8) -AFN(TIM1_CH1N, 1, PA7) -AFN(TIM1_CH2, 1, PA9) -AFN(TIM1_CH2N, 1, PB0) -AFN(TIM1_CH3, 1, PA10) -AFN(TIM1_CH3N, 1, PB1) -AFN(TIM1_CH4, 1, PA11) -AFN(TIM1_ETR, 1, PA12) -AFN(TIM2_CH1, 1, PA0, 1, PA15, 1, PA5) -AFN(TIM2_CH2, 1, PA1, 1, PB3) -AFN(TIM2_CH3, 1, PA2) -AFN(TIM2_CH4, 1, PA3) -AFN(TIM2_ETR, 14, PA0, 2, PA15, 2, PA5) -AFN(TSC_G2_IO1, 9, PB4) -AFN(TSC_G2_IO2, 9, PB5) -AFN(TSC_G2_IO3, 9, PB6) -AFN(TSC_G2_IO4, 9, PB7) -AFN(TSC_G3_IO1, 9, PA15) -AFN(USART1_CK, 7, PA8, 7, PB5) -AFN(USART1_CTS, 7, PA11, 7, PB4) -AFN(USART1_RTS_DE, 7, PA12, 7, PB3) -AFN(USART1_RX, 7, PA10, 7, PB7) -AFN(USART1_TX, 7, PA9, 7, PB6) -AFN(USART2_CK, 7, PA4) -AFN(USART2_CTS, 7, PA0) -AFN(USART2_RTS_DE, 7, PA1) -AFN(USART2_RX, 3, PA15, 7, PA3) -AFN(USART2_TX, 7, PA2) -AFN(USART3_CK, 7, PB0) -AFN(USART3_CTS, 7, PA6) -AFN(USART3_RTS_DE, 7, PA15, 7, PB1) -AFN(USB_CRS_SYNC, 10, PA10) -AFN(USB_DM, 10, PA11) -AFN(USB_DP, 10, PA12) -AFN(USB_NOE, 10, PA13) diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc b/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc deleted file mode 100644 index 21c7234..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc +++ /dev/null @@ -1,26 +0,0 @@ -PORT(A, 0) -PORT(A, 1) -PORT(A, 2) -PORT(A, 3) -PORT(A, 4) -PORT(A, 5) -PORT(A, 6) -PORT(A, 7) -PORT(A, 8) -PORT(A, 9) -PORT(A, 10) -PORT(A, 11) -PORT(A, 12) -PORT(A, 13) -PORT(A, 14) -PORT(A, 15) -PORT(B, 0) -PORT(B, 1) -PORT(B, 3) -PORT(B, 4) -PORT(B, 5) -PORT(B, 6) -PORT(B, 7) -PORT(C, 14) -PORT(C, 15) -PORT(H, 3) diff --git a/02-usart/include/arch/stm32l4xxx/peripherals/usart.h b/02-usart/include/arch/stm32l4xxx/peripherals/usart.h deleted file mode 100644 index a1542f4..0000000 --- a/02-usart/include/arch/stm32l4xxx/peripherals/usart.h +++ /dev/null @@ -1,204 +0,0 @@ -#ifndef H__USART_ -#define H__USART_ - -#include -#include -#include - -#include "kern/common.h" -#include "arch/stm32l4xxx/peripherals/rcc.h" -#include - -#define USART1 (* (usart_t*) USART1_BASE) -#define USART2 (* (usart_t*) USART2_BASE) - -/* - * Possible USART clock sources. - */ -typedef enum { - USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */ - USART_CLK_SRC_SYSCLK = 1, /* System clock. */ - USART_CLK_SRC_HSI16 = 2, /* 16MHz oscillator. */ - USART_CLK_SRC_LSE = 3 /* Low power 32kHz clock. */ -} usart_clk_src_t; - -typedef struct { - /* USART configuration registers 0x04 - 0x0c. */ -#define usart_ue (1 << 0) /* UART enable */ -#define usart_uesm (1 << 1) /* UART enabled in stop mode. */ -#define usart_re (1 << 2) /* reciever enabled. */ -#define usart_te (1 << 3) /* transmitter enabled. */ -#define usart_idleie (1 << 4) /* Idle interrupt enabled. */ -#define usart_rxneie (1 << 5) /* RXNEIE RXNE interrupt enable. */ -#define usart_tcie (1 << 6) -#define usart_txeie (1 << 7) -#define usart_peie (1 << 8) -#define usart_ps (1 << 9) -#define usart_pce (1 << 10) -#define usart_wake (1 << 11) -#define usart_m0 (1 << 12) -#define usart_mme (1 << 13) -#define usart_cmie (1 << 14) -#define usart_over8 (1 << 15) -#define usart_dedt (0xF << 16) -#define usart_deat (0xF << 21) -#define usart_rtoie (1 << 26) -#define usart_eobie (1 << 27) -#define usart_m1 (1 << 28) - __IO uint32_t c_r1; - __IO uint32_t c_r2; - - -#define usart_eie (1 << 0) // Error interrupt enable. -#define usart_iren (1 << 1) // IrDA mode enabled -#define usart_irlp (1 << 2) // IrDA low power -#define usart_hdsel (1 << 3) // Half duplex selection -#define usart_nack (1 << 4) // Smartcard NACK enable -#define usart_scen (1 << 5) // Smartocard mode enable -#define usart_dmar (1 << 6) // DMA enable reciever -#define usart_dmat (1 << 7) // DMA enable transmitter -#define usart_rtse (1 << 8) // RTS enable -#define usart_ctse (1 << 9) // CTS enable -#define usart_ctsie (1 << 10) // CTS interrupt enable -#define usart_onebit (1 << 11) // One sample bit method enable -#define usart_ovrdis (1 << 12) // Overrun disable -#define usart_ddre (1 << 13) // DMA Disable on reception error -#define usart_dem (1 << 14) // Driver enable mode -#define usart_dep (1 << 15) // Driver enable polarity selection -#define usart_scarcnt0 (1 << 17) -#define usart_scarcnt1 (1 << 18) -#define usart_scarcnt2 (1 << 19) -#define usart_wus0 (1 << 20) // Wakeup from STOP mode interrept flag selection -#define usart_wus1 (1 << 21) // Wakeup from STOP mode interrept flag selection -#define usart_wufie (1 << 22) // Wakeup from STOP mode interrup enable -#define usart_ucesm (1 << 23) // USART clock enable in STOP mode. -#define usart_tcbgtie (1 << 24) // Transmission complete before guard time interrupt - __IO uint32_t c_r3; - - /* USART baud rate register. */ - uint32_t br_r; - uint32_t gtp_r; - uint32_t rto_r; - uint32_t rq_r; - - /* USART ISR register. Offset = 0x1c*/ -#define usart_pe (1 << 0) // Parity error -#define usart_fe (1 << 1) // Framing error -#define usart_nf (1 << 2) // START bit noise detection flag. -#define usart_ore (1 << 3) // Overrun error -#define usart_dlie (1 << 4) // Idle line detected -#define usart_rxne (1 << 5) // Read data register not empty -#define usart_tc (1 << 6) // Transmission complete -#define usart_txe (1 << 7) // Transmit data register empty -#define usart_lbdf (1 << 8) // LIN break detection flag -#define usart_ctsif (1 << 9) // CTS interrupt flag -#define usart_cts (1 << 10) // CTS flag. -#define usart_rtof (1 << 11) // Receiever timeout -#define usart_eobf (1 << 12) // End of block flag -#define usart_abre (1 << 14) // Auto baud rate error -#define usart_abrf (1 << 15) // Auto baud rate flag -#define usart_busy (1 << 16) // Busy flag -#define usart_cmf (1 << 17) // Character match flag -#define usart_sbkf (1 << 18) // send break flag -#define usart_rwu (1 << 19) // receiver wakeup frlom mute mode. -#define usart_wuf (1 << 20) // Wakeup from stop mode flag -#define usart_teack (1 << 21) // Transmit enable acknowledge flag. -#define usart_reack (1 << 22) // Receieve enable acknowledge flag. -#define usart_tcbgt (1 << 25) // Transmission completer before guard time completion. - __IO uint32_t is_r; /* Interrupt service register. */ - -#define usart_pecf (1 << 0) // Parity error clear flag -#define usart_fecf (1 << 1) // Framing error clear flag -#define usart_ncf (1 << 2) // Noise detected clear flag -#define usart_orecf (1 << 3) // Overrun error clear flag -#define usart_idlecf (1 << 4) // Idle line detected clear flag -#define usart_tccf (1 << 6) // Transmission complete clear flag -#define usart_tcbgtcf (1 << 7) // Transmission completed before guard time clear flag -#define usart_lbdcf (1 << 8) // LIN break detection clear flag -#define usart_ctscf (1 << 9) // CTS clear flag -#define usart_rtocf (1 << 11) // Receiver timeout clear flag -#define usart_eobcf (1 << 12) // End of block clear flag -#define usart_cmcf (1 << 17) // Character match clear flag -#define usart_wucf (1 << 20) // Wakeup from Stop mode clear flag. - __IO uint32_t ic_r; - uint32_t rd_r; - uint32_t td_r; -} usart_t; - -static_assert(offsetof(usart_t, ic_r) == 0x20, "Offset assertion failed."); -static_assert(offsetof(usart_t, rd_r) == 0x24, "Offset assertion failed."); - -typedef enum { - OVERSAMPLE_8, - OVERSAMPLE_16 -} oversampling_mode_t; - -static inline void usart_set_divisor( - __IO usart_t* usart, - uint32_t usartdiv) -{ - if (usart->c_r1 & (1 << 15)) { - /* OVER8 is set. */ - usart->br_r = - (usartdiv & ~7) | - ((usartdiv & 7) >> 1); - } else { - /* OVER8 is not set. */ - usart->br_r = usartdiv; - } -} - -static inline void usart_set_oversampling_mode( - __IO usart_t* usart, - oversampling_mode_t mode) -{ - if (mode == OVERSAMPLE_8) { - usart->c_r1 |= 1 << 15; - } else { - usart->c_r1 &= ~(1 << 15); - } -} - -typedef enum { - USART_PARITY_DISABLED = 0, - USART_PARITY_EVEN = 2 << 9, - USART_PARITY_ODD = 3 << 9, -} usart_parity_t; - -typedef enum { - USART_ENABLE_TX = 0x02, - USART_ENABLE_RX = 0x01, - USART_ENABLE_DISABLED = 0x00, -} usart_enable_t; - -void usart_set_parity(__IO usart_t* usart, usart_parity_t parity); - -void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled); - -void usart_enable_dma(__IO usart_t* usart, usart_enable_t enabled); - -/* - * Send a byte on the usart, This command blocks until the data - * is fully sent. - */ -void usart_transmit_byte_sync(__IO usart_t* usart, uint8_t byte); - -void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); - -void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable); - -void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); - -void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable); - -void usart_transmit_bytes_sync( - __IO usart_t* usart, const uint8_t* bytes, uint32_t n); - -void usart_transmit_str_sync(__IO usart_t* usart, const char* str); - -void usart_printf(__IO usart_t* usart, const char* fmt, ...); - -void usart_vprintf(__IO usart_t* usart, const char* fmt, va_list l); - - -#endif /* H__USART_ */ diff --git a/02-usart/include/arch/x86_64/arch.h b/02-usart/include/arch/x86_64/arch.h deleted file mode 100644 index c17721d..0000000 --- a/02-usart/include/arch/x86_64/arch.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef ARCH_H_ -#define ARCH_H_ - -#include "fake_env.h" - -#define ARCH_PC -#define enable_all_interrupts() do {} while(0) - -#define RCC_BASE (load_fake_rcc__()) - -#define DMA1_BASE (load_fake_ahb1__() + 0x0) -#define DMA2_BASE (load_fake_ahb1__() + 0x400) - -#define USART1_BASE (load_fake_apb2__() + 0x3800) -#define USART2_BASE (load_fake_apb1__() + 0x4400) - -#define GPIOA_BASE (load_fake_ahb2__() + 0x0) -#define GPIOB_BASE (load_fake_ahb2__() + 0x400) -#define GPIOC_BASE (load_fake_ahb2__() + 0x800) -#define GPIOH_BASE (load_fake_ahb2__() + 0x1C00) - -#define SRAM1_BASE (load_fake_sram1__() + 0x0) -#define SRAM2_BASE (load_fake_sram2__() + 0x0) - -#define SYSTEM_CONFIG_BLOCK_BASE (load_fake_scb__()) -#define NVIC_BASE (load_fake_nvic__()) - -#define SPI1_BASE (load_fake_spi1__()) -#define SPI3_BASE (load_fake_spi3__()) - -// Pretend there's a data segement at the start of SRAM1 for more accurate -// testing. -#define GHOST_DATA_SEGMENT_SIZE 1234 -#define DATA_SEGMENT_START (*((uint8_t*)SRAM1_BASE)) -#define DATA_SEGMENT_STOP (*(((uint8_t*)SRAM1_BASE) + GHOST_DATA_SEGMENT_SIZE)) - -#endif /* ARCH_H_ */ diff --git a/02-usart/include/kern/common.h b/02-usart/include/kern/common.h deleted file mode 100644 index 653279e..0000000 --- a/02-usart/include/kern/common.h +++ /dev/null @@ -1,50 +0,0 @@ -#ifndef COMMON__H -#define COMMON__H - -#include -#include -#include - -#define WEAK __attribute__((weak)) -#define NORETURN __attribute__((noreturn)) - -#ifndef static_assert -#define static_assert(a, b) -#endif - -/* Define __IO to be volatile if it's not already. */ -#ifndef __IO -#define __IO volatile -#endif - -#define CTZ(n) __builtin_ctz(n) - -#define bool int -#ifndef __cplusplus -#define true 1 -#define false 0 -#endif - -#define PACKED __attribute__((packed)) -#define BIT(n) (1 << (n)) - -#define RESERVED_CONCAT_IMPL(x, y) x ## y -#define RESERVED_MACRO_CONCAT(x, y) RESERVED_CONCAT_IMPL(x, y) -#define RESERVED(n) \ - bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) :n - -#define RESERVE(type) \ - __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__) - -#define ptr2reg(ptr) \ - ((uint32_t) (ptrdiff_t) (ptr)) - -typedef __IO uint32_t bits_t; - -#define regset(reg, mask, val) \ - ((reg) = ((reg) & ~mask) | (val << CTZ(mask))) - -#define regget(reg, mask) \ - (((reg) & mask) >> (CTZ(mask))) - -#endif /* COMMON_H */ diff --git a/02-usart/include/kern/delay.h b/02-usart/include/kern/delay.h deleted file mode 100644 index 65a26d6..0000000 --- a/02-usart/include/kern/delay.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef H__DELAY__ -#define H__DELAY__ - -#include - -/* - * Loops and count-downs the delay, the time this takes depends on the speed - * of the clock. - */ -void delay(uint32_t delay); - -#endif /* H__DELAY__ */ diff --git a/02-usart/include/kern/dma/dma_manager.h b/02-usart/include/kern/dma/dma_manager.h deleted file mode 100644 index 0d17bd5..0000000 --- a/02-usart/include/kern/dma/dma_manager.h +++ /dev/null @@ -1,279 +0,0 @@ -#ifndef PERI_DMA_H_ -#define PERI_DMA_H_ - -#include "kern/common.h" -#include "arch/stm32l4xxx/peripherals/dma.h" /* Access to the DMA registers. */ -#include "arch/stm32l4xxx/peripherals/irq.h" - -#define DMA_ERROR_CHANNEL_IN_USE 1 - -#define CAT2(x, y) x ## y -#define CAT1(v, c) CAT2(v, c) -#define DMA_RESERVED(dma) CAT1(dma ## _PERIPH_RESERVED, __COUNTER__) - -#define ALTERNATE0 0x0000 -#define ALTERNATE1 0x0100 -#define ALTERNATE2 0x0200 -#define ALTERNATE3 0x0300 - -#define DMA_N_CHANNELS 7 -typedef enum { - DMA1_PERIPH_ADC1 = 0, - DMA1_PERIPH_ADC2 = 1, - DMA1_PERIPH_ADC3 = 2, - DMA1_PERIPH_DFSDM1_FLT0 = 3, - DMA1_PERIPH_DFSDM1_FLT1 = 4, - DMA1_PERIPH_DFSDM1_FLT2 = 5, - DMA1_PERIPH_DFSDM1_FLT3 = 6, - - DMA_RESERVED(DMA1) = 7, - DMA1_PERIPH_SPI1_RX = 8, - DMA1_PERIPH_SPI1_TX = 9, - DMA1_PERIPH_SPI2_RX = 10, - DMA1_PERIPH_SPI2_TX = 11, - DMA1_PERIPH_SAI2_A = 12, - DMA1_PERIPH_SAI2_B = 13, - - DMA_RESERVED(DMA1) = 14, - DMA1_PERIPH_USART3_TX = 15, - DMA1_PERIPH_USART3_RX = 16, - DMA1_PERIPH_USART1_TX = 17, - DMA1_PERIPH_USART1_RX = 18, - DMA1_PERIPH_USART2_RX = 19, - DMA1_PERIPH_USART2_TX = 20, - - DMA_RESERVED(DMA1) = 21, - DMA1_PERIPH_I2C3_TX = 22, - DMA1_PERIPH_I2C3_RX = 23, - DMA1_PERIPH_I2C2_TX = 24, - DMA1_PERIPH_I2C2_RX = 25, - DMA1_PERIPH_I2C1_TX = 26, - DMA1_PERIPH_I2C1_RX = 27, - - DMA1_PERIPH_TIM2_CH3 = 28, - DMA1_PERIPH_TIM2_UP = 29, - DMA1_PERIPH_TIM16_CH1_1 = 30 | ALTERNATE0, - DMA1_PERIPH_TIM16_UP_1 = 30 | ALTERNATE1, /* Same as TIM16_CH1. */ - DMA_RESERVED(DMA1) = 31, - DMA1_PERIPH_TIM2_CH1 = 32, - DMA1_PERIPH_TIM16_CH1_2 = 33, - DMA1_PERIPH_TIM16_UP_2 = 33 | ALTERNATE1, /* Same as TIM16_CH1. */ - DMA1_PERIPH_TIM2_CH2 = 34, - DMA1_PERIPH_TIM2_CH4 = 34 | ALTERNATE1, /* Same as TIM2_CH2. */ - - - DMA1_PERIPH_TIM17_CH1_1 = 35, - DMA1_PERIPH_TIM17_UP_1 = 35 | ALTERNATE1, /* Same as TIM17_CH1 */ - DMA1_PERIPH_TIM3_CH3 = 36, - DMA1_PERIPH_TIM3_CH4 = 37, - DMA1_PERIPH_TIM3_UP = 37 | ALTERNATE1, /* Same as TIM3_CH4 */ - DMA1_PERIPH_TIM7_UP = 38, - DMA1_PERIPH_DAC_CH2 = 38 | ALTERNATE1, /* Same as TIM7_UP */ - DMA1_PERIPH_QUADSPI = 39, - DMA1_PERIPH_TIM3_CH1 = 40, - DMA1_PERIPH_TIM3_TRIG = 40 | ALTERNATE1, /* Same as TIM3_CH1 */ - DMA1_PERIPH_TIM17_CH1_2 = 41, - DMA1_PERIPH_TIM17_UP_2 = 41 | ALTERNATE1, /* Same as TIM17_CH1 */ - - DMA1_PERIPH_TIM4_CH1 = 42, - DMA_RESERVED(DMA1) = 43, - DMA1_PERIPH_TIM6_UP = 44, - DMA1_PERIPH_DAC_CH1 = 44 | ALTERNATE1, /* Same as TIM6_UP */ - DMA1_PERIPH_TIM4_CH2 = 45, - DMA1_PERIPH_TIM4_CH3 = 46, - DMA_RESERVED(DMA1) = 47, - DMA1_PERIPH_TIM4_UP = 48, - - DMA_DMA1_PERIHP_RESERVED5 = 49, - DMA1_PERIPH_TIM1_CH1 = 50, - DMA1_PERIPH_TIM1_CH2 = 51, - DMA1_PERIPH_TIM1_CH4 = 52, - DMA1_PERIPH_TIM1_TRIG = 52 | ALTERNATE1, /* Same as TIM1_TRIG */ - DMA1_PERIPH_TIM1_COM = 52 | ALTERNATE2, /* Same as TIM1_TRIG */ - DMA1_PERIPH_TIM15_CH1 = 53, - DMA1_PERIPH_TIM15_UP = 53 | ALTERNATE1, /* Same as TIM15_CH1 */ - DMA1_PERIPH_TIM15_TRIG = 53 | ALTERNATE2, /* Same as TIM15_CH1 */ - DMA1_PERIPH_TIM15_COM = 53 | ALTERNATE3, /* Same as TIM15_CH1 */ - DMA1_PERIPH_TIM1_UP = 54, - DMA1_PERIPH_TIM1_CH3 = 55, - - DMA2_DMA1_SWITCH__ = 56, - - DMA2_PERIPH_I2C4_RX = 56, - DMA2_PERIPH_I2C4_TX = 57, - DMA2_PERIPH_ADC1 = 58, - DMA2_PERIPH_ADC2 = 59, - DMA2_PERIPH_ADC3 = 60, - DMA2_PERIPH_DCMI_1 = 61, - DMA_RESERVED(DMA2) = 62, - - DMA2_PERIPH_SAI1_A_1 = 63, - DMA2_PERIPH_SAI1_B_1 = 64, - DMA2_PERIPH_SAI2_A = 65, - DMA2_PERIPH_SAI2_B = 66, - DMA_RESERVED(DMA2) = 67, - DMA2_PERIPH_SAI1_A_2 = 68, - DMA2_PERIPH_SAI1_B_2 = 69, - - DMA2_PERIPH_UART5_TX = 70, - DMA2_PERIPH_UART5_RX = 71, - DMA2_PERIPH_UART4_TX = 72, - DMA_RESERVED(DMA2) = 73, - DMA2_PERIPH_UART4_RX = 74, - DMA2_PERIPH_USART1_TX = 75, - DMA2_PERIPH_USART1_RX = 76, - - DMA2_PERIPH_SPI3_RX = 77, - DMA2_PERIPH_SPI3_TX = 78, - DMA_RESERVED(DMA2) = 79, - DMA2_PERIPH_TIM6_UP = 80, - DMA2_PERIPH_DAC_CH1 = 80 | ALTERNATE1, /* Same as TIM6_UP */ - DMA2_PERIPH_TIM7_UP = 81, - DMA2_PERIPH_DAC_CH2 = 81 | ALTERNATE1, /* Same as TIM7_UP */ - DMA_RESERVED(DMA2) = 82, - DMA2_PERIPH_QUADSPI = 83, - - DMA2_PERIPH_SWPMI1_RX = 84, - DMA2_PERIPH_SWPMI1_TX = 85, - DMA2_PERIPH_SPI1_RX = 86, - DMA2_PERIPH_SPI1_TX = 87, - DMA2_PERIPH_DCMI_2 = 88, - DMA2_PERIPH_LPUART1_TX = 89, - DMA2_PERIPH_LPUART1_RX = 90, - - - DMA2_PERIPH_TIM5_CH4 = 91, - DMA2_PERIPH_TIM5_TRIG = 91 | ALTERNATE1, /* Same as TIM5_CH4 */ - DMA2_PERIPH_TIM5_CH3 = 92, - DMA2_PERIPH_TIM5_UP = 92 | ALTERNATE1, /* Same as TIM5_CH3 */ - DMA_RESERVED(DMA2) = 93, - DMA2_PERIPH_TIM5_CH2 = 94, - DMA2_PERIPH_TIM5_CH1 = 95, - DMA2_PERIPH_I2C1_RX = 96, - DMA2_PERIPH_I2C1_TX = 97, - - DMA2_PERIPH_AES_IN_1 = 98, - DMA2_PERIPH_AES_OUT_1 = 99, - DMA2_PERIPH_AES_OUT_2 = 100, - DMA_RESERVED(DMA2) = 101, - DMA2_PERIPH_AES_IN_2 = 102, - DMA_RESERVED(DMA2) = 103, - DMA2_PERIPH_HASH_IN = 104, - - DMA2_PERIPH_TIM8_CH3 = 105, - DMA2_PERIPH_TIM8_UP = 105 | ALTERNATE1, /* Same as TIM8_CH3 */ - DMA2_PERIPH_TIM8_CH4 = 106, - DMA2_PERIPH_TIM8_TRIG = 106 | ALTERNATE1, /* Same as TIM8_CH4 */ - DMA2_PERIPH_TIM8_COM = 106 | ALTERNATE2, /* Same as TIM8_CH4 */ - DMA_RESERVED(DMA2) = 107, - DMA2_PERIPH_SDMMC1_1 = 108, - DMA2_PERIPH_SDMMC1_2 = 109, - DMA2_PERIPH_TIM8_CH1 = 110, - DMA2_PERIPH_TIM8_CH2 = 111, - - - DMA_PERIPH_SENTINEL, -} dma_peripheral_t; - - -/* Defines a DMA channel. */ -typedef struct { - uint8_t dma; /* 0 = DMA1, 1 = DMA2 */ - uint8_t chan; /* 0 - 6 */ -} dma_channel_t; - - -/* - * Defines a DMA channel allocated for memory-to-peripheral transfers. This - * structure is only nominally different from dma_channel_t in order to provide - * rudimentary type-checking. - */ -typedef struct { - dma_channel_t c_; -} dma_mem2p_channel_t; - -/* - * Defines a DMA channel allocated for peripheral-to-memory transfers. This - * structure is only nominally different from dma_channel_t in order to provide - * rudimentary type-checking. - */ -typedef struct { - dma_channel_t c_; -} dma_p2mem_channel_t; - -/* Defines a DMA channel allocated for mem2mem transfers. - * This structure is only nominally different from dma_channel_t - * in order to provide rudimentary type-checking. - */ -typedef struct { - dma_channel_t c_; -} dma_mem2mem_channel_t; - -#define DMA_CHAN_ERROR ((dma_channel_t) { .dma = 0xff, .chan = 0xff }) - -typedef struct { - bool transfer_complete_interrupt_enable; - bool half_transfer_interrupt_enable; - bool transfer_error_interrupt_enable; - - bool circular_mode; - bool peripheral_increment; - bool memory_increment; - - dma_size_t peripheral_block_size; - dma_size_t memory_block_size; - - dma_priority_level_t priority; -} dma_opts_t; - -#define DEFAULT_DMA_OPTS \ - ((dma_opts_t) { .memory_increment = 1, \ - .peripheral_increment = 0, \ - .transfer_complete_interrupt_enable = 0, \ - .half_transfer_interrupt_enable = 0, \ - .transfer_error_interrupt_enable = 0, \ - .circular_mode = 0, \ - .peripheral_block_size = DMA_SIZE_8_BITS, \ - .memory_block_size = DMA_SIZE_8_BITS, \ - .priority = DMA_PRIORITY_LEVEL_MEDIUM }) - -dma_p2mem_channel_t select_dma_channel_p2mem( - dma_peripheral_t peripheral, - dma_opts_t* opts_in, - int* error); - -dma_mem2p_channel_t select_dma_channel_mem2p( - dma_peripheral_t peripheral, - dma_opts_t* opts_in, - int* error); - -/* Returns a dma channel used for memory-to-memory transfers. - * - * channel - the channel this dma should use. The channel should - * be on the range [0-13]. The channels [0-6] refer to the 7 channels - * on DMA1, where channels [7-13] refer to the 7 channels on DMA2. - * - * If `channel` is -1, then the highest unused dma channel is selected. - */ -dma_mem2mem_channel_t select_dma_channel_mem2mem( - int channel, - dma_opts_t* opts, - int* error_out); - -void dma_mem2p_initiate_transfer( - dma_mem2p_channel_t chan, const void* from_loc, uint16_t nblocks); - -void dma_p2mem_initiate_transfer( - dma_p2mem_channel_t chan, void* to_loc, uint16_t nblocks); - -void dma_mem2mem_initiate_transfer( - dma_mem2mem_channel_t chan, - void* to_loc, - const void* from_loc, - uint16_t nblocks); - -void release_dma_channel(dma_channel_t chan); - -interrupt_t dma_channel_get_interrupt(dma_channel_t chan); - -#endif diff --git a/02-usart/include/kern/gpio/gpio_manager.h b/02-usart/include/kern/gpio/gpio_manager.h deleted file mode 100644 index 922a423..0000000 --- a/02-usart/include/kern/gpio/gpio_manager.h +++ /dev/null @@ -1,187 +0,0 @@ -#ifndef KERN_GPIO_GPIO_MANAGE_H_ -#define KERN_GPIO_GPIO_MANAGE_H_ - -#include "kern/common.h" -#include "arch/stm32l4xxx/peripherals/gpio.h" - -#define GPIO_ERROR_IN_USE 1 -#define GPIO_ERROR_INVALID_PIN_FOR_ALTERNATE_FUNCTION 2 -#define GPIO_ERROR_INVALID_PIN 3 - -typedef enum { -/* Creates vaules GPIO_PIN_ i.e. GPIO_PIN_A0 */ -#define PORT(p, pn) \ - GPIO_PIN_P ## p ## pn, -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" -#undef PORT - - N_GPIO_PINS -} gpio_pin_t; - -/* Alternate functions. */ -typedef enum { -#define AFN(fn, ...) \ - GPIO_ALTERNATE_FUNCTION_ ## fn, -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc" -#undef AFN - GPIO_ALTERNATE_FUNCTION_EVENTOUT, -} gpio_alternate_function_t; - -#define gpio_pin_for_alternate_function(af) ((af) / 16) -#define gpio_pin_out_of_range(pin) \ - ((pin) < 0 || (pin) >= N_GPIO_PINS) - -typedef enum { - GPIO_PORT_A, - GPIO_PORT_B, - GPIO_PORT_C, - GPIO_PORT_D, - GPIO_PORT_E, - GPIO_PORT_F, - GPIO_PORT_G, - GPIO_PORT_H, - GPIO_PORT_I, - - N_GPIO_PORTS, -} gpio_port_t; - -typedef enum { - GPIO_MODE_INPUT, - GPIO_MODE_OUTPUT, - GPIO_MODE_ALTERNATE, - GPIO_MODE_ANALOG -} gpio_mode_t; - -/* - * Enum defining the pin speeds that are possible. - */ -typedef enum { - SPEED_2MHZ = 0, - SPEED_10MHZ = 1, - SPEED_50MHZ = 3, -} gpio_speed_t; - -typedef enum { - GPIO_OUTPUT_TYPE_PUSH_PULL, - GPIO_OUTPUT_TYPE_OPEN_DRAIN -} gpio_output_type_t; - -typedef enum { - GPIO_OUTPUT_SPEED_LOW, - GPIO_OUTPUT_SPEED_MEDIUM, - GPIO_OUTPUT_SPEED_HIGH, - GPIO_OUTPUT_SPEED_VERY_HIGH, -} gpio_output_speed_t; - -typedef enum { - GPIO_PULL_DIR_NONE, - GPIO_PULL_DIR_UP, - GPIO_PULL_DIR_DOWN, -} gpio_pull_dir_t; - -/* Returns the appropriate gpio_port for the provided pin. */ -inline static gpio_port_t get_port_for_pin(gpio_pin_t pin) -{ - switch (pin) { -#define PORT(p, pn) \ - case GPIO_PIN_P ## p ## pn: return GPIO_PORT_ ## p; -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" -#undef PORT - case N_GPIO_PINS: return N_GPIO_PORTS; - } - - /* Should be unreachable. */ -} - -#define DEFAULT_GPIO_OPTS_OUTPUT \ - (gpio_pin_opts_t) { \ - .mode = GPIO_MODE_OUTPUT, \ - .pull_dir = GPIO_PULL_DIR_DOWN, \ - .output_opts.speed = GPIO_OUTPUT_SPEED_MEDIUM, \ - .output_opts.type = GPIO_OUTPUT_TYPE_PUSH_PULL, \ - } - -#define DEFAULT_GPIO_OPTS_INPUT \ - (gpio_pin_opts_t) { \ - .mode = GPIO_MODE_OUTPUT, \ - .pull_dir = GPIO_PULL_DIR_DOWN, \ - } - -typedef struct { - gpio_mode_t mode; - gpio_pull_dir_t pull_dir; - - union { - struct { - } input_opts; - - struct { - gpio_output_speed_t speed; - gpio_output_type_t type; - } output_opts; - - struct { - uint8_t function; - } alternate_opts; - - struct { - } analog_opts; - }; -} gpio_pin_opts_t; - -/* Differentiates at compile-time from the a gpio_pin_t enum value and a pin - * that's been reserved. */ -typedef struct { - gpio_pin_t v_; -} gpio_reserved_pin_t; - -/* Returns a pointer to the GPIO pin bus and offset. This is useful for when - * raw access to the values are needed. I.e. time critical applications. */ -void get_gpio_pin_port_off( - gpio_pin_t pin, gpio_port_config_t** out_cfg, int* out_off); - -/* Sets the given GPIO pin to high. */ -void set_gpio_pin_high(gpio_reserved_pin_t pin); - -/* Sets the given GPIO pin to low. */ -void set_gpio_pin_low(gpio_reserved_pin_t pin); - -/** returns true if a GPIO pin is in use. */ -bool gpio_pin_in_use(gpio_pin_t pin); - -/* - * Reserve the provided GPIO pin using the opts provided. - * - * sets error_out to GPIO_ERROR_IN_USE if the GPIO pin could not be reserved - * because it already has been reserved. - * - * The function will automatically enable the correct GPIO port bus. - */ -gpio_reserved_pin_t reserve_gpio_pin( - gpio_pin_t pin, gpio_pin_opts_t* opts, int* error_out); - -/* Enables and returns the pin reserved for the alternate function. - * - * If the `hint` parameter is defined (non -1) the manager will try - * to reserve that pin for the alternate function and fail if it can't. - * - * If `hint` is -1 then the first available pin for that alternate function - * will be reserved and returned. - * - * - */ -gpio_reserved_pin_t gpio_enable_alternate_function( - gpio_alternate_function_t fn, - gpio_pin_t hint, - int* error_out); - -/* - * Releases the GPIO pin so it can be reserved again in the future. - * - * The pin is reset during this process and if there are no more reserved pins - * on the corresponding port this function will disable the port. (last one out - * gets the lights.). - */ -void release_gpio_pin(gpio_reserved_pin_t gpio_pin); - -#endif /* KERN_GPIO_GPIO_MANAGE_H_ */ diff --git a/02-usart/include/kern/gpio/sysled.h b/02-usart/include/kern/gpio/sysled.h deleted file mode 100644 index b2c9056..0000000 --- a/02-usart/include/kern/gpio/sysled.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Headers for interacting and managing the system LED. - */ -#ifndef SYSLED_H_ -#define SYSLED_H_ - -#include "kern/gpio/gpio_manager.h" - -gpio_reserved_pin_t get_sysled(); - -#endif diff --git a/02-usart/include/kern/init.h b/02-usart/include/kern/init.h deleted file mode 100644 index 737b85f..0000000 --- a/02-usart/include/kern/init.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef INIT_H_ -#define INIT_H_ - -/** Globals annotated with _no_init will not be set during init1 bootup - * where the data segement is loaded from flash and the bss segment is - * cleared. - * - * This is useful for routines that run in the init0 boot procedure - * that need persistent globals. - * - * Note that initializing a global annotated with _no_init will have - * no effect as the variable will remain uninitialized until explicitly - * set by by the program. - */ -#define _no_init \ - __attribute((__section__(".noinit"))) - -#define init0 \ - static void init0fn(); \ - static __attribute((__section__(".init0"))) \ - __attribute((__used__)) \ - void(*init0_ptr)() = init0fn; \ - static void init0fn -#define init1 \ - static void init1fn(); \ - static __attribute((__section__(".init1"))) \ - __attribute((__used__)) \ - void(*init1_ptr)() = init1fn; \ - static void init1fn -#define init2 \ - static void init2fn(); \ - static __attribute((__section__(".init2"))) \ - __attribute((__used__)) \ - void(*init2_ptr)() = init2fn; \ - static void init2fn -#define init3 \ - static void init3fn(); \ - static __attribute((__section__(".init3"))) \ - __attribute((__used__)) \ - void(*init3_ptr)() = init3fn; \ - static void init3fn -#define init4 \ - static void init4fn(); \ - static __attribute((__section__(".init4"))) \ - __attribute((__used__)) \ - void(*init4_ptr)() = init4fn; \ - static void init4fn -#define init5 \ - static void init5fn(); \ - static __attribute((__section__(".init5"))) \ - __attribute((__used__)) \ - void(*init5_ptr)() = init5fn; \ - static void init5fn -#define init6 \ - static void init6fn(); \ - static __attribute((__section__(".init6"))) \ - __attribute((__used__)) \ - void(*init6_ptr)() = init6fn; \ - static void init6fn -#define init7 \ - static void init7fn(); \ - static __attribute((__section__(".init7"))) \ - __attribute((__used__)) \ - void(*init7_ptr)() = init7fn; \ - static void init7fn - -#endif /* INIT_H_ */ diff --git a/02-usart/include/kern/lib.h b/02-usart/include/kern/lib.h deleted file mode 100644 index be0e8e9..0000000 --- a/02-usart/include/kern/lib.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef LIB_H_ -#define LIB_H_ - -#include - -void hexify(uint32_t v, char* into); - -void decimalify(int v, char* into); - -#endif diff --git a/02-usart/include/kern/log.h b/02-usart/include/kern/log.h deleted file mode 100644 index 5e49def..0000000 --- a/02-usart/include/kern/log.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef LOG_H_ -#define LOG_H_ - -/* - * Defines logging capabilities. This logging unit will enable logging on - * the systems main USART output. - */ - -/** Similar to fprintf, but with a stripped-down format-string DSL. */ -void klogf(const char* fmt, ...); - -#endif diff --git a/02-usart/include/kern/mem.h b/02-usart/include/kern/mem.h deleted file mode 100644 index c0999f5..0000000 --- a/02-usart/include/kern/mem.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef MEM_H_ -#define MEM_H_ - -#include "arch.h" -#include - -#define DATA_SEGMENT_STOP_ADDR ((uint8_t*) &DATA_SEGMENT_STOP) -#define DATA_SEGMENT_START_ADDR ((uint8_t*) &DATA_SEGMENT_START) - -#define MAX_HEAP_SIZE \ - ((16384 - (DATA_SEGMENT_STOP_ADDR - DATA_SEGMENT_START_ADDR)) / 4 * 4) - -/* allocates memory on the head, which is stored in sram2 */ -void* halloc(size_t n); - -/* Frees the memory allocated by halloc. */ -void hfree(void* mem); - -#ifdef FOR_TESTING - -void* debug_halloc_get_next_ptr(void* ptr); - -void* debug_halloc_get_prev_ptr(void* ptr); - -int debug_halloc_assert_consistency(char* error, size_t len); - -void debug_print_blocks(); - -#endif - - -#endif diff --git a/02-usart/include/kern/string.h b/02-usart/include/kern/string.h deleted file mode 100644 index 3c9f0b4..0000000 --- a/02-usart/include/kern/string.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef STRING_H_ -#define STRING_H_ - -void kstrcpy(char* into, const char* from); - -#endif /* STRING_H_ */ diff --git a/02-usart/linker/linker_script.ld b/02-usart/linker/linker_script.ld deleted file mode 100644 index 9a9f5b3..0000000 --- a/02-usart/linker/linker_script.ld +++ /dev/null @@ -1,55 +0,0 @@ -MEMORY -{ - flash : org = 0x08000000, len = 256k - sram1 : org = 0x20000000, len = 48k - sram2 : org = 0x10000000, len = 16k -} - -SECTIONS -{ - /* This is where the code goes. */ - . = ORIGIN(flash); - .text : { - *(.vectors); /* All .vector sections go here. */ - *(.text); /* All .text sections go here. */ - } >flash - - .data : { - /* Data segment as defined in the flash. */ - INIT_DATA_VALUES = LOADADDR(.data); - - /* Data segment where it will be in memory. */ - DATA_SEGMENT_START = .; - *(.data); - DATA_SEGMENT_STOP = .; - - INIT_ROUTINES_FLASH_START = - LOADADDR(.data) + (DATA_SEGMENT_STOP - DATA_SEGMENT_START); - - INITS_START = .; - *(.init0); - *(.init1); - *(.init2); - *(.init3); - *(.init4); - *(.init5); - *(.init6); - *(.init7); - INITS_END = .; - - INIT_ROUTINES_FLASH_STOP = - LOADADDR(.data) + (INITS_END - DATA_SEGMENT_START); - - /* Align by 4 so we can optimize the copier to use uint32's. */ - . = ALIGN(0x04); - - *(.noinit); - } >sram1 AT>flash - - BSS_START = .; - .bss : { - *(.bss); - . = ALIGN(0x04); - } > sram1 - BSS_END = .; -} diff --git a/02-usart/src/arch/stm32l4xxx/peripherals/clock.c b/02-usart/src/arch/stm32l4xxx/peripherals/clock.c deleted file mode 100644 index 9051572..0000000 --- a/02-usart/src/arch/stm32l4xxx/peripherals/clock.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file sets the system clock to its full glory of 80Mhz - */ - -#include "arch/stm32l4xxx/peripherals/clock.h" -#include "arch/stm32l4xxx/peripherals/flash.h" - -#include "kern/init.h" - -#include - -#define TIMEOUT 10000 - - -int pll_off() -{ - uint32_t c; - - RCC.c_r &= ~BIT(24); /* Turn off pll. */ - for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c) - ; /* Wait for OFF. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int pll_on() -{ - uint32_t c; - - RCC.c_r |= BIT(24); /* Turn on PLL. */ - for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c) - ; /* Wait for RDY. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */) -{ - if (RCC.c_r & BIT(25)) { - /* PLL must be off to configure it. */ - return E_NOT_OFF; - } - - /* Make sure inputs are valid. */ - if (pllp_div_factor == 1 || pllp_div_factor > 31) { - return E_BADPLLP_DIV; - } - if (plln < 8 || plln > 86) { - return E_BADPLLN; - } - - RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | - (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); - - return 0; -} - -static _no_init uint8_t clock_mHz; -uint8_t get_clock_mhz() -{ - return clock_mHz; -} - -int set_system_clock_MHz(uint8_t mhz) -{ - clock_mHz = mhz; - - /* Set the source of the system colck to MSI temporarily. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_MSI); - - if (mhz <= 8 || mhz > 80) { - return E_BAD_ARG; - } - - pll_off(); - - configure_pll( - 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, - PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, - - /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. - */ - mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, - PLL_SRC_MSI /* pll src | 04 Mhz */); - - pll_on(); - - /* Configure the flash to have 4 wait states. This is required at - * 80 MHz. */ - FLASH.ac_r &= ~0x07; - FLASH.ac_r |= 0x04; - - /* Set the source of the system colck to PLL. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_PLL); - return 0; -} - -int set_system_clock_src(system_clock_src_t src) -{ - uint8_t value = RCC.cfg_r & ~0x03; - RCC.cfg_r = value | src; - return 0; -} diff --git a/02-usart/src/arch/stm32l4xxx/peripherals/irq.c b/02-usart/src/arch/stm32l4xxx/peripherals/irq.c deleted file mode 100644 index 364b9a7..0000000 --- a/02-usart/src/arch/stm32l4xxx/peripherals/irq.c +++ /dev/null @@ -1,96 +0,0 @@ -#include "arch/stm32l4xxx/peripherals/irq.h" -#include "arch/stm32l4xxx/peripherals/gpio.h" -#include "arch/stm32l4xxx/peripherals/nvic.h" - -#include "arch.h" -#include "kern/delay.h" -#include "kern/gpio/gpio_manager.h" - -#define IRQ_RESERVED(n) -#define IRQ(name, uname_, n) \ - void WEAK name () { \ - unhandled_isr(n); \ - } -#include "arch/stm32l4xxx/peripherals/isrs.inc" -#undef IRQ_RESERVED -#undef IRQ - -void isr_simple_pin_on() -{ - int ec; - gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; - gpio_reserved_pin_t pin3 = reserve_gpio_pin(GPIO_PIN_PB3, &opts, &ec); - - set_gpio_pin_high(pin3); -} - -#define IRQ_RESERVED(n) 0, -#define IRQ(name, uname_, n) name, -const void* vectors[] __attribute__((section(".vectors"))) = { - (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ -#include "arch/stm32l4xxx/peripherals/isrs.inc" -}; -#undef IRQ_RESERVED -#undef IRQ - -/* Encodes the provided number as a series of flashes on the on-board - * LED. The flashes follow as such: - * - * Before the bits of the code are flashed, a rapid succession of 20 flashes - * followed by a pause will occur indicating that the next 8 flashes indicate - * the bits of the provided code. - * - * Eoch of the next eight flashes indicate either a 1 or 0 depending on the - * length of flash. The first flash is the least-significant bit, the next the - * second least, the third third least, etc. - * - * - A quick flash followed by a long pause indicates a 0 bit. - * - A "long" flash followed by a equally long pause indicates a 1 bit. - */ -void unhandled_isr(uint8_t number) -{ - int ec; - gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; - gpio_reserved_pin_t pin3 = reserve_gpio_pin(GPIO_PIN_PB3, &opts, &ec); - - for (;;) { - for (int i = 0; i < 20; ++ i) { - set_gpio_pin_high(pin3); - delay(1000000); - set_gpio_pin_low(pin3); - delay(1000000); - } - delay(50000000); - - int n = number; - for (int i = 0; i < 8; ++ i) { - if (n & 1) { - // LSB is a 1 - set_gpio_pin_high(pin3); - delay(15000000); - set_gpio_pin_low(pin3); - delay(15000000); - } else { - // LSB is a 0 - set_gpio_pin_high(pin3); - delay(1000000); - set_gpio_pin_low(pin3); - delay(29000000); - } - - n >>= 1; - } - } -} - -void enable_interrupts(interrupt_set_t* interrupts) -{ - for (int i = 0; i < sizeof(NVIC.ise_r) / sizeof(uint32_t); ++ i) - NVIC.ise_r[i] = interrupts->irqs[i]; -} - -void disable_interrupts(interrupt_set_t* interrupts) -{ - for (int i = 0; i < sizeof(NVIC.ise_r) / sizeof(uint32_t); ++ i) - NVIC.ice_r[i] = interrupts->irqs[i]; -} diff --git a/02-usart/src/arch/stm32l4xxx/peripherals/usart.c b/02-usart/src/arch/stm32l4xxx/peripherals/usart.c deleted file mode 100644 index 7309b48..0000000 --- a/02-usart/src/arch/stm32l4xxx/peripherals/usart.c +++ /dev/null @@ -1,152 +0,0 @@ -#include "arch/stm32l4xxx/peripherals/usart.h" -#include "kern/delay.h" -#include "kern/lib.h" -#include - -void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) -{ - rcc->ccip_r = (rcc->ccip_r & (~0x03)) | usart_clk_src; -} - -void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) -{ - rcc->ccip_r = (rcc->ccip_r & ~(0x03 << 2)) | (usart_clk_src << 2); -} - -void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable) -{ - if (enable) { - rcc->apb1en1_r |= BIT(17); - } else { - rcc->apb1en1_r &= ~BIT(17); - } -} - -void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable) -{ - if (enable) { - rcc->apb2en_r |= BIT(14); - } else { - rcc->apb2en_r &= ~BIT(14); - } -} - -void usart_set_parity(__IO usart_t* usart, usart_parity_t parity) -{ - uint32_t c_r1 = usart->c_r1; - c_r1 &= ~(0x3 << 9); - c_r1 |= parity; - usart->c_r1 = c_r1; -} - -void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled) -{ - if (!enabled) { - regset(usart->c_r1, usart_ue, 0); - } else { - /* Set the rx enabled. */ - regset(usart->c_r1, usart_re, !!(enabled & USART_ENABLE_RX)); - regset(usart->c_r1, usart_te, !!(enabled & USART_ENABLE_TX)); - regset(usart->c_r1, usart_ue, 1); - } -} - -void usart_transmit_byte_sync(__IO usart_t* usart, uint8_t byte) -{ - usart->td_r = byte; - /* Per the manual, when bit 7 of the IS register is set, then the usart - * data has been sent to the shift register. - * - * This bit is cleared by writing to the TD register. */ - while (!(usart->is_r & BIT(7))) - ; -} - -void usart_transmit_bytes_sync(__IO usart_t* usart, const uint8_t* bytes, uint32_t n) -{ - while (n --) { - usart_transmit_byte_sync(usart, *(bytes ++)); - } -} - -void usart_transmit_str_sync(__IO usart_t* usart, const char* str) -{ - while (*str) { - if (*str == '\n') { - usart_transmit_byte_sync(usart, '\r'); - } - usart_transmit_byte_sync(usart, *(str ++)); - } -} - -void usart_enable_dma(__IO usart_t* usart, usart_enable_t enabled) -{ - switch(enabled) { - case USART_ENABLE_DISABLED: - regset(usart->c_r3, usart_dmar, 0); - regset(usart->c_r3, usart_dmat, 0); - break; - - case USART_ENABLE_TX: - regset(usart->c_r3, usart_dmat, 1); - break; - - case USART_ENABLE_RX: - regset(usart->c_r3, usart_dmar, 1); - break; - }; -} - -void usart_vprintf(__IO usart_t* usart, const char* fmt, va_list l) -{ - union { - void* ptr; - char* str; - int i; - } b; - char buf[128]; - - while (*fmt != 0) { - if (*fmt == '%') { - switch (*(++fmt)) { - case 0: - goto end; - case '%': - usart_transmit_byte_sync(usart, '%'); - break; - case 'p': - b.ptr = va_arg(l, void*); - hexify(ptr2reg(b.ptr), buf); - usart_transmit_str_sync(usart, "0x"); - usart_transmit_str_sync(usart, buf); - break; - case 'd': - case 'i': - b.i = va_arg(l, int); - decimalify(b.i, buf); - usart_transmit_str_sync(usart, buf); - break; - case 's': - b.str = va_arg(l, char*); - usart_transmit_str_sync(usart, b.str); - } - ++ fmt; - } else { - if (*fmt == '\n') { - usart_transmit_byte_sync(usart, '\r'); - } - usart_transmit_byte_sync(usart, *(fmt ++)); - } - } - -end: - va_end(l); -} - -void usart_printf(__IO usart_t* usart, const char* fmt, ...) -{ - va_list l; - va_start(l, fmt); - - usart_vprintf(usart, fmt, l); -} diff --git a/02-usart/src/kern/delay.c b/02-usart/src/kern/delay.c deleted file mode 100644 index 28ef710..0000000 --- a/02-usart/src/kern/delay.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "kern/delay.h" - -void delay(uint32_t delay) -{ - while (delay--) { - /* needed to keep the compiler from optimizing away the loop. */ - asm volatile(""); - } -} diff --git a/02-usart/src/kern/dma/dma_manager.c b/02-usart/src/kern/dma/dma_manager.c deleted file mode 100644 index 00e9f3d..0000000 --- a/02-usart/src/kern/dma/dma_manager.c +++ /dev/null @@ -1,311 +0,0 @@ -#include "kern/dma/dma_manager.h" -#include "arch/stm32l4xxx/peripherals/dma.h" -#include "arch/stm32l4xxx/peripherals/usart.h" -#include "arch/stm32l4xxx/peripherals/rcc.h" - - -/* Bitmask of DMA2 channels in use. */ -static uint8_t dma_inuse[2]; - -static inline dma_t* get_dma(int dma) -{ - if (dma) { - return &DMA2; - } else { - return &DMA1; - } -} - -static dma_t* get_raw_dma(dma_channel_t chan) -{ - return get_dma(chan.dma); -} - -static dma_channel_config_t* get_raw_channel_config(dma_channel_t chan) -{ - dma_t* dma = get_raw_dma(chan); - return &dma->channel_config[chan.chan]; -} - -static uint32_t get_periph_location(dma_peripheral_t operipheral) -{ -#define CASE(p, n) case p: return ptr2reg(n); - switch (operipheral) { - CASE(DMA1_PERIPH_USART1_RX, &USART1.rd_r) - CASE(DMA1_PERIPH_USART1_TX, &USART1.td_r) - CASE(DMA1_PERIPH_USART2_RX, &USART2.rd_r) - CASE(DMA1_PERIPH_USART2_TX, &USART2.td_r) - - default: - return 0; - }; -#undef CASE -} - -static dma_channel_t allocate_dma_channel( - dma_peripheral_t operipheral, int* modesel) -{ - dma_peripheral_t peripheral = operipheral & 0xff; - int dmasel = peripheral >= DMA2_DMA1_SWITCH__; - if (dmasel) { - peripheral -= DMA2_DMA1_SWITCH__; - } - int chan = peripheral % DMA_N_CHANNELS; - - *modesel = peripheral / 7; - return (dma_channel_t) { - .dma = dmasel, - .chan = chan - }; -} - -/* - * Atomically reserves the DMA channel so other calls - * cannot erroneously reserve the same DMA channel. - * - * Returns 0 if this function was unable to reserve - * the channel. - */ -static int try_reserve_dma_channel( - dma_channel_t chan) -{ - int in_use = __sync_fetch_and_or( - &dma_inuse[chan.dma], 1 << chan.chan); - - return !(in_use & (1 << chan.chan)); -} - -void release_dma_channel(dma_channel_t chan) -{ - dma_channel_config_t* config = get_raw_channel_config(chan); - regset(config->cc_r, dma_cc_en, 0); /* Disable the register. */ - dma_inuse[chan.dma] &= ~(1 << chan.chan); /* Release the DMA. */ - - if (!dma_inuse[chan.dma]) { - /* Power-down the DMA if not in use. */ - if (chan.dma) { - regset(RCC.ahb1en_r, rcc_dma2en, 0); - } else { - regset(RCC.ahb1en_r, rcc_dma1en, 0); - } - } -} - -void configure_dma_channel( - dma_channel_t chan, - dma_peripheral_t operipheral, - dma_opts_t* opts, - dma_dir_t dir, - int selmode, - bool mem2mem, - int* error_out) -{ - if (chan.dma) { - regset(RCC.ahb1en_r, rcc_dma2en, 1); - } else { - regset(RCC.ahb1en_r, rcc_dma1en, 1); - } - - dma_t* dma = get_raw_dma(chan); - regset(dma->csel_r, 0xF << (4 * chan.chan), selmode); - dma_channel_config_t* config = - &dma->channel_config[chan.chan]; - - uint32_t reg = 0; - - regset(reg, dma_cc_dir, dir); - regset(reg, dma_cc_tcie, opts->transfer_complete_interrupt_enable); - regset(reg, dma_cc_htie, opts->half_transfer_interrupt_enable); - regset(reg, dma_cc_teie, opts->transfer_error_interrupt_enable); - regset(reg, dma_cc_circ, opts->circular_mode); - regset(reg, dma_cc_pinc, opts->peripheral_increment); - regset(reg, dma_cc_minc, opts->memory_increment); - regset(reg, dma_cc_psize, opts->peripheral_block_size); - regset(reg, dma_cc_msize, opts->memory_block_size); - regset(reg, dma_cc_pl, opts->priority); - regset(reg, dma_cc_mem2mem, mem2mem); - - config->cc_r = reg; - config->cpa_r = get_periph_location(operipheral); - - *error_out = 0; -} - -dma_mem2mem_channel_t select_dma_channel_mem2mem( - int channel, - dma_opts_t* opts, - int* error_out) -{ - -#define WRAP(c) ((dma_mem2mem_channel_t) { .c_ = c }) - // TODO this should probably be in a critical section. - dma_channel_t chan; - if (channel == -1) { - chan.dma = 1; - if ((dma_inuse[chan.dma] & 0x7F) == 0x7F) { - chan.dma = 0; - } - - if ((dma_inuse[chan.dma] & 0x7F) == 0x7F) { - *error_out = DMA_ERROR_CHANNEL_IN_USE; - return WRAP(DMA_CHAN_ERROR); - } - - uint8_t t = ~(dma_inuse[chan.dma] << 1); - chan.chan = 6 - (__builtin_clz(t) - 24); - } else { - if (channel < 7) { - chan.dma = 0; - chan.chan = channel; - } else { - chan.dma = 0; - chan.chan = channel - 7; - } - } - - if (!try_reserve_dma_channel(chan)) { - *error_out = DMA_ERROR_CHANNEL_IN_USE; - return WRAP(DMA_CHAN_ERROR); - } - - int ec = 0; - configure_dma_channel( - chan, - -1 /* No peripheral */, - opts, - READ_FROM_PERIPHERAL, - /* selmode = */ 0x8, - /* mem2mem = */ true, - &ec); - - if (ec) { - *error_out = ec; - return WRAP(DMA_CHAN_ERROR); - } - - *error_out = 0; - return WRAP(chan); -#undef WRAP -} - -dma_mem2p_channel_t select_dma_channel_mem2p( - dma_peripheral_t peripheral, - dma_opts_t* opts_in, - int* error_out) -{ -#define WRAP(c) ((dma_mem2p_channel_t) { .c_ = c }) - *error_out = 0; - - int modesel; - dma_channel_t ret = - allocate_dma_channel(peripheral, &modesel); - - if (!try_reserve_dma_channel(ret)) { - *error_out = DMA_ERROR_CHANNEL_IN_USE; - return WRAP(DMA_CHAN_ERROR); - } - - configure_dma_channel( - ret, - peripheral, - opts_in, - READ_FROM_MEMORY, - modesel, - /* mem2mem = */ false, - error_out); - - if (*error_out) { - return WRAP(DMA_CHAN_ERROR); - } - - *error_out = 0; - return WRAP(ret); -#undef WRAP -} - -dma_p2mem_channel_t select_dma_channel_p2mem( - dma_peripheral_t peripheral, - dma_opts_t* opts_in, - int* error_out) -{ -#define WRAP(c) ((dma_p2mem_channel_t) { .c_ = c }) - *error_out = 0; - - int modesel; - dma_channel_t ret = - allocate_dma_channel(peripheral, &modesel); - - if (!try_reserve_dma_channel(ret)) { - *error_out = DMA_ERROR_CHANNEL_IN_USE; - return WRAP(DMA_CHAN_ERROR); - } - - configure_dma_channel( - ret, - peripheral, - opts_in, - READ_FROM_PERIPHERAL, - modesel, - /* mem2mem = */ false, - error_out); - - if (*error_out) { - return WRAP(DMA_CHAN_ERROR); - } - - *error_out = 0; - return WRAP(ret); -#undef WRAP -} - - -void dma_mem2p_initiate_transfer( - dma_mem2p_channel_t chan, const void* from_loc, uint16_t nblocks) -{ - dma_channel_config_t* config = get_raw_channel_config(chan.c_); - config->cma_r = ptr2reg(from_loc); - config->cndt_r = nblocks; - - regset(config->cc_r, dma_cc_en, 1); -} - -void dma_mem2mem_initiate_transfer( - dma_mem2mem_channel_t chan, - void* to_loc, - const void* from_loc, - uint16_t nblocks) -{ - dma_channel_config_t* config = get_raw_channel_config(chan.c_); - config->cma_r = ptr2reg(to_loc); - config->cpa_r = ptr2reg(from_loc); - config->cndt_r = nblocks; - - regset(config->cc_r, dma_cc_en, 1); -} - -void dma_p2mem_initiate_transfer( - dma_p2mem_channel_t chan, void* to_loc, uint16_t nblocks) -{ - dma_channel_config_t* config = get_raw_channel_config(chan.c_); - - config->cma_r = ptr2reg(to_loc); - config->cndt_r = nblocks; - - regset(config->cc_r, dma_cc_en, 1); -} - -interrupt_t dma_channel_get_interrupt(dma_channel_t chan) -{ - if (chan.dma == 0) { - return IRQ_DMA1_CHANNEL1_IRQ + chan.chan; - } else { - switch (chan.chan) { - case 5: - return IRQ_DMA1_CHANNEL6_IRQ; - case 6: - return IRQ_DMA1_CHANNEL7_IRQ; - default: - return IRQ_DMA2_CHANNEL1_IRQ + chan.chan; - } - } -} diff --git a/02-usart/src/kern/gpio/gpio_manager.c b/02-usart/src/kern/gpio/gpio_manager.c deleted file mode 100644 index 82dd0ba..0000000 --- a/02-usart/src/kern/gpio/gpio_manager.c +++ /dev/null @@ -1,402 +0,0 @@ -#include "kern/gpio/gpio_manager.h" - -#include "arch/stm32l4xxx/peripherals/irq.h" -#include "arch/stm32l4xxx/peripherals/rcc.h" - -/* A list of whether the pins are in use or not as a bitmask. */ -uint32_t pins_inuse[N_GPIO_PINS / 32 + (N_GPIO_PINS % 32 != 0)]; - -struct gpio_afn_and_pin { - int8_t afn_number; - gpio_pin_t gpio_pin; -}; - -/* - * Returns which (pin, afn) pairs provide the given alternate function. - * The out array needs to have 5 positions. - * - * This function will use afn_number = -1 as the terminal. - * - * Note that EVENTOUT is a special case because all pins have an event out - * at afn=15 and should be assumed by other logic and thus is not handled - * by this function. - */ -static void get_ports_and_pins_for_alternate_function( - gpio_alternate_function_t afn, struct gpio_afn_and_pin* out) -{ - switch (afn) { -#define AFN1(fn, ...) \ - static_assert(false, "Unable to parse afn_table at " #fn); -#define AFN3(fn, ...) \ - static_assert(false, "Unable to parse afn_table at " #fn); -#define AFN5(fn, ...) \ - static_assert(false, "Unable to parse afn_table at " #fn); -#define AFN7(fn, ...) \ - static_assert(false, "Unable to parse afn_table at " #fn); - -#define AFN2(fn, afn, pin) \ - out[0].afn_number = afn; \ - out[0].gpio_pin = GPIO_PIN_ ## pin - -#define AFN4(fn, afn0, pin0, afn1, pin1) \ - AFN2(fn, afn0, pin0); \ - out[1].afn_number = afn1; \ - out[1].gpio_pin = GPIO_PIN_ ## pin1 - -#define AFN6(fn, afn0, pin0, afn1, pin1, afn2, pin2) \ - AFN4(fn, afn0, pin0, afn1, pin1); \ - out[2].afn_number = afn2; \ - out[2].gpio_pin = GPIO_PIN_ ## pin2 - -#define AFN8(fn, afn0, pin0, afn1, pin1, afn2, pin2, afn3, pin3) \ - AFN6(fn, afn0, pin0, afn1, pin1, afn2, pin2); \ - out[2].afn_number = afn3; \ - out[2].gpio_pin = GPIO_PIN_ ## pin3 - -#define GET_MACRO(_1, _2, _3, _4, _5, _6, _7, _8, NAME, ...) NAME -#define GET_N(_1, _2, _3, _4, _5, _6, _7, _8, NAME, ...) NAME -#define AFN(fn, ...) \ - case GPIO_ALTERNATE_FUNCTION_ ## fn: \ - GET_MACRO(__VA_ARGS__, AFN8, AFN7, AFN6, AFN5, AFN4, AFN3, AFN2, AFN1)\ - (fn, __VA_ARGS__); \ - out[GET_N(__VA_ARGS__, 4, 4, 3, 3, 2, 2, 1, 1)] = \ - (struct gpio_afn_and_pin){-1, -1}; \ - break; - -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc" - case GPIO_ALTERNATE_FUNCTION_EVENTOUT: - return; - } -} - -static inline int offset_for_gpio_pin(gpio_pin_t pin) -{ - switch (pin) { -#define PORT(p, pn) \ - case GPIO_PIN_P ## p ## pn: return pn; -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" -#undef PORT - case N_GPIO_PINS: return -1; - } - - /* Should be unreachable. */ - return -1; -} - -inline bool gpio_pin_in_use(gpio_pin_t pin) -{ - return !!(pins_inuse[pin / 32] & (1 << (pin % 32))); -} - -#define A(...) -#define B(...) -#define C(...) -#define D(...) -#define E(...) -#define F(...) -#define G(...) -#define H(...) -#define I(...) -#define SELECT_MACRO(PORT) PORT -#define PORT(port, pin) \ - SELECT_MACRO(port)(GPIO_PIN_P ## port ## pin, pin) -static int gc_port_a() -{ - return 0 -#undef A -#define A(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef A -#define A(...) -} - -static int gc_port_b() -{ - return 0 -#undef B -#define B(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef B -#define B(...) -} - -static int gc_port_c() -{ - return 0 -#undef C -#define C(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef C -#define C(...) -} - -static int gc_port_d() -{ - return 0 -#undef D -#define D(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef D -#define D(...) -} - -static int gc_port_e() -{ - return 0 -#undef E -#define E(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef E -#define E(...) -} - -static int gc_port_f() -{ - return 0 -#undef F -#define F(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef F -#define F(...) -} - -static int gc_port_g() -{ - return 0 -#undef G -#define G(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef G -#define G(...) -} - -static int gc_port_h() -{ - return 0 -#undef H -#define H(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef H -#define H(...) -} - -static int gc_port_i() -{ - return 0 -#undef I -#define I(abspin, relpin) \ - | (gpio_pin_in_use(abspin) << (relpin)) -#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" - ; -#undef I -#define I(...) -} - - -static inline bool gpio_pin_try_reserve(gpio_pin_t pin) -{ - int in_use = __sync_fetch_and_or( - &pins_inuse[pin / 32], 1 << (pin % 32)); - return !(in_use & (1 << (pin % 32))); -} - -inline static gpio_port_config_t* get_gpio_port_config(gpio_port_t port) -{ - switch(port) { - case GPIO_PORT_A: return (gpio_port_config_t*) GPIOA_BASE; - case GPIO_PORT_B: return (gpio_port_config_t*) GPIOB_BASE; - case GPIO_PORT_C: return (gpio_port_config_t*) GPIOC_BASE; - case GPIO_PORT_H: return (gpio_port_config_t*) GPIOH_BASE; - default: return NULL; - } -} - -inline static gpio_port_config_t* get_gpio_port_config_for_pin(gpio_pin_t pin) -{ - gpio_port_t port = get_port_for_pin(pin); - return get_gpio_port_config(port); -} - -gpio_reserved_pin_t reserve_gpio_pin( - gpio_pin_t pin, gpio_pin_opts_t* opts, int* error_out) -{ - *error_out = 0; - if (!gpio_pin_try_reserve(pin)) { - *error_out = GPIO_ERROR_IN_USE; - return (gpio_reserved_pin_t) { .v_ = -1 }; - } - - gpio_port_t port = get_port_for_pin(pin); - regset(RCC.ahb2en_r, rcc_gpioen(port), 1); - - gpio_port_config_t* port_config = get_gpio_port_config(port); - - - int off = offset_for_gpio_pin(pin); - - regset(port_config->mode_r, gpio_mode_n(off), opts->mode); - regset(port_config->pupd_r, gpio_pupd_n(off), opts->pull_dir); - - switch(opts->mode) { - case GPIO_MODE_INPUT: - break; - - case GPIO_MODE_OUTPUT: - regset(port_config->ospeed_r, gpio_ospeed_n(off), opts->output_opts.speed); - regset(port_config->otype_r, gpio_otype_n(off), opts->output_opts.type); - break; - - case GPIO_MODE_ALTERNATE: - if (off < 8) { - regset( - port_config->af_rl, - gpio_afsel_n(off), - opts->alternate_opts.function); - } else { - regset( - port_config->af_rh, - gpio_afsel_n(off - 8), - opts->alternate_opts.function); - } - break; - - case GPIO_MODE_ANALOG: - regset(port_config->asc_r, gpio_asc_n(off), 1); - break; - } - - return (gpio_reserved_pin_t) { .v_ = pin }; -} - -gpio_reserved_pin_t gpio_enable_alternate_function( - gpio_alternate_function_t fn, - gpio_pin_t hint, - int* error_out) -{ - int i = 0; - gpio_pin_opts_t opts; - struct gpio_afn_and_pin afn_and_pin[5]; - - if (gpio_pin_out_of_range(hint) && hint != -1) { - *error_out = GPIO_ERROR_INVALID_PIN; - return (gpio_reserved_pin_t) { .v_ = -1 }; - } - - opts.mode = GPIO_MODE_ALTERNATE; - - if (fn == GPIO_ALTERNATE_FUNCTION_EVENTOUT) { - afn_and_pin[i].afn_number = GPIO_ALTERNATE_FUNCTION_EVENTOUT; - if (hint == -1) { - hint = GPIO_PIN_PA0; - } - afn_and_pin[i].gpio_pin = hint; - } else { - get_ports_and_pins_for_alternate_function(fn, afn_and_pin); - - if (hint == -1) { - hint = afn_and_pin[0].gpio_pin; - } - - for(i = 0; - i < 5 - && afn_and_pin[i].gpio_pin != hint - && afn_and_pin[i].gpio_pin != -1; - ++ i); - - if (afn_and_pin[i].gpio_pin == -1 || i == 5) { - *error_out = GPIO_ERROR_INVALID_PIN_FOR_ALTERNATE_FUNCTION; - return (gpio_reserved_pin_t) { .v_ = -1 }; - } - } - - opts.alternate_opts.function = afn_and_pin[i].afn_number; - return reserve_gpio_pin(afn_and_pin[i].gpio_pin, &opts, error_out); -} - -void release_gpio_pin(gpio_reserved_pin_t rpin) -{ - gpio_pin_t pin = rpin.v_; - // TODO this should be a critical section. - gpio_port_t port = get_port_for_pin(pin); - pins_inuse[pin / 32] &= ~(1 << (pin % 32)); - - int used; - switch(port) { - case GPIO_PORT_A: - used = gc_port_a(); - break; - case GPIO_PORT_B: - used = gc_port_b(); - break; - case GPIO_PORT_C: - used = gc_port_c(); - break; - case GPIO_PORT_D: - used = gc_port_d(); - break; - case GPIO_PORT_E: - used = gc_port_e(); - break; - case GPIO_PORT_F: - used = gc_port_f(); - break; - case GPIO_PORT_G: - used = gc_port_g(); - break; - case GPIO_PORT_H: - used = gc_port_h(); - break; - case GPIO_PORT_I: - used = gc_port_i(); - break; - - case N_GPIO_PORTS: - used = 1; - break; - } - - if (!used) { - regset(RCC.ahb2en_r, rcc_gpioen(port), 0); - } -} - -inline void get_gpio_pin_port_off( - gpio_pin_t pin, gpio_port_config_t** out_cfg, int* out_off) -{ - *out_cfg = get_gpio_port_config_for_pin(pin); - *out_off = offset_for_gpio_pin(pin); -} - -void set_gpio_pin_high(gpio_reserved_pin_t pin) -{ - int off; - gpio_port_config_t* portcfg; - get_gpio_pin_port_off(pin.v_, &portcfg, &off); - - regset(portcfg->od_r, (1 << off), 1); -} - -void set_gpio_pin_low(gpio_reserved_pin_t pin) -{ - int off; - gpio_port_config_t* portcfg; - get_gpio_pin_port_off(pin.v_, &portcfg, &off); - - regset(portcfg->od_r, (1 << off), 0); -} diff --git a/02-usart/src/kern/gpio/sysled.c b/02-usart/src/kern/gpio/sysled.c deleted file mode 100644 index a728da3..0000000 --- a/02-usart/src/kern/gpio/sysled.c +++ /dev/null @@ -1,14 +0,0 @@ -#include "kern/gpio/sysled.h" - -#define SYSLED GPIO_PIN_PB3 - -gpio_reserved_pin_t get_sysled() -{ - if (gpio_pin_in_use(SYSLED)) { - return (gpio_reserved_pin_t) { .v_ = SYSLED }; - } - - int ec; - gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; - return reserve_gpio_pin(SYSLED, &opts, &ec); -} diff --git a/02-usart/src/kern/init.c b/02-usart/src/kern/init.c deleted file mode 100644 index 2531ca9..0000000 --- a/02-usart/src/kern/init.c +++ /dev/null @@ -1,82 +0,0 @@ -#include "kern/init.h" - -#include "arch.h" -#include "arch/stm32l4xxx/peripherals/system.h" -#include "arch/stm32l4xxx/peripherals/clock.h" - -#include "kern/log.h" - -/* Forward-declare the main function. This is implemented in main.c. */ -int main(); - -/* These are defined in the linker script. */ - -#ifdef ARCH_STM32L4 -extern uint32_t INIT_DATA_VALUES; -extern uint32_t DATA_SEGMENT_START; -extern uint32_t DATA_SEGMENT_STOP; -extern uint32_t BSS_START; -extern uint32_t BSS_END; - -extern void(*INIT_ROUTINES_FLASH_START)(); -extern void(*INIT_ROUTINES_FLASH_STOP)(); - -init0() -{ - /* Enable a higher clock speed. This is the first thing we do - * beacuse it will boost the boot up time. */ - set_system_clock_MHz(80); -} - -init1() -{ - /* Next, we'll copy the data sections from flash to ram. */ - uint32_t* src; - uint32_t* dest; - - src = &INIT_DATA_VALUES; - dest = &DATA_SEGMENT_START; - - /* Copy the values from flash into the data segment. */ - while (dest != &DATA_SEGMENT_STOP) { - *(dest++) = *(src++); - } - - /* Everything in the BSS segment is set to zero. */ - dest = &BSS_START; - while (dest != &BSS_END) { - *(dest++) = 0; - } -} - -init3() -{ - klogf("--- System Restart ---\n"); - klogf("Setting the vector offset table to point to the start of flash.\n"); - - /* Set the vector offset table to be at the start - * of FLASH memory. */ - SCB.vto_r = 0x08000000; -} - -/* - * Runs before main. Initializes the data and bss segments by loading them - * into memory. - */ -_Noreturn void on_reset() -{ - void (**initfn)(); - for(initfn = &INIT_ROUTINES_FLASH_START; - initfn < &INIT_ROUTINES_FLASH_STOP; - ++ initfn) { - - (*initfn)(); - } - - /* Jump to main. */ - main(); - - for(;;); -} - -#endif /* ARCH_STM32L4 */ diff --git a/02-usart/src/kern/lib.c b/02-usart/src/kern/lib.c deleted file mode 100644 index 88188cc..0000000 --- a/02-usart/src/kern/lib.c +++ /dev/null @@ -1,56 +0,0 @@ -#include "kern/lib.h" - -#define nybble_to_hex(n) \ - ((n) < 10 ? 0x30 + (n) : ('A' + ((n) - 10))) - -void hexify(uint32_t v, char* into) -{ - into += 8; - - *(into--) = 0; - - *(into--) = nybble_to_hex(v & 0x0F); - v >>= 4; - *(into--) = nybble_to_hex(v & 0x0F); - v >>= 4; - *(into--) = nybble_to_hex(v & 0x0F); - v >>= 4; - *(into--) = nybble_to_hex(v & 0x0F); - v >>= 4; - - *(into--) = nybble_to_hex(v & 0x0F); - v >>= 4; - *(into--) = nybble_to_hex(v & 0x0F); - v >>= 4; - *(into--) = nybble_to_hex(v & 0x0F); - v >>= 4; - *into = nybble_to_hex(v & 0x0F); - v >>= 4; -} - -void decimalify(int v, char* into) -{ - int c = 0; - int i; - - if (v == 0) { - *(into ++) = '0'; - *into = 0; - return; - } else { - while (v > 0) { - *(into ++) = 0x30 + (v % 10); - v /= 10; - ++ c; - } - } - *into = 0; - - into -= c; - for (i = 0; i < c / 2; ++ i) { - char tmp = into[i]; - into[i] = into[c - i - 1]; - into[c - i - 1] = tmp; - } - -} diff --git a/02-usart/src/kern/log.c b/02-usart/src/kern/log.c deleted file mode 100644 index a217183..0000000 --- a/02-usart/src/kern/log.c +++ /dev/null @@ -1,55 +0,0 @@ -#include "arch/stm32l4xxx/peripherals/usart.h" -#include "arch/stm32l4xxx/peripherals/clock.h" - -#include "kern/log.h" -#include "kern/init.h" -#include "kern/gpio/gpio_manager.h" - -#include "kern/common.h" - -void setup_usart2(uint32_t baud_rate); - -/** This module requires an initialization routine. This is a level2 routine, - * so anything running at level3 or lower is guaranteed to have access - * to the klong. */ -init2() -{ - setup_usart2(115200); - regset(USART2.c_r1, usart_txeie, 1); - regset(USART2.c_r1, usart_rxneie, 1); - usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX); - - klogf("klog() enabled on USART2\n"); -} - -void klogf(const char* fmt, ...) -{ - va_list l; - va_start(l, fmt); - - usart_vprintf(&USART2, fmt, l); -} - -void setup_usart2(uint32_t baud_rate) -{ - enable_hsi(&RCC, true); - - int ec = 0; - gpio_enable_alternate_function( - GPIO_ALTERNATE_FUNCTION_USART2_TX, GPIO_PIN_PA2, &ec); - - gpio_enable_alternate_function( - GPIO_ALTERNATE_FUNCTION_USART2_RX, GPIO_PIN_PA15, &ec); - - set_usart2_clock_src(&RCC, USART_CLK_SRC_HSI16); - set_usart2_clock_enabled(&RCC, USART_CLK_SRC_HSI16); - - /* De-assert reset of USART2 */ - regset(RCC.apb1rst1_r, rcc_usart2rst, 0); - - USART2.c_r1 = 0; - USART2.c_r2 = 0; - USART2.c_r3 = 0; - - usart_set_divisor(&USART2, 16000000 / baud_rate); -} diff --git a/02-usart/src/kern/main.c b/02-usart/src/kern/main.c deleted file mode 100644 index ebb2164..0000000 --- a/02-usart/src/kern/main.c +++ /dev/null @@ -1,29 +0,0 @@ -#include "arch.h" -#include "kern/log.h" - -#include "arch/stm32l4xxx/peripherals/system.h" -#include "arch/stm32l4xxx/peripherals/clock.h" - -void on_systick() /* Overrides weak-symbol on_systick. */ -{ - klogf("Systick\n"); -} - -#ifdef ARCH_STM32L4 - -/* Main function. This gets executed from the interrupt vector defined above. */ -int main() -{ - klogf("Hello, World! Clock Mhz: %d\n", (uint32_t) get_clock_mhz()); - - /* Set the countdown to start from 10,000,0000. */ - SCB.strv_r = 10000000; - - /* Enable interrupts. */ - regset(SCB.stcs_r, scb_tickint, 1); - - /* Start the systick. */ - regset(SCB.stcs_r, scb_enable, 1); -} - -#endif diff --git a/02-usart/src/kern/mem.c b/02-usart/src/kern/mem.c deleted file mode 100644 index 5234fff..0000000 --- a/02-usart/src/kern/mem.c +++ /dev/null @@ -1,280 +0,0 @@ -#include "arch.h" -#include "kern/mem.h" -#include "kern/common.h" - -#ifdef ARCH_STM32L4 -/* Provide a definition for memset() when not provided for the - * microcontroller. */ -void* memset(void* dest, int c, size_t n) -{ - uint8_t c8 = (uint8_t) c; - uint8_t* dest8 = (uint8_t*) dest; - uint8_t* to = dest8 + n; - - while(dest8 < to) { - *(dest8 ++) = c8; - } - - return dest; -} - -#else - -void* memset(void* dest, int c, size_t n); - -#endif - -typedef uint16_t halloc_off_t; - -#define CANARY 0x5a - -// The sizes will count the number of WORDS allocated. -// Since there's a max size of 16k, only 12 bits will be -// needed for this. -typedef struct HALLOC_NODE { - union { - uint32_t header; - struct { - /* Is this memory block currently in use (hasn't been hfree'd) */ - uint8_t used:1; - /* Number of words allocated. Does not include the header. */ - uint16_t size:12; - /* The location of the previous block (in WORDS from offest) */ - halloc_off_t prev:12; - uint8_t canary:7; - } PACKED; - }; - - uint8_t mem[]; /* The memory to use. */ -} halloc_node_t; - -static_assert(offsetof(halloc_node_t, mem) == 4, "Offset check failed."); - -halloc_node_t* halloc_start; - -#define halloc_node_out_of_range(node) \ - ((uint8_t*) (node) == ((uint8_t*)&DATA_SEGMENT_STOP) + MAX_HEAP_SIZE) - -#define halloc_node_next(cur) \ - ((halloc_node_t*)(((uint8_t*)(cur)) + (((cur)->size + 1) * 4))) - -#define halloc_node_prev(cur) halloc_node_at_off(cur->prev) - -#define halloc_node_at_off(offset) \ - ((halloc_node_t*)(((uint8_t*) halloc_start) + (offset) * 4)) - -#define halloc_node_get_off(node) \ - (((uint32_t)(((uint8_t*)(node)) - ((uint8_t*)(halloc_start)))) / 4) - -#define get_halloc_node(mem) \ - ((halloc_node_t*)(((uint8_t*)mem) - 4)) - -#define size_for(n) \ - (((n) / 4) + ((n) % 4 != 0)) - -void* halloc(size_t size) -{ - if (!halloc_start) { - halloc_start = (halloc_node_t*) DATA_SEGMENT_STOP_ADDR; - memset(halloc_start, 0, sizeof(halloc_node_t)); - halloc_start->size = (MAX_HEAP_SIZE / 4) - 1; - halloc_start->canary = CANARY; - } - - size_t realsz = size_for(size); /* Clip the size to the nearest word. */ - halloc_off_t offset = 0; - while (offset < (MAX_HEAP_SIZE / 4)) { - halloc_node_t* cur = halloc_node_at_off(offset); - - if (!cur->used && (cur->size >= realsz)) { - cur->used = true; - size_t orig_size = cur->size; - cur->size = realsz; - - if (orig_size > realsz) { - /* This halloc node needs to split into two blocks. */ - halloc_node_t* next = halloc_node_next(cur); - next->used = 0; - next->size = orig_size - realsz - sizeof(halloc_node_t) / 4; - next->prev = offset; - next->canary = CANARY; - - halloc_node_t* nextnext = halloc_node_next(next); - if (halloc_node_get_off(nextnext) < (MAX_HEAP_SIZE / 4)) { - nextnext->prev = halloc_node_get_off(next); - } - } - - return (void*) cur->mem; - } - - offset += (sizeof(halloc_node_t) / 4) + cur->size; - } - - return NULL; -} - - -/* Joins this node with the previous and next nodes if they're free. */ -static void coalesce(halloc_node_t* cur) -{ - halloc_node_t* orig = cur; - halloc_node_t* last_freed; - halloc_node_t* next_used; - - /* Find the earliest contiguous free'd block. */ - while (!cur->used && cur != halloc_start) { - cur = halloc_node_prev(cur); - } - - if (cur == halloc_start && !cur->used) { - last_freed = cur; - } else { - last_freed = halloc_node_next(cur); - } - - /* Find the next used block. */ - cur = orig; - while (!cur->used && !halloc_node_out_of_range(cur)) { - cur = halloc_node_next(cur); - } - - next_used = cur; - - if (!halloc_node_out_of_range(next_used)) { - next_used->prev = halloc_node_get_off(last_freed); - } - - last_freed->size = ((uint8_t*) next_used - (last_freed->mem)) / 4; -} - -#ifdef FOR_TESTING -#include -#include -void panic(const char* x) -{ - fprintf(stderr, "%s\n", x); - assert(0); -} -#else -void panic(const char* x) -{ - for(;;); -} -#endif - -void hfree(void* mem) -{ - /* Like normal free(), do nothing on free'ing NULL */ - if (!mem) return; - - halloc_node_t* header = get_halloc_node(mem); - if (!header->used) { - panic("Heap double free or corruption!\n"); - return; - } - - header->used = 0; - coalesce(header); -} - -#ifdef FOR_TESTING - -#include - -void* debug_halloc_get_next_ptr(void* ptr) -{ - halloc_node_t* node = ptr - sizeof(halloc_node_t); - halloc_node_t* next = halloc_node_next(node); - - return next->mem; -} - -void* debug_halloc_get_prev_ptr(void* ptr) -{ - halloc_node_t* node = ptr - sizeof(halloc_node_t); - halloc_node_t* prev = halloc_node_prev(node); - - return prev->mem; -} - -void debug_print_blocks() -{ - printf("------ Print Blocks -------\n"); - halloc_node_t* cur = halloc_node_at_off(0); - - while (!halloc_node_out_of_range(cur)) { - printf("header (%04x) {used=%d, size=%5d, prev=%04x, canary=%02x}\n", - halloc_node_get_off(cur), cur->used, cur->size, cur->prev, cur->canary); - cur = halloc_node_next(cur); - } -} - -/* Tests that we can walk up and down the allocated blocks and that they - * are properly aligned. */ -int debug_halloc_assert_consistency(char* error, size_t len) -{ - halloc_node_t* cur = halloc_node_at_off(0); - size_t total_size = 0; - size_t loop_check = 0; - size_t n_blocks = 1; - size_t n_blocks_back = 1; - - while(1) { - if (cur->canary != CANARY) { - snprintf(error, len, "Node has corrupted canary. %02x vs expected %02x\n", - cur->canary, CANARY); - return 1; - } - - total_size += cur->size + 1; - - halloc_node_t* next = halloc_node_next(cur); - if ((uint8_t*) next == ((uint8_t*)&DATA_SEGMENT_STOP) + MAX_HEAP_SIZE) { - break; - } else if ((uint8_t*) next > (uint8_t*)DATA_SEGMENT_STOP_ADDR + MAX_HEAP_SIZE){ - snprintf( - error, len, "Next node points is out of bounds. %p vs max of %p\n", - next, - (void*)(DATA_SEGMENT_STOP_ADDR + MAX_HEAP_SIZE)); - return 1; - } - - cur = next; - ++ n_blocks; - } - - if (total_size * 4 != MAX_HEAP_SIZE) { - snprintf( - error, len, "Total recorded size is inconsistent. %lu vs %lu\n", - total_size * 4, MAX_HEAP_SIZE); - return 1; - } - - if (cur == halloc_start) { - return 0; - } - - while (loop_check < 10000) { - halloc_node_t* prev = halloc_node_prev(cur); - ++ n_blocks_back; - - if (prev == halloc_start) { - if (n_blocks != n_blocks_back) { - snprintf( - error, len, "Different number of blocks found on the way back. Found %lu on the way back vs %lu up.\n", - n_blocks_back, n_blocks); - return 1; - } - return 0; - } - - cur = prev; - ++ loop_check; - } - - snprintf(error, len, "Loop check failed.\n"); - return 1; -} - -#endif diff --git a/02-usart/src/kern/stdlibrepl.c b/02-usart/src/kern/stdlibrepl.c deleted file mode 100644 index 2d9d839..0000000 --- a/02-usart/src/kern/stdlibrepl.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Replacement for common stdlib functions that don't exist - * on the ARM bare-metal compilation environment. - */ - -#include - -size_t strlen(char* ch) -{ - size_t ret = 0; - while(*(ch ++) != 0) ++ ret; - return ret; -} diff --git a/02-usart/src/kern/string.c b/02-usart/src/kern/string.c deleted file mode 100644 index 4afa228..0000000 --- a/02-usart/src/kern/string.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "kern/string.h" - -void kstrcpy(char* into, const char* from) -{ - while(*from) { - *(into ++) = *(from ++); - } - *into = 0; -} diff --git a/02-usart/src/kern/vector.c b/02-usart/src/kern/vector.c deleted file mode 100644 index e69de29..0000000 diff --git a/02-usart/test_harness/Makefile b/02-usart/test_harness/Makefile deleted file mode 100644 index 443292b..0000000 --- a/02-usart/test_harness/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -CC=gcc -CFLAGS=-g3 -ggdb -Wall - -test_harness.a: test_harness.c test_harness.h fake_env.o - gcc -o test_harness.o -c test_harness.c $(CFLAGS) - ar r test_harness.a test_harness.o fake_env.o - -fake_env.o: fake_env.c fake_env.h - gcc -o fake_env.o -c fake_env.c $(CFLAGS) diff --git a/02-usart/test_harness/fake_env.c b/02-usart/test_harness/fake_env.c deleted file mode 100644 index 6a32c99..0000000 --- a/02-usart/test_harness/fake_env.c +++ /dev/null @@ -1,63 +0,0 @@ -#include "fake_env.h" - -#include -#include - -struct fakeenv_memseg { - const char* name; - void* segment; -}; - -#define DEFINE_MEMORY_SEGMENT(seg, start_addr, end_addr) \ - static __attribute((__section__("fakeenv"))) \ - struct fakeenv_memseg fake_##seg = { \ - .name = #seg, \ - .segment = NULL, \ - }; \ - void* load_fake_##seg##__ () \ - { \ - if (fake_##seg .segment == NULL) { \ - fake_##seg .segment = malloc((end_addr) - (start_addr)); \ - assert(fake_##seg .segment != NULL); \ - } \ - return fake_##seg.segment; \ - } - -extern struct fakeenv_memseg __start_fakeenv; -extern struct fakeenv_memseg __stop_fakeenv; - -void wipeout_fake_env() -{ - for (struct fakeenv_memseg* iter = &__start_fakeenv; - iter < &__stop_fakeenv; - ++ iter) { - free(iter->segment); - iter->segment = NULL; - } -} - -/* Reset and clock control. */ -DEFINE_MEMORY_SEGMENT(rcc, 0x40021000, 0x400210A0) - -/* Peripheral buses */ -DEFINE_MEMORY_SEGMENT(apb1, 0x40000000, 0x40010000) -DEFINE_MEMORY_SEGMENT(apb2, 0x40010000, 0x40020000) -DEFINE_MEMORY_SEGMENT(ahb1, 0x40020000, 0x40024400) -DEFINE_MEMORY_SEGMENT(ahb2, 0x48000000, 0x50060C00) - -/* System Control Block */ -DEFINE_MEMORY_SEGMENT(scb, 0xE000E008, 0xE000EF04) - -/* Nested Vector Interrupt Controller (NVIC) */ -/* Note that this memory space acutally overlaps with the SCB, but - * they are functionally distinct entitites and such are modeled as - * separate structures in memeory. */ -DEFINE_MEMORY_SEGMENT(nvic, 0xE000E004, 0xE000E4F0) - -/* SRAM */ -DEFINE_MEMORY_SEGMENT(sram1, 0x20000000, 0x2000C000) -DEFINE_MEMORY_SEGMENT(sram2, 0x2000C000, 0x20018000) - -/* Serial Peripheral Interface */ -DEFINE_MEMORY_SEGMENT(spi1, 0x40013000, 0x400133FF) -DEFINE_MEMORY_SEGMENT(spi3, 0x40003C00, 0x40003FFF) diff --git a/02-usart/test_harness/fake_env.h b/02-usart/test_harness/fake_env.h deleted file mode 100644 index 34056f4..0000000 --- a/02-usart/test_harness/fake_env.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef FAKE_ENV_H_ -#define FAKE_ENV_H_ - -/* Functions which wil lazily load fake chunks of memory - * corresponding to the*/ -void* load_fake_ahb1__(); -void* load_fake_ahb2__(); -void* load_fake_apb1__(); -void* load_fake_apb2__(); -void* load_fake_sram1__(); -void* load_fake_sram2__(); -void* load_fake_scb__(); -void* load_fake_nvic__(); -void* load_fake_rcc__(); -void* load_fake_spi1__(); -void* load_fake_spi3__(); - -void wipeout_fake_env(); - -#endif /* FAKE_ENV_H_ */ diff --git a/02-usart/test_harness/test_harness.c b/02-usart/test_harness/test_harness.c deleted file mode 100644 index bf9249c..0000000 --- a/02-usart/test_harness/test_harness.c +++ /dev/null @@ -1,181 +0,0 @@ -#include "test_harness.h" -#include "fake_env.h" - -#include -#include -#include -#include -#include -#include -#include - - -static jmp_buf jmpbuf; - -volatile test_t dummy - __attribute((__section__("tests"))) - __attribute((__used__)) = { - "dummy", - "dummy", - NULL -}; - -extern unsigned char __data_start; -extern unsigned char _end; -extern test_t __start_tests; -extern test_t __stop_tests; - -test_t* iter = &__start_tests; - -static int execute_test(test_t* test); - -void test_printll(size_t sz, long long v1, long long v2) -{ - fprintf(stderr, "%lld == %lld\n", v1, v2); -} -void test_printul(size_t sz, unsigned long v1, unsigned long v2) -{ - fprintf(stderr, "%lu == %lu\n", v1, v2); -} -void test_printd(size_t sz, int v1, int v2) -{ - fprintf(stderr, "%d == %d\n", v1, v2); -} -void test_printl(size_t sz, long v1, long v2) -{ - fprintf(stderr, "%lu == %lu\n", v1, v2); -} -void test_printui(size_t sz, unsigned int v1, unsigned int v2) -{ - fprintf(stderr, "%u == %u\n", v1, v2); -} -void test_prints(size_t sz, short v1, short v2) -{ - fprintf(stderr, "%hu == %hu\n", v1, v2); -} -void test_printus(size_t sz, unsigned short v1, unsigned short v2) -{ - fprintf(stderr, "%hu == %hu\n", v1, v2); -} -void test_printc(size_t sz, char v1, char v2) -{ - fprintf(stderr, "'%c' == '%c'\n", v1, v2); -} -void test_printf(size_t sz, double v1, double v2) -{ - fprintf(stderr, "%f == %f\n", v1, v2); -} -void test_printp(size_t sz, void* v1, void* v2) -{ - fprintf(stderr, "%p == %p\n", v1, v2); -} -void test_printuc( - size_t sz, unsigned char v1, unsigned char v2) -{ - fprintf(stderr, "%02x == %02x\n", (int) v1, (int) v2); -} - -static int do_fork = 1; -static size_t saved_data_size; -static unsigned char* saved_data = NULL; - -int main(int argc, char** argv) { - /* Save all initialized data. */ - saved_data_size = &_end - &__data_start; - saved_data = malloc(saved_data_size); - memcpy(saved_data, &__data_start, saved_data_size); - - - if (argc > 1 && strcmp(argv[1], "--nofork") == 0) { - do_fork = 0; - } - - for( ; iter < &__stop_tests; ++ iter) { - if (iter->fn_ptr != NULL) { - execute_test(iter); - } - } -} - -void test_harness_abort(int ec) -{ - longjmp(jmpbuf, ec); - assert("Long jump failed.\n"); -} - -/* - * When nofork is true, this function will be called after each - * test to try and make each test hermetic. - * - * It does this by reseting the data segment to what it was when - * the program was first initialized. - * - * Of course, without forking, there's no way to guarantee hermetic - * testing in C. In fact a simple segementation fault will break - * the hermetic testing, but this does a pretty good job of at least - * reseting the environment so tests don't directly depend on eachother. - */ -static void nofork_reset() -{ - wipeout_fake_env(); - - /* Reset the data segment to what it was before. */ - memcpy(&__data_start, saved_data, saved_data_size); -} - -static int execute_test(test_t* test) -{ - char fullname[512]; - int status; - int ec = 0; - pid_t pid; - - snprintf( - fullname, sizeof(fullname), "%s::%s", iter->test_suite, iter->test_name); - - if (!do_fork) { - if ((ec = setjmp(jmpbuf)) == 0) { - test->fn_ptr(); - printf(GREEN "[PASS]" RESET " %s\n", fullname); - nofork_reset(); - return 0; - } else { - printf(RED "[FAIL] (%d)" RESET " %s\n", ec, fullname); - nofork_reset(); - return ec; - } - } - - if (!(pid = fork())) { - // child - - if ((ec = setjmp(jmpbuf))) { - exit(ec); - } else { - test->fn_ptr(); - exit(0); - } - } else { - if (waitpid(pid, &status, 0) == -1) { - fprintf(stderr, "waitpid() failed\n"); - return 1; - } - - if (WIFEXITED(status)) { - switch ((ec = WEXITSTATUS(status))) { - case 0: - printf(GREEN "[PASS]" RESET " %s\n", fullname); - return 0; - default: - printf(RED "[FAIL] (%d)" RESET " %s\n", ec, fullname); - return ec; - } - } else if (WIFSIGNALED(status)) { - int ec = WTERMSIG(status); - printf("%s " RED "[FAIL] signaled %d" RESET "\n", fullname, ec); - return ec; - } - - return ec; - } -} diff --git a/02-usart/test_harness/test_harness.h b/02-usart/test_harness/test_harness.h deleted file mode 100644 index 698e2da..0000000 --- a/02-usart/test_harness/test_harness.h +++ /dev/null @@ -1,101 +0,0 @@ -#ifndef TEST_HARNESS_H_ -#define TEST_HARNESS_H_ - -#include -#include - -#define YELLOW "\x1b[00;33m" -#define GREEN "\x1b[01;32m" -#define RED "\x1b[01;31m" -#define RESET "\x1b[0m" - -typedef struct { - const char* test_suite; - const char* test_name; - int (*fn_ptr)(); - void* alignment; -} test_t; - -#define GENPR(fmt, v1, v2) \ - fprintf(stderr, fmt "\n", v1, v2) - -void test_printll(size_t sz, long long v1, long long v2); -void test_printul(size_t sz, unsigned long v1, unsigned long v2); -void test_printd(size_t sz, int v1, int v2); -void test_printl(size_t sz, long v1, long v2); -void test_printui(size_t sz, unsigned int v1, unsigned int v2); -void test_prints(size_t sz, short v1, short v2); -void test_printus(size_t sz, unsigned short v1, unsigned short v2); -void test_printc(size_t sz, char v1, char v2); -void test_printf(size_t sz, double v1, double v2); -void test_printp(size_t sz, void* v1, void* v2); -void test_printuc(size_t sz, unsigned char v1, unsigned char v2); - -#define FORMAT_STRING(v1, v2) \ - _Generic((v1), \ - long long: test_printll, \ - unsigned long: test_printul, \ - int: test_printd, \ - long: test_printl, \ - unsigned int: test_printui, \ - short: test_prints, \ - unsigned short: test_printus, \ - char: test_printc, \ - unsigned char: test_printuc, \ - double: test_printf, \ - default: test_printp)(sizeof(v1), v1, v2) \ - -#define TRY_PRINT_TYPE(v1, v2, type, fmt) \ - else if (__builtin_types_compatible_p(typeof (v1), type)) { \ - fprintf(stderr, fmt " == " fmt "\n", v1, v2); \ - } - -#define TYPE_STR(t) #t - -#define ASSERT_TRUE(x) \ - do { \ - if (!(x)) { \ - fprintf(stderr, RED "ASSERT_TRUE FAILED!\n" RESET); \ - fprintf(stderr, " - " YELLOW "In expression ASSERT_TRUE(" #x ")\n"); \ - fprintf(stderr, RESET " - " YELLOW "At " __FILE__ ":%d\n" RESET, __LINE__); \ - test_harness_abort(1); \ - } \ - } while (0) - -#define ASSERT_EQ(x, y) \ - do { \ - if ((x) != (y)) { \ - fprintf(stderr, RED "ASSERT_EQ FAILED! " RESET "Not true that "); \ - FORMAT_STRING((x), (y)); \ - fprintf(stderr, " - " YELLOW "In expression ASSERT_EQ(" #x ", " #y ")\n"); \ - fprintf(stderr, RESET " - " YELLOW "At " __FILE__ ":%d\n" RESET, __LINE__); \ - test_harness_abort(1); \ - } \ - } while (0) - -#define ASSERT_EQ_STR(x, y) \ - do { \ - if (strcmp(x, y)) { \ - fprintf(stderr, \ - RED "ASSSERT_EQ_STR FAILED! " RESET "Not true that \"%s\" equals \"%s\"", \ - x, y); \ - fprintf(stderr, " - " YELLOW "In expression ASSERT_EQ_STR(" #x ", " #y ")\n"); \ - fprintf(stderr, RESET " - " YELLOW "At " __FILE__":%d\n" RESET, __LINE__); \ - test_harness_abort(1); \ - } \ - } while (0) - - -#define TEST(test_suite, test_name) \ - int test_suite ## _ ## test_name ## _fn (void); \ - volatile test_t test_suite ## _ ## test_name ## _testing_struct__ \ - __attribute((__section__("tests"))) __attribute((__used__)) = \ - {#test_suite, #test_name, test_suite ## _ ## test_name ## _fn}; \ - int test_suite ## _ ## test_name ## _fn (void) - -void test_harness_abort(int ec); - - -void wipeout_fake_env(); - -#endif diff --git a/02-usart/tests/metatest.c b/02-usart/tests/metatest.c deleted file mode 100644 index 1024156..0000000 --- a/02-usart/tests/metatest.c +++ /dev/null @@ -1,22 +0,0 @@ -#include "test_harness.h" - -/* Tests the test harness itself. */ - -static int my_variable; -static int my_initialized_variable = 5; - -TEST(meta, clobbers_variables) -{ - my_variable = 6; - my_initialized_variable = 5; - - return 0; -} - -TEST(meta, variables_reset) -{ - ASSERT_EQ(my_variable, 0); - ASSERT_EQ(my_initialized_variable, 5); - - return 0; -} diff --git a/02-usart/tests/test_dma.c b/02-usart/tests/test_dma.c deleted file mode 100644 index 50cdb5b..0000000 --- a/02-usart/tests/test_dma.c +++ /dev/null @@ -1,189 +0,0 @@ -#include "test_harness.h" -#include "arch/stm32l4xxx/peripherals/dma.h" -#include "arch/stm32l4xxx/peripherals/rcc.h" -#include "arch/stm32l4xxx/peripherals/usart.h" -#include "kern/dma/dma_manager.h" - -#include -#include -#include - -TEST(dma, smoke) -{ - dma_t* dma = &DMA1; - memset(dma, 0, sizeof(dma_t)); - - regset(dma->is_r, dma_tcif1, 1); - ASSERT_EQ(dma->is_r, 2); - - regset(dma->is_r, dma_htif7, 1); - ASSERT_EQ(dma->is_r, 67108866); - return 0; -} - -TEST(dma, cc_regset) -{ - dma_t* dma = &DMA1; - memset(dma, 0, sizeof(dma_t)); - - dma_channel_config_t* channel_config = &dma->channel_config[2]; - regset(channel_config->cc_r, dma_cc_msize, DMA_SIZE_32_BITS); - - ASSERT_EQ(channel_config->cc_r, 1 << 11); - return 0; -} - -TEST(dma, correct_align) -{ - dma_t dma; - - // Assert the DMA registers are aligned with what the spec says. - ASSERT_EQ((long)(&dma.csel_r) - (long)(&dma), 0xA8); - - return 0; -} - -TEST(dma, regset_pl) -{ - uint32_t reg = 0; - - regset(reg, dma_cc_pl, DMA_PRIORITY_LEVEL_MEDIUM); - - ASSERT_EQ(reg, (1 << 12)); - - ASSERT_EQ( - regget(reg, dma_cc_pl), - DMA_PRIORITY_LEVEL_MEDIUM); - return 0; -} - -TEST(dma_peri, select_peripheral) -{ - dma_opts_t opts = DEFAULT_DMA_OPTS; - int ec; - - dma_mem2p_channel_t chan = - select_dma_channel_mem2p( - DMA1_PERIPH_USART2_TX, - &opts, - &ec); - - ASSERT_EQ(DMA1.channel_config[6].cpa_r, ptr2reg(&USART2.td_r)); - - ASSERT_EQ( - regget(DMA1.channel_config[6].cc_r, dma_cc_dir), - READ_FROM_MEMORY); - - ASSERT_EQ( - regget(DMA1.channel_config[6].cc_r, dma_cc_minc), - 1); - - ASSERT_EQ( - regget(DMA1.channel_config[6].cc_r, dma_cc_pl), - DMA_PRIORITY_LEVEL_MEDIUM); - - ASSERT_EQ(regget(DMA1.csel_r, dma_c7s), 0x2); - - ASSERT_EQ(regget(RCC.ahb1en_r, rcc_dma1en), 1); - - release_dma_channel(chan.c_); - - ASSERT_EQ(regget(RCC.ahb1en_r, rcc_dma1en), 0); - return 0; -} - -TEST(dma_peri, unable_to_realloc) -{ - dma_opts_t opts = DEFAULT_DMA_OPTS; - - int ec = 0; - - dma_mem2p_channel_t chan = - select_dma_channel_mem2p( - DMA1_PERIPH_USART2_TX, - &opts, - &ec); - - ASSERT_EQ(ec, 0); - - select_dma_channel_p2mem( - DMA1_PERIPH_USART2_TX, - &opts, - &ec); - - ASSERT_EQ(ec, DMA_ERROR_CHANNEL_IN_USE); - - release_dma_channel(chan.c_); - - chan = select_dma_channel_mem2p( - DMA1_PERIPH_USART2_TX, - &opts, - &ec); - - ASSERT_EQ(ec, 0); - - release_dma_channel(chan.c_); - return 0; -} - -TEST(dma_peri, select_mem2mem) -{ - int ec = 0; - dma_opts_t opts = DEFAULT_DMA_OPTS; - dma_mem2mem_channel_t chan = - select_dma_channel_mem2mem(-1, &opts, &ec); - - ASSERT_EQ(ec, 0); - - ASSERT_EQ(chan.c_.dma, 1); - ASSERT_EQ(chan.c_.chan, 6); - - dma_mem2mem_channel_t chan2 = - select_dma_channel_mem2mem(-1, &opts, &ec); - - ASSERT_EQ(ec, 0); - - ASSERT_EQ(chan2.c_.dma, 1); - ASSERT_EQ(chan2.c_.chan, 5); - - release_dma_channel(chan.c_); - - dma_mem2mem_channel_t chan3 = - select_dma_channel_mem2mem(-1, &opts, &ec); - - ASSERT_EQ(chan3.c_.dma, 1); - ASSERT_EQ(chan3.c_.chan, 6); - - release_dma_channel(chan2.c_); - release_dma_channel(chan3.c_); - return 0; -} - -TEST(dma_peri, select_mem2mem_2) -{ - dma_opts_t opts = DEFAULT_DMA_OPTS; - dma_mem2mem_channel_t chans[14]; - int ec; - - for (int i = 0; i < 14; ++ i) { - chans[i] = select_dma_channel_mem2mem( - -1, &opts, &ec); - - ASSERT_EQ(ec, 0); - } - - select_dma_channel_mem2mem(-1, &opts, &ec); - ASSERT_EQ(ec, DMA_ERROR_CHANNEL_IN_USE); - - for (int i = 0; i < 14; ++ i) { - if (i < 7) { - ASSERT_EQ(chans[i].c_.chan, 6 - i); - ASSERT_EQ(chans[i].c_.dma, 1); - } else { - ASSERT_EQ(chans[i].c_.chan, 6 - (i - 7)); - ASSERT_EQ(chans[i].c_.dma, 0); - } - release_dma_channel(chans[i].c_); - } - return 0; -} diff --git a/02-usart/tests/test_gpio.c b/02-usart/tests/test_gpio.c deleted file mode 100644 index bcb953c..0000000 --- a/02-usart/tests/test_gpio.c +++ /dev/null @@ -1,194 +0,0 @@ -#include "test_harness.h" - -#include "arch/stm32l4xxx/peripherals/rcc.h" -#include "kern/gpio/gpio_manager.h" - -TEST(gpio_manager, smell) -{ - gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; - int ec = 5; - gpio_reserved_pin_t some_pin = reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); - ASSERT_EQ(ec, 0); - ASSERT_TRUE(gpio_pin_in_use(GPIO_PIN_PA15)); - - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); - release_gpio_pin(some_pin); - - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); - return 0; -} - -TEST(gpio_manager, multiplereserve) -{ - int ec; - gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; - reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); - ASSERT_TRUE(ec == 0); - - reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); - ASSERT_EQ(ec, GPIO_ERROR_IN_USE); - - return 0; -} - -TEST(gpio_manager, alternate) -{ - int ec; - - /* Pretending to start the USART. */ - gpio_enable_alternate_function( - GPIO_ALTERNATE_FUNCTION_USART2_TX, GPIO_PIN_PA2, &ec); - - ASSERT_EQ(ec, 0); - - gpio_enable_alternate_function( - GPIO_ALTERNATE_FUNCTION_USART2_RX, GPIO_PIN_PA15, &ec); - - ASSERT_EQ(ec, 0); - - gpio_port_config_t* gpioa = (gpio_port_config_t*) GPIOA_BASE; - - ASSERT_EQ(regget(gpioa->mode_r, gpio_mode_n(15)), GPIO_MODE_ALTERNATE); - ASSERT_EQ(regget(gpioa->mode_r, gpio_mode_n(2)), GPIO_MODE_ALTERNATE); - - ASSERT_EQ(regget(gpioa->af_rl, gpio_afsel_n(2)), 7); - ASSERT_EQ(regget(gpioa->af_rh, gpio_afsel_n(7)), 3); - - return 0; -} - -TEST(gpio_manager, bad_alternate) -{ - int ec; - - /* Pretending to start the USART. */ - gpio_enable_alternate_function( - GPIO_ALTERNATE_FUNCTION_USART2_RX, GPIO_PIN_PA2, &ec); - - ASSERT_EQ(ec, GPIO_ERROR_INVALID_PIN_FOR_ALTERNATE_FUNCTION); - - return 0; -} - -TEST(gpio_manager, bad_pin) -{ - int ec; - - /* Pretending to start the USART. */ - gpio_enable_alternate_function( - GPIO_ALTERNATE_FUNCTION_USART2_RX, 99, &ec); - - ASSERT_EQ(ec, GPIO_ERROR_INVALID_PIN); - - return 0; -} - -TEST(gpio_manager, alternate_then_reserve_fail) -{ - int ec; - - /* Pretending to start the USART. */ - gpio_enable_alternate_function( - GPIO_ALTERNATE_FUNCTION_USART2_TX, GPIO_PIN_PA2, &ec); - - ASSERT_EQ(ec, 0); - - gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; - reserve_gpio_pin(GPIO_PIN_PA2, &opts, &ec); - - ASSERT_EQ(ec, GPIO_ERROR_IN_USE); - - return 0; -} - -TEST(gpio_manager, get_gpio_pin_port_off) -{ - - gpio_port_config_t* cfg; - int off; - get_gpio_pin_port_off(GPIO_PIN_PA5, &cfg, &off); - - ASSERT_EQ(cfg, (void*)(GPIOA_BASE)); - ASSERT_EQ(off, 5); - - return 0; -} - -TEST(gpio_manager, sets_gpio_settings) -{ - gpio_pin_opts_t opts; - int ec; - - opts.mode = GPIO_MODE_OUTPUT; - opts.pull_dir = GPIO_PULL_DIR_NONE; - opts.output_opts.speed = GPIO_OUTPUT_SPEED_VERY_HIGH; - opts.output_opts.type = GPIO_OUTPUT_TYPE_PUSH_PULL; - - reserve_gpio_pin(GPIO_PIN_PA2, &opts, &ec); - ASSERT_EQ(ec, 0); - - gpio_port_config_t* gpioa = (gpio_port_config_t*) GPIOA_BASE; - - ASSERT_EQ(regget(gpioa->mode_r, gpio_mode_n(2)), GPIO_MODE_OUTPUT); - ASSERT_EQ(regget(gpioa->pupd_r, gpio_pupd_n(2)), GPIO_PULL_DIR_NONE); - ASSERT_EQ(regget(gpioa->ospeed_r, gpio_ospeed_n(2)), GPIO_OUTPUT_SPEED_VERY_HIGH); - ASSERT_EQ(regget(gpioa->otype_r, gpio_otype_n(2)), GPIO_OUTPUT_TYPE_PUSH_PULL); - - return 0; -} - -TEST(gpio_manager, gc) -{ - int ec; - gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; - - gpio_reserved_pin_t p1 = reserve_gpio_pin(GPIO_PIN_PA0, &opts, &ec); - ASSERT_EQ(ec, 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); - - gpio_reserved_pin_t p2 = reserve_gpio_pin(GPIO_PIN_PA1, &opts, &ec); - ASSERT_EQ(ec, 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); - - gpio_reserved_pin_t p3 = reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); - ASSERT_EQ(ec, 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); - - gpio_reserved_pin_t p4 = reserve_gpio_pin(GPIO_PIN_PB3, &opts, &ec); - ASSERT_EQ(ec, 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - gpio_reserved_pin_t p5 = reserve_gpio_pin(GPIO_PIN_PB1, &opts, &ec); - ASSERT_EQ(ec, 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - gpio_reserved_pin_t p6 = reserve_gpio_pin(GPIO_PIN_PB0, &opts, &ec); - ASSERT_EQ(ec, 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - release_gpio_pin(p1); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - release_gpio_pin(p2); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - release_gpio_pin(p3); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - release_gpio_pin(p4); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - release_gpio_pin(p5); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); - - release_gpio_pin(p6); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); - ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 0); - - return 0; -} diff --git a/02-usart/tests/test_irq.c b/02-usart/tests/test_irq.c deleted file mode 100644 index 3c4ee9c..0000000 --- a/02-usart/tests/test_irq.c +++ /dev/null @@ -1,43 +0,0 @@ -#include "test_harness.h" - -#include "arch/stm32l4xxx/peripherals/irq.h" -#include "arch/stm32l4xxx/peripherals/nvic.h" - -TEST(irq, nvic) -{ - interrupt_set_t is = { 0 }; - - interrupt_set_add(&is, IRQ_USART2); - interrupt_set_add(&is, IRQ_USART3); - - enable_interrupts(&is); - - ASSERT_EQ(is.irqs[1], 0xC0); - ASSERT_EQ(NVIC.ise_r[1], 0xC0); - - return 0; -} - -TEST(irq, nvic_edgecase) -{ - interrupt_set_t is = { 0 }; - interrupt_set_add(&is, IRQ_WWDG_IRQ); - interrupt_set_add(&is, IRQ_I2C1_ER); - - enable_interrupts(&is); - - ASSERT_EQ(is.irqs[0], 1); - ASSERT_EQ(NVIC.ise_r[0], 1); - ASSERT_EQ(is.irqs[1], 1); - ASSERT_EQ(NVIC.ise_r[1], 1); - - return 0; -} - -TEST(irq, enable_single_interrupt) -{ - enable_interrupt(IRQ_USART2); - ASSERT_EQ(NVIC.ise_r[1], 0x40); - - return 0; -} diff --git a/02-usart/tests/test_lib.c b/02-usart/tests/test_lib.c deleted file mode 100644 index 33076c2..0000000 --- a/02-usart/tests/test_lib.c +++ /dev/null @@ -1,21 +0,0 @@ -#include "test_harness.h" -#include "kern/lib.h" - -TEST(lib, hexify) -{ - char buf[10]; - - hexify(0xaaaaaaaa, buf); - ASSERT_EQ_STR(buf, "AAAAAAAA"); - - hexify(0xdddddddd, buf); - ASSERT_EQ_STR(buf, "DDDDDDDD"); - - hexify(0x02468ace, buf); - ASSERT_EQ_STR(buf, "02468ACE"); - - hexify(0xdeadbeef, buf); - ASSERT_EQ_STR(buf, "DEADBEEF"); - - return 0; -} diff --git a/02-usart/tests/test_memory.c b/02-usart/tests/test_memory.c deleted file mode 100644 index 04e9289..0000000 --- a/02-usart/tests/test_memory.c +++ /dev/null @@ -1,378 +0,0 @@ -#ifndef FOR_TESTING -#define FOR_TESTING -#endif - -#include - -#include "arch.h" -#include "test_harness.c" -#include "kern/common.h" -#include "kern/mem.h" - -struct TEST_STRUCT { - uint32_t array[3]; -}; - -struct TEST_STRUCT2 { - uint32_t array[10]; -}; - -/* Copy of the node structure. */ -typedef struct HALLOC_NODE { - union { - uint32_t header; - struct { - /* Is this memory block currently in use (hasn't been hfree'd) */ - bool used:1; - /* Number of words allocated. Does not include the header. */ - uint16_t size:12; - /* The location of the previous block (in WORDS from offest) */ - uint16_t prev:12; - uint8_t canary:7; - } PACKED; - }; - - uint8_t mem[]; /* The memory to use. */ -} halloc_node_t; - -extern halloc_node_t* halloc_start; - -static void wipeout_halloc() -{ - memset(halloc_start, 0, 1024); - halloc_start = NULL; -} - - -static struct TEST_STRUCT* new_test_struct() -{ - struct TEST_STRUCT* ret = halloc(sizeof(struct TEST_STRUCT)); - - ret->array[0] = 1; - ret->array[1] = 2; - ret->array[2] = 3; - - return ret; -} - -static struct TEST_STRUCT2* new_test_struct2() -{ - struct TEST_STRUCT2* ret = halloc(sizeof(struct TEST_STRUCT2)); - - for (int i = 0; i < 10; ++ i) { - ret->array[i] = i; - } - - return ret; -} - -#define ASSERT_CHAIN(t1, t2) \ - ASSERT_EQ(V(t1) + sizeof(*t1) + 4, V(t2)) - -TEST(memory, halloc) -{ - -#define V(x) ((void*)(x)) - struct TEST_STRUCT* test1 = new_test_struct(); - struct TEST_STRUCT2* test2 = new_test_struct2(); - struct TEST_STRUCT* test3 = new_test_struct(); - struct TEST_STRUCT2* test4 = new_test_struct2(); - struct TEST_STRUCT2* test5 = new_test_struct2(); - - ASSERT_TRUE(V(test1) != V(test2)); - ASSERT_TRUE(V(test2) != V(test3)); - ASSERT_TRUE(V(test3) != V(test1)); - ASSERT_TRUE(V(test2) != V(test5)); - ASSERT_TRUE(V(test4) != V(test5)); - - ASSERT_CHAIN(test1, test2); - ASSERT_CHAIN(test2, test3); - ASSERT_CHAIN(test3, test4); - ASSERT_CHAIN(test4, test5); - - - char buf[1024]; - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf( - stderr, - "Consistency check failed. (%s:%d)\n", - __FILE__, - __LINE__); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - - wipeout_halloc(); - - return 0; -} - -struct UNEVEN_STRUCT { - uint8_t arr[5]; -}; - -struct UNEVEN_STRUCT* new_uneven_struct() -{ - struct UNEVEN_STRUCT* ret = halloc(sizeof(struct UNEVEN_STRUCT)); - - ret->arr[0] = 1; - ret->arr[1] = 2; - ret->arr[2] = 3; - ret->arr[3] = 4; - ret->arr[4] = 5; - - return ret; -} - -#define size_for(n) \ - (((n) / 4) + ((n) % 4 != 0)) - -TEST(memory, uneven_halloc) -{ - if (halloc_start) { - wipeout_halloc(); - } - - struct UNEVEN_STRUCT* test1 = new_uneven_struct(); - struct UNEVEN_STRUCT* test2 = new_uneven_struct(); - - ASSERT_EQ(V(test1) + 12, test2); - - wipeout_halloc(); - - return 0; -} - -TEST(memory, halloc_free) -{ - if (halloc_start) { - wipeout_halloc(); - } - - struct TEST_STRUCT* test1 = new_test_struct(); - struct TEST_STRUCT2* test2 = new_test_struct2(); - struct TEST_STRUCT* test3 = new_test_struct(); - struct TEST_STRUCT2* test4 = new_test_struct2(); - struct TEST_STRUCT2* test5 = new_test_struct2(); - - hfree(test2); - hfree(test4); - hfree(test3); - hfree(test1); - hfree(test5); - - ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); - - test1 = new_test_struct(); - test2 = new_test_struct2(); - test3 = new_test_struct(); - test4 = new_test_struct2(); - test5 = new_test_struct2(); - - hfree(test1); - hfree(test3); - hfree(test2); - hfree(test4); - hfree(test5); - - ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); - - test1 = new_test_struct(); - test2 = new_test_struct2(); - test3 = new_test_struct(); - test4 = new_test_struct2(); - test5 = new_test_struct2(); - - hfree(test4); - hfree(test3); - hfree(test1); - hfree(test2); - hfree(test5); - - ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); - - wipeout_halloc(); - - return 0; -} - -TEST(memory, halloc_free_alloc2) -{ - if (halloc_start) { - wipeout_halloc(); - } - - struct TEST_STRUCT2* test1 = new_test_struct2(); - struct TEST_STRUCT2* test2 = new_test_struct2(); - - hfree(test1); - - struct TEST_STRUCT* test3 = new_test_struct(); - struct TEST_STRUCT* test4 = new_test_struct(); - - ASSERT_EQ(debug_halloc_get_next_ptr(test3), V(test4)); - - ASSERT_EQ( - // There should be a free block after test4. - debug_halloc_get_next_ptr(debug_halloc_get_next_ptr(test4)), - V(test2)); - - ASSERT_EQ( - // There should be a free block after test4. - debug_halloc_get_prev_ptr(debug_halloc_get_prev_ptr(test2)), - V(test4)); - - char buf[1024]; - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf(stderr, "Consistency check failed.\n"); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - - return 0; -} - -TEST(memory, relink_backref_after_free) -{ - if (halloc_start) { - wipeout_halloc(); - } - - struct TEST_STRUCT* test2 = new_test_struct(); - struct TEST_STRUCT* test3 = new_test_struct(); - - hfree(test2); - hfree(test3); - - char buf[1024]; - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf(stderr, "Consistency check failed.\n"); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - - return 0; -} - -TEST(memory, consistency_stress) -{ -#define NRUNS 500 - if (halloc_start) { - wipeout_halloc(); - } - - int i; - void* allocd[NRUNS] = { 0 }; - char buf[1024]; - - for (i = 0; i < NRUNS; ++ i) { - size_t nalloc = rand() % 20; - allocd[i] = halloc(nalloc); - - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf( - stderr, - "Consistency check failed. (At index=%d, %s:%d)\n", - i, - __FILE__, - __LINE__); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - - ASSERT_TRUE(allocd[i]); - - memset(allocd[i], 0xFF, nalloc); - size_t idx = rand() % NRUNS; - - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf( - stderr, - "Consistency check failed. (At index=%d, %s:%d)\n", - i, - __FILE__, - __LINE__); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - - hfree(allocd[idx]); - allocd[idx] = NULL; - - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf( - stderr, - "Consistency check failed. (At index=%d, %s:%d)\n", - i, - __FILE__, - __LINE__); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - - idx = rand() % NRUNS; - hfree(allocd[idx]); - allocd[idx] = NULL; - - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf( - stderr, - "Consistency check failed. (At index=%d, %s:%d)\n", - i, - __FILE__, - __LINE__); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - } - - for(i = 0; i < NRUNS; ++ i) { - if (allocd[i]) { - hfree(allocd[i]); - } - - if (debug_halloc_assert_consistency(buf, 1024)) { - fprintf( - stderr, - "Consistency check failed. (At index=%d, %s:%d)\n", - i, - __FILE__, - __LINE__); - fprintf(stderr, buf); - ASSERT_TRUE(false); - } - } - ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); - - return 0; -} - -TEST(memory, halloc_free_alloc) -{ - if (halloc_start) { - wipeout_halloc(); - } - - new_test_struct(); - struct TEST_STRUCT2* test2 = new_test_struct2(); - new_test_struct(); - struct TEST_STRUCT2* test4 = new_test_struct2(); - new_test_struct2(); - - hfree(test4); - - struct TEST_STRUCT2* test6 = new_test_struct2(); - - // test_6 should have been allocated in test_4's spot. - ASSERT_EQ(test6, test4); - - hfree(test2); - struct TEST_STRUCT* test7 = new_test_struct(); - struct TEST_STRUCT* test8 = new_test_struct(); - - // Test 2 was large enough to accomodate 3 smaller structs. - ASSERT_EQ(V(test7), V(test2)); - ASSERT_EQ(V(test8), V(test2) + sizeof(*test7) + 4); - - return 0; -} diff --git a/02-usart/tests/test_spi.c b/02-usart/tests/test_spi.c deleted file mode 100644 index cc25d6e..0000000 --- a/02-usart/tests/test_spi.c +++ /dev/null @@ -1,11 +0,0 @@ -#include "test_harness.h" - -#include "arch/stm32l4xxx/peripherals/spi.h" - -TEST(spi, smoke) -{ - __IO spi_t* spi = &SPI1; - spi->s_r = 1; - - return 0; -} diff --git a/02-usart/tests/test_usart.c b/02-usart/tests/test_usart.c deleted file mode 100644 index b19d687..0000000 --- a/02-usart/tests/test_usart.c +++ /dev/null @@ -1,22 +0,0 @@ -#include "test_harness.h" -#include "arch/stm32l4xxx/peripherals/usart.h" - -#include - -TEST(usart, enable_dma) -{ - __IO usart_t* usart = &USART1; - - usart->c_r3 = 0; - - usart_enable_dma(usart, USART_ENABLE_TX); - ASSERT_EQ(usart->c_r3, 128); - - usart_enable_dma(usart, USART_ENABLE_RX); - ASSERT_EQ(usart->c_r3, 192); - - usart_enable_dma(usart, USART_ENABLE_DISABLED); - ASSERT_EQ(usart->c_r3, 0); - - return 0; -} diff --git a/02.5-collatz/Makefile.preamble b/02.5-collatz/Makefile.preamble deleted file mode 100644 index 3c8a61b..0000000 --- a/02.5-collatz/Makefile.preamble +++ /dev/null @@ -1,21 +0,0 @@ -OPT?=-O -PREFIX?=arm-unknown-eabi- -CC=$(PREFIX)gcc -LD=$(PREFIX)ld -CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude -LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static - - -all: _$(PREFIX)_obs/main.elf - -_$(PREFIX)_obs/main.bin: _$(PREFIX)_obs/main.elf - $(PREFIX)objcopy -O binary _$(PREFIX)_obs/main.elf _$(PREFIX)_obs/main.bin - -flash: _$(PREFIX)_obs/main.bin - st-flash write _$(PREFIX)_obs/main.bin 0x8000000 - -clean: - rm -rf _*_obs - -genmake: - ./genmake.pl > Makefile diff --git a/02.5-collatz/genmake.pl b/02.5-collatz/genmake.pl deleted file mode 100755 index 341db3d..0000000 --- a/02.5-collatz/genmake.pl +++ /dev/null @@ -1,70 +0,0 @@ -#!/usr/bin/perl - -# This script is designed to introspect C files and generate a makefile to use. - -sub header_deps { - my $file = @_[0]; - my @headers; - - if (open(my $fh, '<:encoding(UTF-8)', $file)) { - print STDERR "\x1b[35m[Trace] - Reading file $file\x1b[00m\n"; - push(@headers, $file); - - while (<$fh>) { - /#include\s+"(.*)"\s*$/ && push(@headers, header_deps("include/$1")); - } - } - - return @headers; -} - -my @files = glob('src/*.c'); -my @obj_files; - -open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble") - or die "Missing Makefile.preamble"; - -while (<$fh>) { - print "$_"; -} - -# Emit a rule that will rerun genmake if the c files do not match. -my $idempotency_cmd = - "ls src/*.c include/*.h| sha1sum | awk '{print \$1}'"; - -my $idempotency_cmd_make = - "ls src/*.c include/*.h | sha1sum | awk '{print \$\$1}'"; - -print "IDEMPOTENCY_HASH=" . `$idempotency_cmd` . "\n"; - -my $arch_obs_dir = "_\$(PREFIX)_obs"; -print "CHEAT_PRE_MAKE := \$(shell mkdir -p $arch_obs_dir)\n"; - -foreach $file (@files) { - my $c_file = $file; - (my $file_no_ext = $file) =~ s/src\/(.*)\.c$/\1/g; - - my $obj_file = "$arch_obs_dir/${file_no_ext}.o"; - my $s_file = "${file_no_ext}.s"; - - push(@obj_files, $obj_file); - my @deps = header_deps($c_file); - - my $deps_as_join = join(" ", @deps); - - # Emit the rule to make the object file. - print "$obj_file: $deps_as_join\n\t"; - print '$(CC) -c ' . $c_file . ' -o ' . $obj_file . ' $(CFLAGS)' . "\n\n"; - - # Emit the rule to make the assembly file. - print "$s_file: $deps_as_join\n\t"; - print '$(CC) -S ' . $c_file . ' -o ' . $s_file . ' $(CFLAGS)' . "\n\n"; -} - -my $obj_files_deps = join(' ', @obj_files); -print "FORCE:\n\t\n\n"; -print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t"; -print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] " - . "&& ./genmake.pl > Makefile && make main.elf ) " - . "|| " - . "\$(LD) -o $arch_obs_dir/main.elf \$(LD_FLAGS) $obj_files_deps\n\n"; diff --git a/02.5-collatz/include/apb.h b/02.5-collatz/include/apb.h deleted file mode 100644 index 11fa7ab..0000000 --- a/02.5-collatz/include/apb.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef H__APB_ -#define H__APB_ - -#endif /* H__APB_ */ diff --git a/02.5-collatz/include/clock.h b/02.5-collatz/include/clock.h deleted file mode 100644 index 46ac6f2..0000000 --- a/02.5-collatz/include/clock.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef CLOCK_H__ -#define CLOCK_H__ - -#include -#include "rcc.h" - -#define PERIPH_BASE ((uint32_t)0x40000000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) -#define PWR_BASE (PERIPH_BASE + 0x7000) -#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ - -#ifndef __IO -#define __IO volatile -#endif - -typedef struct { - __IO uint32_t cr; - __IO uint32_t csr; -} pwr_t; - -// typedef struct { -// __IO uint32_t acr; -// __IO uint32_t pecr; -// __IO uint32_t pdkeyr; -// __IO uint32_t pekeyr; -// __IO uint32_t prgkeyr; -// __IO uint32_t optkeyr; -// __IO uint32_t sr; -// __IO uint32_t obr; -// __IO uint32_t wrpr; -// } flash_t; - -// #define FLASH (*(flash_t*) (FLASH_R_BASE)) -#define PWR (*(pwr_t*)(PWR_BASE)) - -/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */ -typedef enum { - PLL_DIVISOR_2 = 1, - PLL_DIVISOR_4 = 3, - PLL_DIVISOR_6 = 5, - PLL_DIVISOR_8 = 7, - PLL_DIVISOR_OFF = 0, -} pll_divisor_t; - -/* Valid values for the PLLP bits off the PLLCFG register. */ -typedef enum { - PLLP_DIVISOR_7 = 1, - PLLP_DIVISOR_17 = 3, - PLLP_DIVISOR_OFF = 0, -} pllp_divisor_t; - -/* Valid values for the PLLM bits of the PLLCFG register. */ -typedef enum { - PLLM_DIVISOR_1 = 0, - PLLM_DIVISOR_2 = 1, - PLLM_DIVISOR_3 = 2, - PLLM_DIVISOR_4 = 3, - PLLM_DIVISOR_5 = 4, - PLLM_DIVISOR_6 = 5, - PLLM_DIVISOR_7 = 6, - PLLM_DIVISOR_8 = 7, -} pllm_divisor_t; - -/* Possible sources for the input clock. */ -typedef enum { - PLL_SRC_NONE = 0, - PLL_SRC_MSI = 1, - PLL_SRC_HSI = 2, - PLL_SRC_HSE = 3, -} pll_src_t; - -/* Valid sources for the system clock. */ -typedef enum { - SYSTEM_CLOCK_SRC_MSI = 0, - SYSTEM_CLOCK_SRC_HSI = 1, - SYSTEM_CLOCK_SRC_HSE = 2, - SYSTEM_CLOCK_SRC_PLL = 3, -} system_clock_src_t; - -#define E_BADPLLN (-2) -#define E_BADPLLP_DIV (-1) -#define E_TIMEOUT (-3) -#define E_NOT_OFF (-4) -#define E_BAD_ARG (-5) - -#define enable_hsi(rcc, enabled) do { \ - if (enabled) { \ - (rcc)->c_r |= BIT(8); \ - } else { \ - (rcc)->c_r &= ~BIT(8); \ - } \ -} while(0) - -/* - * Sets the system clock to a full 80Mhz. - */ -int set_system_clock_MHz(uint8_t mhz); - -/* - * Set the PLL on. - */ -int pll_on(); - -/* - * Set the PLL off. - */ -int pll_off(); - -/* - * Sets the source of the system clock. - */ -int set_system_clock_src(system_clock_src_t src); - -/* - * Configure the PLL. - */ -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */); - -#endif /* CLOCK_H__ */ diff --git a/02.5-collatz/include/common.h b/02.5-collatz/include/common.h deleted file mode 100644 index 9d5c7cd..0000000 --- a/02.5-collatz/include/common.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef COMMON__H -#define COMMON__H - -#include - -/* Define __IO to be volatile if it's not already. */ -#ifndef __IO -#define __IO volatile -#endif - -#define bool int -#ifndef __cplusplus -#define true 1 -#define false 0 -#endif - -#define PACKED __attribute__((packed)) -#define BIT(n) (1 << (n)) - -#define RESERVED_CONCAT_IMPL(x, y) x ## y -#define RESERVED_MACRO_CONCAT(x, y) RESERVED_CONCAT_IMPL(x, y) -#define RESERVED(n) \ - bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) :n - -#define RESERVE(type) \ - __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__) - -typedef uint32_t bits_t; - -#endif /* COMMON_H */ diff --git a/02.5-collatz/include/delay.h b/02.5-collatz/include/delay.h deleted file mode 100644 index 65a26d6..0000000 --- a/02.5-collatz/include/delay.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef H__DELAY__ -#define H__DELAY__ - -#include - -/* - * Loops and count-downs the delay, the time this takes depends on the speed - * of the clock. - */ -void delay(uint32_t delay); - -#endif /* H__DELAY__ */ diff --git a/02.5-collatz/include/flash.h b/02.5-collatz/include/flash.h deleted file mode 100644 index a163a25..0000000 --- a/02.5-collatz/include/flash.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef H__FLASH_ -#define H__FLASH_ - -#include "common.h" - -/* - * Header file for dealing with flash. - */ - -#define FLASH_BASE 0x40022000 - -typedef struct { - __IO uint32_t ac_r; /* Flash access control register. */ - - /* TODO fill out the rest. */ -} PACKED flash_t; - -#define FLASH (*(__IO flash_t*)FLASH_BASE) - -#endif /* H__FLASH_ */ diff --git a/02.5-collatz/include/gpio.h b/02.5-collatz/include/gpio.h deleted file mode 100644 index 62169c6..0000000 --- a/02.5-collatz/include/gpio.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef GPIO_H__ -#define GPIO_H__ - -#include "common.h" -#include "rcc.h" - -#include - -/* - * Possible GPIO ports. - */ -typedef enum { - GPIO_PORT_A = 0, - GPIO_PORT_B = 1, - GPIO_PORT_C = 2, - GPIO_PORT_D = 3 -} gpio_port_number_t; - -/* - * Structure defining the layout of the layout of the GPIO registers on the - * stm32l432 development board. - */ -typedef struct GPIO_PORT_STR { - __IO uint32_t mode_r; /* Mode register */ - __IO uint32_t otype_r; - __IO uint32_t ospeed_r; - __IO uint32_t pupd_r; - __IO uint32_t id_r; - __IO uint32_t output_r; - __IO uint32_t bsr_r; - __IO uint32_t lck_r; - __IO uint32_t af_rl; - __IO uint32_t af_rh; -} PACKED gpio_port_t; - -/* - * Enum defining the PINs in a GPIO port. Each port has 16 pins to use in - * the stm32l432. - */ -typedef enum GPIO_PIN_ENUM { - PIN_0 = 0, - PIN_1 = 1, - PIN_2 = 2, - PIN_3 = 3, - PIN_4 = 4, - PIN_5 = 5, - PIN_6 = 6, - PIN_7 = 7, - PIN_8 = 8, - PIN_9 = 9, - PIN_10 = 10, - PIN_11 = 11, - PIN_12 = 12, - PIN_13 = 13, - PIN_14 = 14, - PIN_15 = 15 -} gpio_pin_t; - -/* Alternate function number. */ -typedef enum { - AFN_0 = 0, - AFN_1 = 1, - AFN_2 = 2, - AFN_3 = 3, - AFN_4 = 4, - AFN_5 = 5, - AFN_6 = 6, - AFN_7 = 7, - AFN_8 = 8, - AFN_9 = 9, - AFN_10 = 10, - AFN_11 = 11, - AFN_12 = 12, - AFN_13 = 13, - AFN_14 = 14, - AFN_15 = 15 -} alternate_function_t; - -/* - * Enum defining the pin modes that are possible. - */ -typedef enum { - MODE_INPUT = 0, - MODE_OUTPUT = 1, - MODE_ALTERNATE = 2, - MODE_ANALOG = 3 -} gpio_pin_mode_t; - -/* - * Enum defining the pin speeds that are possible. - */ -typedef enum { - SPEED_2MHZ = 0, - SPEED_10MHZ = 1, - SPEED_50MHZ = 3, -} speed_t; - -/* - * Structure defining an OUTPUT pin. Structurally equivalent to the input pin, - * but can be used in a slightly type-safe manner. - */ -typedef struct { - __IO gpio_port_t* gpio_port; - gpio_pin_t pin; -} gpio_output_pin_t; - -/* - * Sets the mode on a GPIO pin. - * - * gpio_port: the gpio port to use. - * pin: the pin number to set. - * pin_mode: the mode to set the pin to. - */ -void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode); - -/* - * Sets the given GPIO pin to be an output pin. Returns an output_pin struct - * corresponding to - */ -gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, gpio_pin_t pin); - -/* - * Sets an output pin on or off. - * - * pin: the pin to toggle. - * onoff: 0 for off, non-zero of on. - */ -void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff); - -#define pin_on(p) set_gpio_output_pin(p, 1) - -#define pin_off(p) set_gpio_output_pin(p, 0) - -/* - * Enables a GPIO port and returns a reference to the register definition - * of that GPIO port. - */ -__IO gpio_port_t* enable_gpio(gpio_port_number_t number); - -/* Sets the alternate function for a GPIO pin. */ -void set_gpio_alternate_function( - __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn); - -#endif /* GPIO_H__ */ diff --git a/02.5-collatz/include/isr_vector.h b/02.5-collatz/include/isr_vector.h deleted file mode 100644 index 3e55f52..0000000 --- a/02.5-collatz/include/isr_vector.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef h__ISR_VECTOR_H__ -#define h__ISR_VECTOR_H__ - -/* - * Include file for interrupt service routines. - */ - -/* - * The interrupt service routines. These link in the function `main` as the - * main function. - */ -extern const void* isr_vector[]; - -/* - * Defines an error state. This loops forever and defines a distinct flashing - * pattern to let the user know an unhandled ISR happened. - */ -void unhandled_isr(); - -#endif /* h___ISR_VECTOR_H__ */ diff --git a/02.5-collatz/include/rcc.h b/02.5-collatz/include/rcc.h deleted file mode 100644 index 7ed4dee..0000000 --- a/02.5-collatz/include/rcc.h +++ /dev/null @@ -1,93 +0,0 @@ -#ifndef H__RCC_ -#define H__RCC_ - -#include "common.h" -#include - -#define RCC_BASE ((uint32_t)0x40021000) - -typedef struct { - __IO uint32_t c_r; /* Clock control register. 0x00 */ - __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ - __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ - __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ - __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ - - __IO uint32_t reserved_1; /* Not used. offset 0x14. */ - - __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ - __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ - __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ - - __IO uint32_t reserved_2; /* Not used. offset 0x24. */ - - __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ - __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ - __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ - - __IO uint32_t reserved_3; /* Not used. offset 0x34. */ - - __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */ - __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */ - __IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */ - - __IO uint32_t reserved_4; /* Not used. offset 0x44. */ - - __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ - __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ - __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ - - __IO uint32_t reserved_5; /* Not used. offset 0x54. */ - - __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ - __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ - __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ - - __IO uint32_t reserved_6; /* Not used. offset 0x64. */ - - __IO uint32_t ahb1smen_r; /* 0x68 */ - __IO uint32_t ahb2smen_r; /* 0x6c */ - __IO uint32_t ahb3smen_r; /* 0x70 */ - - __IO uint32_t reserved_7; - - __IO uint32_t apb1smen_r1; /* 0x78 */ - __IO uint32_t apb1smen_r2; /* 0x7c */ - __IO uint32_t apb2smen_r; /* 0x80 */ - - __IO uint32_t reserved_8; - - __IO uint32_t ccip_r; /* 0x88 */ -} PACKED rcc_t; - -#define RCC (*(__IO rcc_t*)RCC_BASE) - -/* Macros to operate on the RCC registers. */ - -/* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hse(rcc, e) \ - do { \ - if (e) { \ - (rcc).c_r |= 1 << 16; \ - } else { \ - (rcc).c_r &= ~(1 << 16); \ - } \ - } while (0) - -/* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */ -#define set_hsi(rcc, e) \ - do { \ - if (e) { \ - (rcc).c_r |= 1 << 8; \ - } else { \ - (rcc).c_r &= ~(1 << 8); \ - } \ - } while (0) - -/* Checks to see if the hse is ready. */ -#define hse_ready(rcc) ((rcc).c_r & (1 << 17)) - -/* Checks to see if the hse is ready. */ -#define hsi_ready(rcc) ((rcc).c_r & (1 << 10)) - -#endif diff --git a/02.5-collatz/include/spin.h b/02.5-collatz/include/spin.h deleted file mode 100644 index a23d25b..0000000 --- a/02.5-collatz/include/spin.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef H__SPIN_ -#define H__SPIN_ - -#include - -/* - * Flash a code on the status LED. - * - * The flash codes a binary from MSB to LSB. A long flash is a 1, a short flash - * is a 0. Each independent flashing is succeced by a break of 4 times that - * of a long flash. - */ -void spin(uint32_t base_delay, uint8_t code); - -#endif /* H__SPIN_ */ diff --git a/02.5-collatz/include/usart.h b/02.5-collatz/include/usart.h deleted file mode 100644 index 257aab6..0000000 --- a/02.5-collatz/include/usart.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef H__USART_ -#define H__USART_ - -#include "common.h" -#include "rcc.h" - -#include - -/* - * Possibel USART clock sources. - */ -typedef enum { - USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */ - USART_CLK_SRC_SYSCLK = 1, /* System clock. */ - USART_CLK_SRC_HSI16 = 2, /* 16MHz oscillator. */ - USART_CLK_SRC_LSE = 3 /* Low power 32kHz clock. */ -} usart_clk_src_t; - -typedef struct { - /* USART configuration registers 0x04 - 0x0c. */ - union { - uint32_t c_r1; - struct { - bits_t ue:1; /* UART enable */ - bits_t uesm:1; /* UART enabled in stop mode. */ - bits_t re:1; /* reciever enabled. */ - bits_t te:1; /* transmitter enabled. */ - bits_t idleie:1; /* Idle interrupt enabled. */ - bits_t rxneie:1; /* RXNEIE RXNE interrupt enable. */ - bits_t tcie:1; - bits_t txeie:1; - bits_t peie:1; - bits_t ps:1; - bits_t pce:1; - bits_t wake:1; - bits_t m0:1; - bits_t mme:1; - bits_t cmie:1; - bits_t over8:1; - bits_t dedt:4; - bits_t deat:4; - bits_t rtoie:1; - bits_t eobie:1; - bits_t m1:1; - bits_t reserved:3; - } PACKED c1_bf; - }; - uint32_t c_r2; - uint32_t c_r3; - - /* USART baud rate register. */ - uint32_t br_r; - uint32_t gtp_r; - uint32_t rto_r; - uint32_t rq_r; - uint32_t is_r; - uint32_t ic_r; - uint32_t rd_r; - uint32_t td_r; -} usart_t; - -#define USART1 (* (__IO usart_t*) 0x40013800) -#define USART2 (* (__IO usart_t*) 0x40004400) -typedef enum { - OVERSAMPLE_8, - OVERSAMPLE_16 -} oversampling_mode_t; - -static inline void usart_set_divisor( - __IO usart_t* usart, - uint32_t usartdiv) -{ - if (usart->c_r1 & (1 << 15)) { - /* OVER8 is set. */ - usart->br_r = - (usartdiv & ~7) | - ((usartdiv & 7) >> 1); - } else { - /* OVER8 is not set. */ - usart->br_r = usartdiv; - } -} - -static inline void usart_set_oversampling_mode( - __IO usart_t* usart, - oversampling_mode_t mode) -{ - if (mode == OVERSAMPLE_8) { - usart->c_r1 |= 1 << 15; - } else { - usart->c_r1 &= ~(1 << 15); - } -} - -typedef enum { - USART_PARITY_DISABLED = 0, - USART_PARITY_EVEN = 2 << 9, - USART_PARITY_ODD = 3 << 9, -} usart_parity_t; - -typedef enum { - USART_ENABLE_TX = 0x02, - USART_ENABLE_RX = 0x01, - USART_ENABLE_DISABLED = 0x00, -} usart_enable_t; - -void usart_set_parity(__IO usart_t* usart, usart_parity_t parity); - -void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled); - -/* - * Send a byte on the usart, This command blocks until the data - * is fully sent. - */ -void usart_transmit_byte(__IO usart_t* usart, uint8_t byte); - -void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); - -void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable); - -void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); - -void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable); - -void usart_transmit_bytes( - __IO usart_t* usart, const uint8_t* bytes, uint32_t n); - -void usart_transmit_str(__IO usart_t* usart, const char* str); - - -#endif /* H__USART_ */ diff --git a/02.5-collatz/linker/linker_script.ld b/02.5-collatz/linker/linker_script.ld deleted file mode 100644 index 348d03b..0000000 --- a/02.5-collatz/linker/linker_script.ld +++ /dev/null @@ -1,36 +0,0 @@ -MEMORY -{ - flash : org = 0x08000000, len = 256k - sram1 : org = 0x20000000, len = 48k - sram2 : org = 0x10000000, len = 16k -} - -SECTIONS -{ - /* This is where the code goes. */ - . = ORIGIN(flash); - .text : { - *(.vectors); /* All .vector sections go here. */ - *(.text); /* All .text sections go here. */ - } >flash - - .data : { - /* Data segment as defined in the flash. */ - INIT_DATA_VALUES = LOADADDR(.data); - - /* Data segment where it will be in memory. */ - DATA_SEGMENT_START = .; - *(.data); - DATA_SEGMENT_STOP = .; - - /* Align by 4 so we can optimize the copier to use uint32's. */ - . = ALIGN(0x04); - } >sram1 AT>flash - - BSS_START = .; - .bss : { - *(.bss); - . = ALIGN(0x04); - } > sram1 - BSS_END = .; -} diff --git a/02.5-collatz/src/clock.c b/02.5-collatz/src/clock.c deleted file mode 100644 index 75bac97..0000000 --- a/02.5-collatz/src/clock.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file sets the system clock to its full glory of 80Mhz - */ - -#include "clock.h" -#include -#include "flash.h" -#include "gpio.h" -#include "spin.h" - -#define TIMEOUT 10000 - -int pll_off() -{ - uint32_t c; - - RCC.c_r &= ~BIT(24); /* Turn off pll. */ - for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c) - ; /* Wait for OFF. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int pll_on() -{ - uint32_t c; - - RCC.c_r |= BIT(24); /* Turn on PLL. */ - for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c) - ; /* Wait for RDY. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */) -{ - if (RCC.c_r & BIT(25)) { - /* PLL must be off to configure it. */ - return E_NOT_OFF; - } - - /* Make sure inputs are valid. */ - if (pllp_div_factor == 1 || pllp_div_factor > 31) { - return E_BADPLLP_DIV; - } - if (plln < 8 || plln > 86) { - return E_BADPLLN; - } - - RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | - (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); - - return 0; -} - -int set_system_clock_MHz(uint8_t mhz) -{ - /* Set the source of the system colck to MSI temporarily. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_MSI); - - if (mhz <= 8 || mhz > 80) { - return E_BAD_ARG; - } - - pll_off(); - - configure_pll( - 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, - PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, - - /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. - */ - mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, - PLL_SRC_MSI /* pll src | 04 Mhz */); - - pll_on(); - - /* Configure the flash to have 4 wait states. This is required at - * 80 MHz. */ - FLASH.ac_r &= ~0x07; - FLASH.ac_r |= 0x04; - - /* Set the source of the system colck to PLL. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_PLL); - return 0; -} - -int set_system_clock_src(system_clock_src_t src) -{ - uint8_t value = RCC.cfg_r & ~0x03; - RCC.cfg_r = value | src; -} diff --git a/02.5-collatz/src/delay.c b/02.5-collatz/src/delay.c deleted file mode 100644 index 2a16d47..0000000 --- a/02.5-collatz/src/delay.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "delay.h" - -void delay(uint32_t delay) -{ - while (delay--) { - /* needed to keep the compiler from optimizing away the loop. */ - asm volatile(""); - } -} diff --git a/02.5-collatz/src/gpio.c b/02.5-collatz/src/gpio.c deleted file mode 100644 index 02933b7..0000000 --- a/02.5-collatz/src/gpio.c +++ /dev/null @@ -1,52 +0,0 @@ -#include "gpio.h" -#include "rcc.h" - -/* - * Sets the mode of a pin on a gpio por. - */ -void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode) -{ - /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */ - gpio_port->mode_r &= ~(0x03 << pin * 2); - gpio_port->mode_r |= mode << pin * 2; -} - -gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, gpio_pin_t pin) -{ - set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT); - - return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin}; -} - -void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff) -{ - if (onoff) { - pin.gpio_port->output_r |= 1 << pin.pin; - } else { - pin.gpio_port->output_r &= ~(1 << pin.pin); - } -} - -void set_gpio_alternate_function( - __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn) -{ - __IO uint32_t* reg; - if (gpio_pin < 8) { - reg = &(port->af_rl); - } else { - reg = &(port->af_rh); - gpio_pin -= 8; - } - - uint32_t tmp = *reg & (~0x0f << gpio_pin * 4); - *reg = tmp | (afn << gpio_pin * 4); -} - -#define GPIO_PORTS_BASE_ADDR ((uint8_t*)0x48000000) -__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) -{ - RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ - return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); -} diff --git a/02.5-collatz/src/isr_vector.c b/02.5-collatz/src/isr_vector.c deleted file mode 100644 index ab38dc2..0000000 --- a/02.5-collatz/src/isr_vector.c +++ /dev/null @@ -1,165 +0,0 @@ -#include "isr_vector.h" -#include "delay.h" -#include "gpio.h" - -/* Forward-declare the main function. This is implemented in main.c. */ -void main(); - -/* These are defined in the linker script. */ -extern uint32_t INIT_DATA_VALUES; -extern uint32_t DATA_SEGMENT_START; -extern uint32_t DATA_SEGMENT_STOP; -extern uint32_t BSS_START; -extern uint32_t BSS_END; - -/* - * Runs before main. Initializes the data and bss segments by loading them - * into memory. - */ -void init() -{ - uint32_t* src; - uint32_t* dest; - - src = &INIT_DATA_VALUES; - dest = &DATA_SEGMENT_START; - - /* Copy the values from flash into the data segment. */ - while (dest != &DATA_SEGMENT_STOP) { - *(dest++) = *(src++); - } - - /* Everything in the BSS segment is set to zero. */ - dest = &BSS_START; - while (dest != &BSS_END) { - *(dest++) = 0; - } - - /* Jump to main. */ - main(); -} - -const void* vectors[] __attribute__((section(".vectors"))) = { - (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ - init, /* Reset handler */ - unhandled_isr, /* NMI */ - unhandled_isr, /* Hard Fault */ - unhandled_isr, /* MemManage */ - unhandled_isr, /* BusFault */ - unhandled_isr, /* UsageFault */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* SVCall */ - unhandled_isr, /* Debug */ - unhandled_isr, /* Reserved */ - unhandled_isr, /* PendSV */ - unhandled_isr, /* SysTick */ - - /* External interrupt handlers follow */ - unhandled_isr, /* 0 WWDG */ - unhandled_isr, /* 1 PVD */ - unhandled_isr, /* 2 TAMP_SAMP */ - unhandled_isr, /* 3 RTC_WKUP */ - unhandled_isr, /* 4 FLASH */ - unhandled_isr, /* 5 RCC */ - unhandled_isr, /* 6 EXTI0 */ - unhandled_isr, /* 7 EXTI1 */ - unhandled_isr, /* 8 EXTI2 */ - unhandled_isr, /* 9 EXTI3 */ - unhandled_isr, /* 10 EXTI4 */ - unhandled_isr, /* 11 DMA_CH1 */ - unhandled_isr, /* 12 DMA_CH2 */ - unhandled_isr, /* 13 DMA_CH3 */ - unhandled_isr, /* 14 DMA_CH4 */ - unhandled_isr, /* 15 DMA_CH5 */ - unhandled_isr, /* 16 DMA_CH6 */ - unhandled_isr, /* 17 DMA_CH7 */ - unhandled_isr, /* 18 ADC1 */ - unhandled_isr, /* 19 CAN_TX */ - unhandled_isr, /* 20 CAN_RX0 */ - unhandled_isr, /* 21 CAN_RX1 */ - unhandled_isr, /* 22 CAN_SCE */ - unhandled_isr, /* 23 EXTI9_5 */ - unhandled_isr, /* 24 TIM1_BRK/TIM15 */ - unhandled_isr, /* 25 TIM1_UP/TIM16 */ - unhandled_isr, /* 26 TIM1_TRG_COM */ - unhandled_isr, /* 27 TIM1_CC */ - unhandled_isr, /* 28 TIM2 */ - unhandled_isr, /* 29 Reserved */ - unhandled_isr, /* 30 Reserved */ - unhandled_isr, /* 31 I2C1_EV */ - unhandled_isr, /* 32 I2C1_ER */ - unhandled_isr, /* 33 I2C2_EV */ - unhandled_isr, /* 34 I2C2_ER */ - unhandled_isr, /* 35 SPI1 */ - unhandled_isr, /* 36 SPI2 */ - unhandled_isr, /* 37 USART1 */ - unhandled_isr, /* 38 USART2 */ - unhandled_isr, /* 39 USART3 */ - unhandled_isr, /* 40 EXTI15_10 */ - unhandled_isr, /* 41 RTCAlarm */ - unhandled_isr, /* 42 Reserved */ - unhandled_isr, /* 43 Reserved */ - unhandled_isr, /* 44 Reserved */ - unhandled_isr, /* 45 Reserved */ - unhandled_isr, /* 46 Reserved */ - unhandled_isr, /* 47 Reserved */ - unhandled_isr, /* 48 Reserved */ - unhandled_isr, /* 49 SDMMC1 */ - unhandled_isr, /* 50 Reserved */ - unhandled_isr, /* 51 SPI3 */ - unhandled_isr, /* 52 Reserved */ - unhandled_isr, /* 53 Reserved */ - unhandled_isr, /* 54 TIM6_DACUNDER */ - unhandled_isr, /* 55 TIM7 */ - unhandled_isr, /* 56 DMA2_CH1 */ - unhandled_isr, /* 57 DMA2_CH2 */ - unhandled_isr, /* 58 DMA2_CH3 */ - unhandled_isr, /* 59 DMA2_CH4 */ - unhandled_isr, /* 60 DMA2_CH5 */ - unhandled_isr, /* 61 Reserved */ - unhandled_isr, /* 62 Reserved */ - unhandled_isr, /* 63 Reserved*/ - unhandled_isr, /* 64 COMP */ - unhandled_isr, /* 65 LPTIM1 */ - unhandled_isr, /* 66 LPTIM2 */ - unhandled_isr, /* 67 USB_FS */ - unhandled_isr, /* 68 DMA_CH6 */ - unhandled_isr, /* 69 DMA_CH7 */ - unhandled_isr, /* 70 LPUART1 */ - unhandled_isr, /* 71 QUADSPI */ - unhandled_isr, /* 72 I2C3_EV */ - unhandled_isr, /* 73 I2C3_ER */ - unhandled_isr, /* 74 SAI1 */ - unhandled_isr, /* 75 Reserved */ - unhandled_isr, /* 76 SWPMI1 */ - unhandled_isr, /* 77 TSC */ - unhandled_isr, /* 78 Reserved */ - unhandled_isr, /* 79 AES */ - unhandled_isr, /* 80 RNG */ - unhandled_isr, /* 81 FPU */ - unhandled_isr /* 82 CRS */ -}; - -/* - * Does nothing ... forever. - */ -void unhandled_isr() -{ - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - for (;;) { - /* Flash in a distinct pattern to know that something went wrong. */ - - pin_off(pin3); - delay(1000000); - pin_on(pin3); - delay(1000000); - pin_off(pin3); - delay(1000000); - pin_on(pin3); - delay(5000000); - } -} diff --git a/02.5-collatz/src/main.c b/02.5-collatz/src/main.c deleted file mode 100644 index 5af52ed..0000000 --- a/02.5-collatz/src/main.c +++ /dev/null @@ -1,93 +0,0 @@ - -#include "clock.h" -#include "delay.h" -#include "gpio.h" -#include "spin.h" -#include "usart.h" - -volatile uint32_t delay_amt = 20000000 / 4; - -int enable_usart2(uint32_t baud_rate) -{ - __IO gpio_port_t* port_a = enable_gpio(GPIO_PORT_A); - enable_hsi(&RCC, true); - - // Turn on the clock for the USART2 peripheral - set_usart2_clock_src(&RCC, USART_CLK_SRC_HSI16); - set_usart2_clock_enabled(&RCC, true); - - // Configure the I/O pins. Will use PA2 as TX and PA15 as RX so setup for - // alternate function - set_gpio_pin_mode(port_a, PIN_2, MODE_ALTERNATE); - set_gpio_pin_mode(port_a, PIN_15, MODE_ALTERNATE); - set_gpio_alternate_function(port_a, PIN_2, AFN_7); - set_gpio_alternate_function(port_a, PIN_15, AFN_3); - - // De-assert reset of USART2 - RCC.apb1rst1_r &= ~BIT(17); - - // Configure the USART - // disable USART first to allow setting of other control bits - // This also disables parity checking and enables 16 times oversampling - - USART2.c_r1 = 0; - USART2.c_r2 = 0; - USART2.c_r3 = 0; - - usart_set_divisor(&USART2, 16000000 / baud_rate); - usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX); -} - -int enable_usart1(uint32_t baud_rate) -{ - /* Enable the GPIO bus. */ - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - - /* Enable the USART clock. */ - RCC.apb2en_r |= BIT(14); - - /* == Configure the IO Pins. == */ - - /* GPIO D5 (Port B pin 6) is USART1 Tx, - * GPIO D6 (Port B pin 7) is USART1 Rx. */ - set_gpio_pin_mode(port_b, PIN_6, MODE_ALTERNATE); - set_gpio_pin_mode(port_b, PIN_7, MODE_ALTERNATE); - - /* Set the GPIO pins to use the USART alternate function. */ - set_gpio_alternate_function(port_b, PIN_6, AFN_7); - set_gpio_alternate_function(port_b, PIN_7, AFN_7); - - RCC.apb2rst_r &= ~BIT(14); /* De-assert reset of USART1 */ - - uint32_t baud_rate_div = 80000000 / baud_rate; - USART1.c_r1 = 0; - USART1.c_r2 = 0; - USART1.c_r3 = 0; - USART1.br_r = baud_rate_div; - - USART1.c_r1 |= BIT(3) | BIT(2); - USART1.c_r1 |= BIT(0); - - /* Enable the transmitter and the receiver. */ - usart_set_enabled(&USART1, USART_ENABLE_TX); - asm volatile(" cpsie i "); -} - -/* Main function. This gets executed from the interrupt vector defined above. */ -int main() -{ - /* Enable the GPIO port B. */ - - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - gpio_output_pin_t pin1 = set_gpio_pin_output(port_b, PIN_1); - - /* Enable a higher clock frequency. */ - set_system_clock_MHz(80); - - enable_usart2(115200); - - pin_on(pin3); - usart_transmit_str(&USART2, "Hello, World\n"); - for(;;); -} diff --git a/02.5-collatz/src/spin.c b/02.5-collatz/src/spin.c deleted file mode 100644 index fbd16b6..0000000 --- a/02.5-collatz/src/spin.c +++ /dev/null @@ -1,49 +0,0 @@ -#include "spin.h" -#include "delay.h" -#include "gpio.h" - -#define SHORT_DELAY 200000 -#define LONG_DELAY (SHORT_DELAY * 2) - -static void flash_bit( - uint32_t base, gpio_output_pin_t out_pin, - uint8_t bit /* 0 => 0, non-zero => 1 */) -{ - pin_on(out_pin); - if (bit) { - delay(base * 2); - } else { - delay(base); - } - pin_off(out_pin); - delay(base); -} - -void spin(uint32_t base, uint8_t c) -{ - uint8_t code; - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - - for (;;) { - code = c; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - - delay(base * 4); - } -} diff --git a/02.5-collatz/src/usart.c b/02.5-collatz/src/usart.c deleted file mode 100644 index eddfbe7..0000000 --- a/02.5-collatz/src/usart.c +++ /dev/null @@ -1,80 +0,0 @@ -#include "usart.h" -#include "delay.h" - -void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) -{ - rcc->ccip_r = rcc->ccip_r & (~0x03) | usart_clk_src; -} - -void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) -{ - rcc->ccip_r = rcc->ccip_r & ~(0x03 << 2) | (usart_clk_src << 2); -} - -void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable) -{ - if (enable) { - rcc->apb1en1_r |= BIT(17); - } else { - rcc->apb1en1_r &= ~BIT(17); - } -} - -void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable) -{ - if (enable) { - rcc->apb2en_r |= BIT(14); - } else { - rcc->apb2en_r &= ~BIT(14); - } -} - -void usart_set_parity(__IO usart_t* usart, usart_parity_t parity) -{ - uint32_t c_r1 = usart->c_r1; - c_r1 &= ~(0x3 << 9); - c_r1 |= parity; - usart->c_r1 = c_r1; -} - -void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled) -{ - uint32_t c_r1 = usart->c_r1; - - if (!enabled) { - usart->c1_bf.ue = 0; - } else { - /* Set the rx enabled. */ - usart->c1_bf.re = !!(enabled & USART_ENABLE_RX); - usart->c1_bf.te = !!(enabled & USART_ENABLE_TX); - usart->c1_bf.ue = 1; - } -} - -void usart_transmit_byte(__IO usart_t* usart, uint8_t byte) -{ - usart->td_r = byte; - /* Per the manual, when bit 7 of the IS register is set, then the usart - * data has been sent to the shift register. - * - * This bit is cleared by writing to the TD register. */ - while (!(usart->is_r & BIT(7))) - ; -} - -void usart_transmit_bytes(__IO usart_t* usart, const uint8_t* bytes, uint32_t n) -{ - while (n --) { - usart_transmit_byte(usart, *(bytes ++)); - } -} - -void usart_transmit_str(__IO usart_t* usart, const char* str) -{ - while (*str) { - if (*str == '\n') { - usart_transmit_byte(usart, '\r'); - } - usart_transmit_byte(usart, *(str ++)); - } -} diff --git a/02.5-collatz/src/vector.c b/02.5-collatz/src/vector.c deleted file mode 100644 index e69de29..0000000 diff --git a/03-refactor/Makefile.preamble b/03-refactor/Makefile.preamble deleted file mode 100644 index 3c8a61b..0000000 --- a/03-refactor/Makefile.preamble +++ /dev/null @@ -1,21 +0,0 @@ -OPT?=-O -PREFIX?=arm-unknown-eabi- -CC=$(PREFIX)gcc -LD=$(PREFIX)ld -CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude -LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static - - -all: _$(PREFIX)_obs/main.elf - -_$(PREFIX)_obs/main.bin: _$(PREFIX)_obs/main.elf - $(PREFIX)objcopy -O binary _$(PREFIX)_obs/main.elf _$(PREFIX)_obs/main.bin - -flash: _$(PREFIX)_obs/main.bin - st-flash write _$(PREFIX)_obs/main.bin 0x8000000 - -clean: - rm -rf _*_obs - -genmake: - ./genmake.pl > Makefile diff --git a/03-refactor/genmake.pl b/03-refactor/genmake.pl deleted file mode 100755 index 341db3d..0000000 --- a/03-refactor/genmake.pl +++ /dev/null @@ -1,70 +0,0 @@ -#!/usr/bin/perl - -# This script is designed to introspect C files and generate a makefile to use. - -sub header_deps { - my $file = @_[0]; - my @headers; - - if (open(my $fh, '<:encoding(UTF-8)', $file)) { - print STDERR "\x1b[35m[Trace] - Reading file $file\x1b[00m\n"; - push(@headers, $file); - - while (<$fh>) { - /#include\s+"(.*)"\s*$/ && push(@headers, header_deps("include/$1")); - } - } - - return @headers; -} - -my @files = glob('src/*.c'); -my @obj_files; - -open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble") - or die "Missing Makefile.preamble"; - -while (<$fh>) { - print "$_"; -} - -# Emit a rule that will rerun genmake if the c files do not match. -my $idempotency_cmd = - "ls src/*.c include/*.h| sha1sum | awk '{print \$1}'"; - -my $idempotency_cmd_make = - "ls src/*.c include/*.h | sha1sum | awk '{print \$\$1}'"; - -print "IDEMPOTENCY_HASH=" . `$idempotency_cmd` . "\n"; - -my $arch_obs_dir = "_\$(PREFIX)_obs"; -print "CHEAT_PRE_MAKE := \$(shell mkdir -p $arch_obs_dir)\n"; - -foreach $file (@files) { - my $c_file = $file; - (my $file_no_ext = $file) =~ s/src\/(.*)\.c$/\1/g; - - my $obj_file = "$arch_obs_dir/${file_no_ext}.o"; - my $s_file = "${file_no_ext}.s"; - - push(@obj_files, $obj_file); - my @deps = header_deps($c_file); - - my $deps_as_join = join(" ", @deps); - - # Emit the rule to make the object file. - print "$obj_file: $deps_as_join\n\t"; - print '$(CC) -c ' . $c_file . ' -o ' . $obj_file . ' $(CFLAGS)' . "\n\n"; - - # Emit the rule to make the assembly file. - print "$s_file: $deps_as_join\n\t"; - print '$(CC) -S ' . $c_file . ' -o ' . $s_file . ' $(CFLAGS)' . "\n\n"; -} - -my $obj_files_deps = join(' ', @obj_files); -print "FORCE:\n\t\n\n"; -print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t"; -print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] " - . "&& ./genmake.pl > Makefile && make main.elf ) " - . "|| " - . "\$(LD) -o $arch_obs_dir/main.elf \$(LD_FLAGS) $obj_files_deps\n\n"; diff --git a/03-refactor/include/apb.h b/03-refactor/include/apb.h deleted file mode 100644 index 11fa7ab..0000000 --- a/03-refactor/include/apb.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef H__APB_ -#define H__APB_ - -#endif /* H__APB_ */ diff --git a/03-refactor/include/clock.h b/03-refactor/include/clock.h deleted file mode 100644 index 30c1302..0000000 --- a/03-refactor/include/clock.h +++ /dev/null @@ -1,112 +0,0 @@ -#ifndef CLOCK_H__ -#define CLOCK_H__ - -#include -#include "rcc.h" - -#define PERIPH_BASE ((uint32_t)0x40000000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) -#define PWR_BASE (PERIPH_BASE + 0x7000) -#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ - -#ifndef __IO -#define __IO volatile -#endif - -typedef struct { - __IO uint32_t cr; - __IO uint32_t csr; -} pwr_t; - -// typedef struct { -// __IO uint32_t acr; -// __IO uint32_t pecr; -// __IO uint32_t pdkeyr; -// __IO uint32_t pekeyr; -// __IO uint32_t prgkeyr; -// __IO uint32_t optkeyr; -// __IO uint32_t sr; -// __IO uint32_t obr; -// __IO uint32_t wrpr; -// } flash_t; - -// #define FLASH (*(flash_t*) (FLASH_R_BASE)) -#define PWR (*(pwr_t*)(PWR_BASE)) - -/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */ -typedef enum { - PLL_DIVISOR_2 = 1, - PLL_DIVISOR_4 = 3, - PLL_DIVISOR_6 = 5, - PLL_DIVISOR_8 = 7, - PLL_DIVISOR_OFF = 0, -} pll_divisor_t; - -/* Valid values for the PLLP bits off the PLLCFG register. */ -typedef enum { - PLLP_DIVISOR_7 = 1, - PLLP_DIVISOR_17 = 3, - PLLP_DIVISOR_OFF = 0, -} pllp_divisor_t; - -/* Valid values for the PLLM bits of the PLLCFG register. */ -typedef enum { - PLLM_DIVISOR_1 = 0, - PLLM_DIVISOR_2 = 1, - PLLM_DIVISOR_3 = 2, - PLLM_DIVISOR_4 = 3, - PLLM_DIVISOR_5 = 4, - PLLM_DIVISOR_6 = 5, - PLLM_DIVISOR_7 = 6, - PLLM_DIVISOR_8 = 7, -} pllm_divisor_t; - -/* Valid sources for the system clock. */ -typedef enum { - SYSTEM_CLOCK_SRC_MSI = 0, - SYSTEM_CLOCK_SRC_HSI = 1, - SYSTEM_CLOCK_SRC_HSE = 2, - SYSTEM_CLOCK_SRC_PLL = 3, -} system_clock_src_t; - -#define E_BADPLLN (-2) -#define E_BADPLLP_DIV (-1) -#define E_TIMEOUT (-3) -#define E_NOT_OFF (-4) -#define E_BAD_ARG (-5) - -int enable_hsi(__IO rcc_t* rcc, bool enable); - -/* - * Sets the system clock to a full 80Mhz. - */ -int set_system_clock_MHz(uint8_t mhz); - -/* - * Set the PLL on. - */ -int pll_on(); - -/* - * Set the PLL off. - */ -int pll_off(); - -/* - * Sets the source of the system clock. - */ -int set_system_clock_src(system_clock_src_t src); - -/* - * Configure the PLL. - */ -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */); - -#endif /* CLOCK_H__ */ diff --git a/03-refactor/include/common.h b/03-refactor/include/common.h deleted file mode 100644 index 9d5c7cd..0000000 --- a/03-refactor/include/common.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef COMMON__H -#define COMMON__H - -#include - -/* Define __IO to be volatile if it's not already. */ -#ifndef __IO -#define __IO volatile -#endif - -#define bool int -#ifndef __cplusplus -#define true 1 -#define false 0 -#endif - -#define PACKED __attribute__((packed)) -#define BIT(n) (1 << (n)) - -#define RESERVED_CONCAT_IMPL(x, y) x ## y -#define RESERVED_MACRO_CONCAT(x, y) RESERVED_CONCAT_IMPL(x, y) -#define RESERVED(n) \ - bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) :n - -#define RESERVE(type) \ - __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__) - -typedef uint32_t bits_t; - -#endif /* COMMON_H */ diff --git a/03-refactor/include/delay.h b/03-refactor/include/delay.h deleted file mode 100644 index 65a26d6..0000000 --- a/03-refactor/include/delay.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef H__DELAY__ -#define H__DELAY__ - -#include - -/* - * Loops and count-downs the delay, the time this takes depends on the speed - * of the clock. - */ -void delay(uint32_t delay); - -#endif /* H__DELAY__ */ diff --git a/03-refactor/include/flash.h b/03-refactor/include/flash.h deleted file mode 100644 index a163a25..0000000 --- a/03-refactor/include/flash.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef H__FLASH_ -#define H__FLASH_ - -#include "common.h" - -/* - * Header file for dealing with flash. - */ - -#define FLASH_BASE 0x40022000 - -typedef struct { - __IO uint32_t ac_r; /* Flash access control register. */ - - /* TODO fill out the rest. */ -} PACKED flash_t; - -#define FLASH (*(__IO flash_t*)FLASH_BASE) - -#endif /* H__FLASH_ */ diff --git a/03-refactor/include/gpio.h b/03-refactor/include/gpio.h deleted file mode 100644 index 62169c6..0000000 --- a/03-refactor/include/gpio.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef GPIO_H__ -#define GPIO_H__ - -#include "common.h" -#include "rcc.h" - -#include - -/* - * Possible GPIO ports. - */ -typedef enum { - GPIO_PORT_A = 0, - GPIO_PORT_B = 1, - GPIO_PORT_C = 2, - GPIO_PORT_D = 3 -} gpio_port_number_t; - -/* - * Structure defining the layout of the layout of the GPIO registers on the - * stm32l432 development board. - */ -typedef struct GPIO_PORT_STR { - __IO uint32_t mode_r; /* Mode register */ - __IO uint32_t otype_r; - __IO uint32_t ospeed_r; - __IO uint32_t pupd_r; - __IO uint32_t id_r; - __IO uint32_t output_r; - __IO uint32_t bsr_r; - __IO uint32_t lck_r; - __IO uint32_t af_rl; - __IO uint32_t af_rh; -} PACKED gpio_port_t; - -/* - * Enum defining the PINs in a GPIO port. Each port has 16 pins to use in - * the stm32l432. - */ -typedef enum GPIO_PIN_ENUM { - PIN_0 = 0, - PIN_1 = 1, - PIN_2 = 2, - PIN_3 = 3, - PIN_4 = 4, - PIN_5 = 5, - PIN_6 = 6, - PIN_7 = 7, - PIN_8 = 8, - PIN_9 = 9, - PIN_10 = 10, - PIN_11 = 11, - PIN_12 = 12, - PIN_13 = 13, - PIN_14 = 14, - PIN_15 = 15 -} gpio_pin_t; - -/* Alternate function number. */ -typedef enum { - AFN_0 = 0, - AFN_1 = 1, - AFN_2 = 2, - AFN_3 = 3, - AFN_4 = 4, - AFN_5 = 5, - AFN_6 = 6, - AFN_7 = 7, - AFN_8 = 8, - AFN_9 = 9, - AFN_10 = 10, - AFN_11 = 11, - AFN_12 = 12, - AFN_13 = 13, - AFN_14 = 14, - AFN_15 = 15 -} alternate_function_t; - -/* - * Enum defining the pin modes that are possible. - */ -typedef enum { - MODE_INPUT = 0, - MODE_OUTPUT = 1, - MODE_ALTERNATE = 2, - MODE_ANALOG = 3 -} gpio_pin_mode_t; - -/* - * Enum defining the pin speeds that are possible. - */ -typedef enum { - SPEED_2MHZ = 0, - SPEED_10MHZ = 1, - SPEED_50MHZ = 3, -} speed_t; - -/* - * Structure defining an OUTPUT pin. Structurally equivalent to the input pin, - * but can be used in a slightly type-safe manner. - */ -typedef struct { - __IO gpio_port_t* gpio_port; - gpio_pin_t pin; -} gpio_output_pin_t; - -/* - * Sets the mode on a GPIO pin. - * - * gpio_port: the gpio port to use. - * pin: the pin number to set. - * pin_mode: the mode to set the pin to. - */ -void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t pin_mode); - -/* - * Sets the given GPIO pin to be an output pin. Returns an output_pin struct - * corresponding to - */ -gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, gpio_pin_t pin); - -/* - * Sets an output pin on or off. - * - * pin: the pin to toggle. - * onoff: 0 for off, non-zero of on. - */ -void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff); - -#define pin_on(p) set_gpio_output_pin(p, 1) - -#define pin_off(p) set_gpio_output_pin(p, 0) - -/* - * Enables a GPIO port and returns a reference to the register definition - * of that GPIO port. - */ -__IO gpio_port_t* enable_gpio(gpio_port_number_t number); - -/* Sets the alternate function for a GPIO pin. */ -void set_gpio_alternate_function( - __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn); - -#endif /* GPIO_H__ */ diff --git a/03-refactor/include/isr_vector.h b/03-refactor/include/isr_vector.h deleted file mode 100644 index 3e55f52..0000000 --- a/03-refactor/include/isr_vector.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef h__ISR_VECTOR_H__ -#define h__ISR_VECTOR_H__ - -/* - * Include file for interrupt service routines. - */ - -/* - * The interrupt service routines. These link in the function `main` as the - * main function. - */ -extern const void* isr_vector[]; - -/* - * Defines an error state. This loops forever and defines a distinct flashing - * pattern to let the user know an unhandled ISR happened. - */ -void unhandled_isr(); - -#endif /* h___ISR_VECTOR_H__ */ diff --git a/03-refactor/include/printf.h b/03-refactor/include/printf.h deleted file mode 100644 index ec3eec0..0000000 --- a/03-refactor/include/printf.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef PRINTF_H_ -#define PRINTF_H_ - -#include -#include - -typedef void(*printf_callback_t)(volatile void*, char); - -void printf_format( - const char* fmt, - printf_callback_t callback, - volatile void* callback_closure, - va_list lst); - -#endif /* PRINTF_H_ */ diff --git a/03-refactor/include/rcc.h b/03-refactor/include/rcc.h deleted file mode 100644 index 3c55e67..0000000 --- a/03-refactor/include/rcc.h +++ /dev/null @@ -1,181 +0,0 @@ -#ifndef H__RCC_ -#define H__RCC_ - -#include "common.h" -#include - -#define RCC_BASE ((uint32_t)0x40021000) - -typedef enum { - SYS_CLK_SW_MSI, - SYS_CLK_SW_HSI, - SYS_CLK_SW_HSE, - SYS_CLK_SW_PLL, -} sys_clk_sw_t; - -typedef enum { - PLL_SRC_NONE, - PLL_SRC_MSI, - PLL_SRC_HSI, - PLL_SRC_HSE -} pll_src_t; - -typedef struct { - /* Clock control register. Offset 0x00. */ - union RCC_CR { - __IO uint32_t r; /* 32 bit register. */ - - /* Bit field for the c_r */ - struct { - bits_t msion:1; /* Turn on teh MSI. */ - bits_t msirdy:1; /* Is the MSI ready? */ - bits_t msipllen:1; /* Enabled/disable the PLL part of MSI. */ - bits_t msirgsel:1; /* MSI clock range selection. */ - bits_t msirange:4; /* MSI range. */ - - bits_t hsion:1; /* Enable the HSI16 clock. */ - bits_t hsikeron:1; /* Force the HSI16 ON even in stop modes. */ - bits_t hsirdy:1; /* Is the hsi ready? */ - bits_t hsiasfs:1; /* HSI automatic start from STOP. */ - RESERVED(4); - - bits_t hseon:1; /* Enable the HSE. */ - bits_t hserdy:1; /* Is the HSE ready? */ - bits_t hsebyp:1; /* Use an external HSE. */ - bits_t csson:1; /* Clock security system enabled. */ - RESERVED(4); - - bits_t pllon:1; /* Enable the main PLL. */ - bits_t pllrdy:1; /* Is the PLL ready? */ - bits_t pllsai1on:1; /* Enable the SAI1 PLL. */ - bits_t pllsai1rdy:1; /* Enable the SAI1 PLL. */ - RESERVED(4); - } PACKED; - } __IO c; - - /* Internal clock sources calibration register (RCC_ICSCR) Offset 0x04. */ - union RCC_ICSCR { - __IO uint32_t r; /* 32 bit register. */ - - /* Bit field for icsc_r. */ - struct { - bits_t msical:8; - bits_t msitrim:8; - bits_t hsical:8; - bits_t hsitrim:5; - - RESERVED(3); - } PACKED; - } __IO icscr; - - - /* Clock configuration register. */ - union RCC_CFGR { - __IO uint32_t r; - - /* Bitfields for cfg_r. */ - struct { - sys_clk_sw_t sw:2; /* System clock switch. @see sys_clk_sw_t enum. */ - sys_clk_sw_t sws:2; /* System clock switch status. */ - - bits_t hpre:4; /* AHB prescaler. */ - bits_t ppre:3; /* APB low-speed prescaller. */ - - RESERVED(1); - - bits_t stopwuck:1; /* Wakeup from Stop and CSS backup clock selection. */ - bits_t mcosel:4; /* Microcontroller clock output. */ - bits_t mcopre:3; /* MCO prescaller. */ - - RESERVED(1); - } PACKED __IO; - } __IO cfg; - - /* PLL Configuration register. Offset 0x0c */ - union RCC_PLLCFGR { - __IO uint32_t r; - - /* Bitfields for pllcfg_r */ - struct { - pll_src_t pllsrc:2; /* PLL input source clock. */ - - RESERVED(2); - - bits_t pllm:3; /* Divisions factor for the main PLL and audio PLL */ - - RESERVED(1); - - bits_t plln:7; /* main PLL multiplication factor for VCO, must be - * on interval [8, 86] inclusive */ - RESERVED(1); - - bits_t pllpen:1; /* Main PLL PLLSAI1CLK output enable. */ - bits_t pllp:1; /* Main division factor for PLLP. - * 0 = 7, 1 = 17 */ - RESERVED(2); - - bits_t pllqen:1; /* Main PLL PLL48M1CLK output enabled. */ - bits_t pllq:2; /* PLLQ division factor. in 2^x. */ - - RESERVED(1); - - bits_t pllren:1; /* PLL PLLCLK enabled. */ - bits_t pllr:2; ; /* main pll divion factor. 2^x. */ - - bits_t pllpdiv:5; /* PLLP division factor. 0 to be handled by PLLP. */ - - } PACKED __IO; - } __IO pllcfg; - - __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ - - __IO uint32_t reserved_1; /* Not used. offset 0x14. */ - - __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ - __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ - __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ - - __IO uint32_t reserved_2; /* Not used. offset 0x24. */ - - __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ - __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ - __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ - - __IO uint32_t reserved_3; /* Not used. offset 0x34. */ - - __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */ - __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */ - __IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */ - - __IO uint32_t reserved_4; /* Not used. offset 0x44. */ - - __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ - __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ - __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ - - __IO uint32_t reserved_5; /* Not used. offset 0x54. */ - - __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ - __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ - __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ - - __IO uint32_t reserved_6; /* Not used. offset 0x64. */ - - __IO uint32_t ahb1smen_r; /* 0x68 */ - __IO uint32_t ahb2smen_r; /* 0x6c */ - __IO uint32_t ahb3smen_r; /* 0x70 */ - - __IO uint32_t reserved_7; - - __IO uint32_t apb1smen_r1; /* 0x78 */ - __IO uint32_t apb1smen_r2; /* 0x7c */ - __IO uint32_t apb2smen_r; /* 0x80 */ - - __IO uint32_t reserved_8; - - __IO uint32_t ccip_r; /* 0x88 */ -} PACKED rcc_t; - -#define RCC (*(__IO rcc_t*)RCC_BASE) - -#endif diff --git a/03-refactor/include/spin.h b/03-refactor/include/spin.h deleted file mode 100644 index a23d25b..0000000 --- a/03-refactor/include/spin.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef H__SPIN_ -#define H__SPIN_ - -#include - -/* - * Flash a code on the status LED. - * - * The flash codes a binary from MSB to LSB. A long flash is a 1, a short flash - * is a 0. Each independent flashing is succeced by a break of 4 times that - * of a long flash. - */ -void spin(uint32_t base_delay, uint8_t code); - -#endif /* H__SPIN_ */ diff --git a/03-refactor/include/usart.h b/03-refactor/include/usart.h deleted file mode 100644 index 265ac2d..0000000 --- a/03-refactor/include/usart.h +++ /dev/null @@ -1,219 +0,0 @@ -#ifndef H__USART_ -#define H__USART_ - -#include "common.h" -#include "rcc.h" - -#include - -/* - * Possibel USART clock sources. - */ -typedef enum { - USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */ - USART_CLK_SRC_SYSCLK = 1, /* System clock. */ - USART_CLK_SRC_HSI16 = 2, /* 16MHz oscillator. */ - USART_CLK_SRC_LSE = 3 /* Low power 32kHz clock. */ -} usart_clk_src_t; - -typedef struct { - /* USART conttrol register 1. */ - union USART_CR1 { - __IO uint32_t r; - struct { - bits_t ue:1; /* UART enable */ - bits_t uesm:1; /* UART enabled in stop mode. */ - bits_t re:1; /* reciever enabled. */ - bits_t te:1; /* transmitter enabled. */ - bits_t idleie:1; /* Idle interrupt enabled. */ - bits_t rxneie:1; /* RXNEIE RXNE interrupt enable. */ - bits_t tcie:1; - bits_t txeie:1; - - bits_t peie:1; - bits_t ps:1; - bits_t pce:1; - bits_t wake:1; - bits_t m0:1; - bits_t mme:1; - bits_t cmie:1; - bits_t over8:1; - - bits_t dedt:5; - bits_t deat:5; - - bits_t rtoie:1; - bits_t eobie:1; - bits_t m1:1; - bits_t reserved:3; - } PACKED; - } __IO c1; - - /* USART control register 2. */ - union USART_CR2 { - __IO uint32_t r; - - struct { - RESERVED(4); - bits_t addm7:1; - bits_t lbdl:1; - bits_t lbdie:1; - RESERVED(1); - - bits_t lbcl:1; - bits_t cpha:1; - bits_t cpol:1; - bits_t clken:1; - bits_t stop:2; - bits_t linen:1; - bits_t swap:1; - - bits_t rxinv:1; - bits_t txinv:1; - bits_t datainv:1; - bits_t msbfirst:1; - bits_t abren:1; - bits_t abrmod:2; - bits_t rtoen:1; - - bits_t add:8; - } PACKED; - } __IO c2; - - union USART_CR3 { - __IO uint32_t r; - - struct { - bits_t eie:1; - bits_t iren:1; - bits_t irlp:1; - bits_t hdsel:1; - bits_t nack:1; - bits_t scen:1; - bits_t dmar:1; - bits_t dmat:1; - - bits_t rtse:1; - bits_t ctse:1; - bits_t ctsie:1; - bits_t onebit:1; - bits_t ovrdis:1; - bits_t ddre:1; - bits_t dem:1; - bits_t dep:1; - - RESERVED(1); - bits_t scarcnt:3; - bits_t wus:2; - bits_t wufie:1; - bits_t ucesm:1; - - bits_t tcbgtie:1; - RESERVED(7); - } PACKED; - } __IO c3; - - /* USART baud rate register. */ - union USART_BRR { - __IO uint32_t r; - - struct { - uint16_t v; - RESERVED(16); - } PACKED; - - /* Structure to use when OVER8 is set in the control register - * USART_C1. */ - struct { - bits_t low:3; - - RESERVED(1); - - bits_t high:12; - - RESERVED(16); - } PACKED over8; - } __IO br; - - uint32_t gtp_r; - uint32_t rto_r; - uint32_t rq_r; - uint32_t is_r; - uint32_t ic_r; - uint32_t rd_r; - uint32_t td_r; -} usart_t; - -#define USART1 (* (__IO usart_t*) 0x40013800) -#define USART2 (* (__IO usart_t*) 0x40004400) -typedef enum { - OVERSAMPLE_8, - OVERSAMPLE_16 -} oversampling_mode_t; - -static inline void usart_set_divisor( - __IO usart_t* usart, - uint16_t usartdiv) -{ - if (usart->c1.r & (1 << 15)) { - /* OVER8 is set. */ - usart->br.over8.high = (usartdiv & ~7); - usart->br.over8.low = ((usartdiv & 7) >> 1); - } else { - /* OVER8 is not set. */ - usart->br.v = usartdiv; - } -} - -static inline void usart_set_oversampling_mode( - __IO usart_t* usart, - oversampling_mode_t mode) -{ - usart->c1.over8 = mode == OVERSAMPLE_8; -} - -typedef enum { - USART_PARITY_DISABLED = 0, - USART_PARITY_ODD = 1, - USART_PARITY_EVEN = 2, -} usart_parity_t; - -typedef enum { - USART_ENABLE_TX = 0x02, - USART_ENABLE_RX = 0x01, - USART_ENABLE_DISABLED = 0x00, -} usart_enable_t; - -void usart_set_parity(__IO usart_t* usart, usart_parity_t parity); - -void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled); - -/* - * Send a byte on the usart, This command blocks until the data - * is fully sent. - */ -void usart_transmit_byte(__IO usart_t* usart, uint8_t byte); - -void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); - -void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable); - -void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); - -void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable); - -void usart_transmit_bytes( - __IO usart_t* usart, const uint8_t* bytes, uint32_t n); - -void usart_transmit_str(__IO usart_t* usart, const char* str); - -void usart_printf(__IO usart_t* usart, const char* fmt, ...); - -/* Returns non-zero if usart2 is enabled. */ -int is_usart2_enabled(); - -/* Enable the second USART. */ -int enable_usart2(uint32_t baud); - - -#endif /* H__USART_ */ diff --git a/03-refactor/linker/linker_script.ld b/03-refactor/linker/linker_script.ld deleted file mode 100644 index 348d03b..0000000 --- a/03-refactor/linker/linker_script.ld +++ /dev/null @@ -1,36 +0,0 @@ -MEMORY -{ - flash : org = 0x08000000, len = 256k - sram1 : org = 0x20000000, len = 48k - sram2 : org = 0x10000000, len = 16k -} - -SECTIONS -{ - /* This is where the code goes. */ - . = ORIGIN(flash); - .text : { - *(.vectors); /* All .vector sections go here. */ - *(.text); /* All .text sections go here. */ - } >flash - - .data : { - /* Data segment as defined in the flash. */ - INIT_DATA_VALUES = LOADADDR(.data); - - /* Data segment where it will be in memory. */ - DATA_SEGMENT_START = .; - *(.data); - DATA_SEGMENT_STOP = .; - - /* Align by 4 so we can optimize the copier to use uint32's. */ - . = ALIGN(0x04); - } >sram1 AT>flash - - BSS_START = .; - .bss : { - *(.bss); - . = ALIGN(0x04); - } > sram1 - BSS_END = .; -} diff --git a/03-refactor/src/clock.c b/03-refactor/src/clock.c deleted file mode 100644 index 7256500..0000000 --- a/03-refactor/src/clock.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file sets the system clock to its full glory of 80Mhz - */ - -#include "clock.h" -#include -#include "flash.h" -#include "gpio.h" -#include "spin.h" - -#define TIMEOUT 10000 - -int pll_off() -{ - uint32_t c; - - RCC.c.pllon = false; - for (c = 0; c < TIMEOUT && RCC.c.pllrdy; ++c) - ; /* Wait for OFF. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int pll_on() -{ - uint32_t c; - - RCC.c.pllon = true; - for (c = 0; c < TIMEOUT && !RCC.c.pllrdy; ++c) - ; /* Wait for RDY. */ - - if (c == TIMEOUT) { - return E_TIMEOUT; - } - - return 0; -} - -int configure_pll( - uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ - pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ - pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ - uint8_t plln, /* PLL numerator. */ - pllm_divisor_t pllm, /* PLL denominator. */ - pll_src_t pllsrc /* PLL source */) -{ - if (RCC.c.pllrdy) { - /* PLL must be off to configure it. */ - return E_NOT_OFF; - } - - /* Make sure inputs are valid. */ - if (pllp_div_factor == 1 || pllp_div_factor > 31) { - return E_BADPLLP_DIV; - } - if (plln < 8 || plln > 86) { - return E_BADPLLN; - } - - union RCC_PLLCFGR tmp; - - tmp.pllpdiv = pllp_div_factor; - tmp.pllr = pllr >> 1; - tmp.pllren = pllr & 1; - tmp.pllp = pllp >> 1; - tmp.pllpen = pllp & 1; - tmp.pllq = pllq >> 1; - tmp.pllqen = pllq & 1; - tmp.plln = plln; - tmp.pllm = pllm; - - tmp.pllsrc = pllsrc; - - RCC.pllcfg = tmp; - - return 0; -} - -int set_system_clock_MHz(uint8_t mhz) -{ - /* Set the source of the system colck to MSI temporarily. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_MSI); - - if (mhz <= 8 || mhz > 80) { - return E_BAD_ARG; - } - - pll_off(); - - configure_pll( - 0, - PLL_DIVISOR_4, - PLL_DIVISOR_4, - PLLP_DIVISOR_7, - mhz, - PLLM_DIVISOR_1, - PLL_SRC_MSI); - - pll_on(); - - /* Configure the flash to have 4 wait states. This is required at - * 80 MHz. */ - FLASH.ac_r &= ~0x07; - FLASH.ac_r |= 0x04; - - /* Set the source of the system colck to PLL. */ - set_system_clock_src(SYSTEM_CLOCK_SRC_PLL); - return 0; -} - -int set_system_clock_src(system_clock_src_t src) -{ - uint8_t value = RCC.cfg.r & ~0x03; - RCC.cfg.r = value | src; -} - -int enable_hsi(__IO rcc_t* rcc, bool enable) -{ - uint32_t c; - rcc->c.hsion = !!enable; - for(c = 0; c < TIMEOUT && !rcc->c.hsirdy; ++ c) - ; - if (c == TIMEOUT) { - return E_TIMEOUT; - } - return 0; -} diff --git a/03-refactor/src/delay.c b/03-refactor/src/delay.c deleted file mode 100644 index 2a16d47..0000000 --- a/03-refactor/src/delay.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "delay.h" - -void delay(uint32_t delay) -{ - while (delay--) { - /* needed to keep the compiler from optimizing away the loop. */ - asm volatile(""); - } -} diff --git a/03-refactor/src/gpio.c b/03-refactor/src/gpio.c deleted file mode 100644 index 02933b7..0000000 --- a/03-refactor/src/gpio.c +++ /dev/null @@ -1,52 +0,0 @@ -#include "gpio.h" -#include "rcc.h" - -/* - * Sets the mode of a pin on a gpio por. - */ -void set_gpio_pin_mode( - __IO gpio_port_t* gpio_port, gpio_pin_t pin, gpio_pin_mode_t mode) -{ - /* Each pin has a 2-bit mode provided at bits pin#*2 and pin#*2+1 */ - gpio_port->mode_r &= ~(0x03 << pin * 2); - gpio_port->mode_r |= mode << pin * 2; -} - -gpio_output_pin_t set_gpio_pin_output( - __IO gpio_port_t* gpio_port, gpio_pin_t pin) -{ - set_gpio_pin_mode(gpio_port, pin, MODE_OUTPUT); - - return (gpio_output_pin_t){.gpio_port = gpio_port, .pin = pin}; -} - -void set_gpio_output_pin(gpio_output_pin_t pin, bool onoff) -{ - if (onoff) { - pin.gpio_port->output_r |= 1 << pin.pin; - } else { - pin.gpio_port->output_r &= ~(1 << pin.pin); - } -} - -void set_gpio_alternate_function( - __IO gpio_port_t* port, gpio_pin_t gpio_pin, alternate_function_t afn) -{ - __IO uint32_t* reg; - if (gpio_pin < 8) { - reg = &(port->af_rl); - } else { - reg = &(port->af_rh); - gpio_pin -= 8; - } - - uint32_t tmp = *reg & (~0x0f << gpio_pin * 4); - *reg = tmp | (afn << gpio_pin * 4); -} - -#define GPIO_PORTS_BASE_ADDR ((uint8_t*)0x48000000) -__IO gpio_port_t* enable_gpio(gpio_port_number_t gpio_port_number) -{ - RCC.ahb2en_r |= 1 << gpio_port_number; /* Enable the GPIO port. */ - return (__IO gpio_port_t*)(GPIO_PORTS_BASE_ADDR + (gpio_port_number * 0x400)); -} diff --git a/03-refactor/src/isr_vector.c b/03-refactor/src/isr_vector.c deleted file mode 100644 index f757ebe..0000000 --- a/03-refactor/src/isr_vector.c +++ /dev/null @@ -1,275 +0,0 @@ -#include "isr_vector.h" -#include "delay.h" -#include "gpio.h" -#include "usart.h" - -/* Forward-declare the main function. This is implemented in main.c. */ -void main(); - -/* These are defined in the linker script. */ -extern uint32_t INIT_DATA_VALUES; -extern uint32_t DATA_SEGMENT_START; -extern uint32_t DATA_SEGMENT_STOP; -extern uint32_t BSS_START; -extern uint32_t BSS_END; - -/* - * Runs before main. Initializes the data and bss segments by loading them - * into memory. - */ -void init() -{ - uint32_t* src; - uint32_t* dest; - - src = &INIT_DATA_VALUES; - dest = &DATA_SEGMENT_START; - - /* Copy the values from flash into the data segment. */ - while (dest != &DATA_SEGMENT_STOP) { - *(dest++) = *(src++); - } - - /* Everything in the BSS segment is set to zero. */ - dest = &BSS_START; - while (dest != &BSS_END) { - *(dest++) = 0; - } - - /* Jump to main. */ - main(); -} - -#define DEF_HANDLER(n) \ - void unhandled_isr_ ## n() { \ - unhandled_isr(n); \ - } - -DEF_HANDLER(1) -DEF_HANDLER(2) -DEF_HANDLER(3) -DEF_HANDLER(4) -DEF_HANDLER(5) -DEF_HANDLER(6) -DEF_HANDLER(7) -DEF_HANDLER(8) -DEF_HANDLER(9) -DEF_HANDLER(10) -DEF_HANDLER(11) -DEF_HANDLER(12) -DEF_HANDLER(13) -DEF_HANDLER(14) -DEF_HANDLER(15) -DEF_HANDLER(16) -DEF_HANDLER(17) -DEF_HANDLER(18) -DEF_HANDLER(19) -DEF_HANDLER(20) -DEF_HANDLER(21) -DEF_HANDLER(22) -DEF_HANDLER(23) -DEF_HANDLER(24) -DEF_HANDLER(25) -DEF_HANDLER(26) -DEF_HANDLER(27) -DEF_HANDLER(28) -DEF_HANDLER(29) -DEF_HANDLER(30) -DEF_HANDLER(31) -DEF_HANDLER(32) -DEF_HANDLER(33) -DEF_HANDLER(34) -DEF_HANDLER(35) -DEF_HANDLER(36) -DEF_HANDLER(37) -DEF_HANDLER(38) -DEF_HANDLER(39) -DEF_HANDLER(40) -DEF_HANDLER(41) -DEF_HANDLER(42) -DEF_HANDLER(43) -DEF_HANDLER(44) -DEF_HANDLER(45) -DEF_HANDLER(46) -DEF_HANDLER(47) -DEF_HANDLER(48) -DEF_HANDLER(49) -DEF_HANDLER(50) -DEF_HANDLER(51) -DEF_HANDLER(52) -DEF_HANDLER(53) -DEF_HANDLER(54) -DEF_HANDLER(55) -DEF_HANDLER(56) -DEF_HANDLER(57) -DEF_HANDLER(58) -DEF_HANDLER(59) -DEF_HANDLER(60) -DEF_HANDLER(61) -DEF_HANDLER(62) -DEF_HANDLER(63) -DEF_HANDLER(64) -DEF_HANDLER(65) -DEF_HANDLER(66) -DEF_HANDLER(67) -DEF_HANDLER(68) -DEF_HANDLER(69) -DEF_HANDLER(70) -DEF_HANDLER(71) -DEF_HANDLER(72) -DEF_HANDLER(73) -DEF_HANDLER(74) -DEF_HANDLER(75) -DEF_HANDLER(76) -DEF_HANDLER(77) -DEF_HANDLER(78) -DEF_HANDLER(79) -DEF_HANDLER(80) -DEF_HANDLER(81) -DEF_HANDLER(82) -DEF_HANDLER(83) -DEF_HANDLER(84) -DEF_HANDLER(85) -DEF_HANDLER(86) -DEF_HANDLER(87) -DEF_HANDLER(88) -DEF_HANDLER(89) -DEF_HANDLER(90) -DEF_HANDLER(91) -DEF_HANDLER(92) -DEF_HANDLER(93) -DEF_HANDLER(94) -DEF_HANDLER(95) -DEF_HANDLER(96) -DEF_HANDLER(97) - -const void* vectors[] __attribute__((section(".vectors"))) = { - (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ - init, /* Reset handler */ - unhandled_isr_1, /* NMI */ - unhandled_isr_2, /* Hard Fault */ - unhandled_isr_3, /* MemManage */ - unhandled_isr_4, /* BusFault */ - unhandled_isr_5, /* UsageFault */ - unhandled_isr_6, /* Reserved */ - unhandled_isr_7, /* Reserved */ - unhandled_isr_8, /* Reserved */ - unhandled_isr_9, /* Reserved */ - unhandled_isr_10, /* SVCall */ - unhandled_isr_11, /* Debug */ - unhandled_isr_12, /* Reserved */ - unhandled_isr_13, /* PendSV */ - unhandled_isr_14, /* SysTick */ - - /* External interrupt handlers follow */ - unhandled_isr_15, /* 0 WWDG */ - unhandled_isr_16, /* 1 PVD */ - unhandled_isr_17, /* 2 TAMP_SAMP */ - unhandled_isr_18, /* 3 RTC_WKUP */ - unhandled_isr_19, /* 4 FLASH */ - unhandled_isr_20, /* 5 RCC */ - unhandled_isr_21, /* 6 EXTI0 */ - unhandled_isr_22, /* 7 EXTI1 */ - unhandled_isr_23, /* 8 EXTI2 */ - unhandled_isr_24, /* 9 EXTI3 */ - unhandled_isr_25, /* 10 EXTI4 */ - unhandled_isr_26, /* 11 DMA_CH1 */ - unhandled_isr_27, /* 12 DMA_CH2 */ - unhandled_isr_28, /* 13 DMA_CH3 */ - unhandled_isr_29, /* 14 DMA_CH4 */ - unhandled_isr_30, /* 15 DMA_CH5 */ - unhandled_isr_31, /* 16 DMA_CH6 */ - unhandled_isr_32, /* 17 DMA_CH7 */ - unhandled_isr_33, /* 18 ADC1 */ - unhandled_isr_34, /* 19 CAN_TX */ - unhandled_isr_35, /* 20 CAN_RX0 */ - unhandled_isr_36, /* 21 CAN_RX1 */ - unhandled_isr_37, /* 22 CAN_SCE */ - unhandled_isr_38, /* 23 EXTI9_5 */ - unhandled_isr_39, /* 24 TIM1_BRK/TIM15 */ - unhandled_isr_40, /* 25 TIM1_UP/TIM16 */ - unhandled_isr_41, /* 26 TIM1_TRG_COM */ - unhandled_isr_42, /* 27 TIM1_CC */ - unhandled_isr_43, /* 28 TIM2 */ - unhandled_isr_44, /* 29 Reserved */ - unhandled_isr_45, /* 30 Reserved */ - unhandled_isr_46, /* 31 I2C1_EV */ - unhandled_isr_47, /* 32 I2C1_ER */ - unhandled_isr_48, /* 33 I2C2_EV */ - unhandled_isr_49, /* 34 I2C2_ER */ - unhandled_isr_50, /* 35 SPI1 */ - unhandled_isr_51, /* 36 SPI2 */ - unhandled_isr_52, /* 37 USART1 */ - unhandled_isr_53, /* 38 USART2 */ - unhandled_isr_54, /* 39 USART3 */ - unhandled_isr_55, /* 40 EXTI15_10 */ - unhandled_isr_56, /* 41 RTCAlarm */ - unhandled_isr_57, /* 42 Reserved */ - unhandled_isr_58, /* 43 Reserved */ - unhandled_isr_59, /* 44 Reserved */ - unhandled_isr_60, /* 45 Reserved */ - unhandled_isr_61, /* 46 Reserved */ - unhandled_isr_62, /* 47 Reserved */ - unhandled_isr_63, /* 48 Reserved */ - unhandled_isr_64, /* 49 SDMMC1 */ - unhandled_isr_65, /* 50 Reserved */ - unhandled_isr_66, /* 51 SPI3 */ - unhandled_isr_67, /* 52 Reserved */ - unhandled_isr_68, /* 53 Reserved */ - unhandled_isr_69, /* 54 TIM6_DACUNDER */ - unhandled_isr_70, /* 55 TIM7 */ - unhandled_isr_71, /* 56 DMA2_CH1 */ - unhandled_isr_72, /* 57 DMA2_CH2 */ - unhandled_isr_73, /* 58 DMA2_CH3 */ - unhandled_isr_74, /* 59 DMA2_CH4 */ - unhandled_isr_75, /* 60 DMA2_CH5 */ - unhandled_isr_76, /* 61 Reserved */ - unhandled_isr_77, /* 62 Reserved */ - unhandled_isr_78, /* 63 Reserved*/ - unhandled_isr_79, /* 64 COMP */ - unhandled_isr_80, /* 65 LPTIM1 */ - unhandled_isr_81, /* 66 LPTIM2 */ - unhandled_isr_82, /* 67 USB_FS */ - unhandled_isr_83, /* 68 DMA_CH6 */ - unhandled_isr_84, /* 69 DMA_CH7 */ - unhandled_isr_85, /* 70 LPUART1 */ - unhandled_isr_86, /* 71 QUADSPI */ - unhandled_isr_87, /* 72 I2C3_EV */ - unhandled_isr_88, /* 73 I2C3_ER */ - unhandled_isr_89, /* 74 SAI1 */ - unhandled_isr_90, /* 75 Reserved */ - unhandled_isr_91, /* 76 SWPMI1 */ - unhandled_isr_92, /* 77 TSC */ - unhandled_isr_93, /* 78 Reserved */ - unhandled_isr_94, /* 79 AES */ - unhandled_isr_95, /* 80 RNG */ - unhandled_isr_96, /* 81 FPU */ - unhandled_isr_97 /* 82 CRS */ -}; - - -/* - * Does nothing ... forever. - */ -void unhandled_isr(int isr) -{ - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - - if (is_usart2_enabled()) { - usart_printf(&USART2, "** Unhandled ISR Vector [%d]\r\n", isr); - } - - for (;;) { - /* Flash in a distinct pattern to know that something went wrong. */ - - pin_off(pin3); - delay(1000000); - pin_on(pin3); - delay(1000000); - pin_off(pin3); - delay(1000000); - pin_on(pin3); - delay(5000000); - } -} diff --git a/03-refactor/src/main.c b/03-refactor/src/main.c deleted file mode 100644 index 97449b2..0000000 --- a/03-refactor/src/main.c +++ /dev/null @@ -1,103 +0,0 @@ - -#include "clock.h" -#include "delay.h" -#include "gpio.h" -#include "spin.h" -#include "usart.h" -#include "sio.h" - -void unhandled_isr_2(); -void init(); - -int in_the_data; -volatile uint32_t delay_amt = 20000000 / 4; - -int enable_usart1(uint32_t baud_rate) -{ - /* Enable the GPIO bus. */ - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - - /* Enable the USART clock. */ - RCC.apb2en_r |= BIT(14); - - /* == Configure the IO Pins. == */ - - /* GPIO D5 (Port B pin 6) is USART1 Tx, - * GPIO D6 (Port B pin 7) is USART1 Rx. */ - set_gpio_pin_mode(port_b, PIN_6, MODE_ALTERNATE); - set_gpio_pin_mode(port_b, PIN_7, MODE_ALTERNATE); - - /* Set the GPIO pins to use the USART alternate function. */ - set_gpio_alternate_function(port_b, PIN_6, AFN_7); - set_gpio_alternate_function(port_b, PIN_7, AFN_7); - - RCC.apb2rst_r &= ~BIT(14); /* De-assert reset of USART1 */ - - uint32_t baud_rate_div = 80000000 / baud_rate; - USART1.c1.r = 0; - USART1.c2.r = 0; - USART1.c3.r = 0; - USART1.br.v = baud_rate_div; - - USART1.c1.r |= BIT(3) | BIT(2); - USART1.c1.r |= BIT(0); - - /* Enable the transmitter and the receiver. */ - usart_set_enabled(&USART1, USART_ENABLE_TX); - asm volatile(" cpsie i "); -} - -void dwn() { - int val = 19; - - while (val > 1) { - usart_printf(&USART2, "Value: %2d\r\n", val); - if ((val & 1) == 0) { - val /= 2; - } else { - val = val * 3 + 1; - } - } - usart_printf(&USART2, "Value: %2d\r\n", val); -} - -/* Main function. This gets executed from the interrupt vector defined above. */ -int main() -{ - /* Enable the GPIO port B. */ - // __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - // gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - // gpio_output_pin_t pin1 = set_gpio_pin_output(port_b, PIN_1); - - /* Enable a higher clock frequency. */ - set_system_clock_MHz(80); - - enable_usart2(115200); - int on_the_stack; - - USART2.c1.tcie = 1; - USART2.c1.txeie = 1; - - // pin_on(pin3); - if (is_usart2_enabled()) { - dwn(); - usart_printf(&USART2, "Hello, %d!\r\n", -15); - usart_printf(&USART2, "Hello, %022x\r\n", 0xeadbeef); - usart_printf(&USART2, "on_the_stack: %08X\r\n", (unsigned) &on_the_stack); - - int i; - - printf("isr-2: %08x\r\n", (unsigned int)(void *) unhandled_isr_2); - printf("init: %08x\r\n", (unsigned int)(void *) init); - for (i = 0; i < 20; ++ i) { - printf("isr %d: %08x\r\n", i, *(unsigned int*)(0x08000000 + i * 4)); - } - } - - // usart_printf(&USART2, "that_thing: %d\n", *(unsigned*)(0x0)); - // for(;;); -} - -void do_thing(void(*fn)()) { - fn(); -} diff --git a/03-refactor/src/printf.c b/03-refactor/src/printf.c deleted file mode 100644 index fa7f519..0000000 --- a/03-refactor/src/printf.c +++ /dev/null @@ -1,152 +0,0 @@ -#include "printf.h" - -enum PRINTF_TYPE { - PRINTF_TYPE_STRING = 0, - PRINTF_TYPE_INT = 1, - PRINTF_TYPE_PERCENT = 2, - PRINTF_TYPE_UNKNOWN = 999 -}; - -static enum PRINTF_TYPE get_printf_type(const char* cur) -{ - while (*cur >= 0x30 && *cur < 0x3a) ++ cur; - - if (*cur == 's') { - return PRINTF_TYPE_STRING; - } else if (*cur == 'd' || *cur == 'x' || *cur == 'X' || *cur == 'u') { - return PRINTF_TYPE_INT; - } - - return PRINTF_TYPE_UNKNOWN; -} - -static const char* printf_handle_string( - const char* fmt, - const char* next, - printf_callback_t callback, - volatile void* closure) -{ - const char* cur = next; - for (; *cur != 0; ++ cur) { - callback(closure, *cur); - } - - return fmt; -} - -static char printf_toupper(char ch) -{ - if (ch <= 0x7a && ch > 0x60) { - return ch - 0x20; - } - return ch; -} - -static const char* parse_fmt( - const char* fmt, - int* out_padding, - char* out_pad_char) -{ - if (*fmt == '0') { - *out_pad_char = '0'; - ++ fmt; - } else { - *out_pad_char = ' '; - } - int padding = 0; - while (*fmt < 0x3a && *fmt >= 0x30) { - padding *= 10; - padding += (*fmt ++) - 0x30; - } - - *out_padding = padding; - return fmt; -} - -static const char* mapping = "0123456789abcdef"; -static const char* printf_handle_int( - const char* fmt, unsigned int next, printf_callback_t callback, volatile void* closure) -{ - int base = 10; - char chars[32]; - int pos = 31; - int upper = 0; - char pad_char; - int padding; - int is_unsigned = 0; - - fmt = parse_fmt(fmt, &padding, &pad_char); - - if (*fmt == 'x' || *fmt == 'X') { - base = 16; - is_unsigned = 1; - } else if (*fmt == 'u') { - is_unsigned = 1; - } - - upper = *fmt == 'X'; - - int next_i = (int) next; - if (next_i < 0 && !is_unsigned) { - callback(closure, '-'); - next_i *= -1; - next = (unsigned) next_i; - } - - if (next == 0) { - callback(closure, '0'); - } else { - while (next > 0) { - char next_ch = mapping[next % base]; - if (upper) next_ch = printf_toupper(next_ch); - chars[pos --] = next_ch; - padding --; - next /= base; - } - - while ((padding--) > 0) { - chars[pos --] = pad_char; - } - - for (++ pos; pos < 32; ++ pos) { - callback(closure, chars[pos]); - } - } - - return fmt; -} - -void printf_format( - const char* fmt, - printf_callback_t callback, - volatile void* closure, - va_list ap) -{ - const char* cur = fmt; - - const char* next_string; - int next_int; - - for (; *cur != 0; ++ cur) { - if (*cur == '%') { - // Handle the formatting here. - ++ cur; - enum PRINTF_TYPE printf_type = get_printf_type(cur); - - switch (printf_type) { - case PRINTF_TYPE_PERCENT: - callback(closure, '%'); - break; - case PRINTF_TYPE_STRING: - next_string = va_arg(ap, const char*); - cur = printf_handle_string(cur, next_string, callback, closure); - break; - case PRINTF_TYPE_INT: - next_int = va_arg(ap, int); - cur = printf_handle_int(cur, next_int, callback, closure); - } - } else { - callback(closure, *cur); - } - } -} diff --git a/03-refactor/src/spin.c b/03-refactor/src/spin.c deleted file mode 100644 index fbd16b6..0000000 --- a/03-refactor/src/spin.c +++ /dev/null @@ -1,49 +0,0 @@ -#include "spin.h" -#include "delay.h" -#include "gpio.h" - -#define SHORT_DELAY 200000 -#define LONG_DELAY (SHORT_DELAY * 2) - -static void flash_bit( - uint32_t base, gpio_output_pin_t out_pin, - uint8_t bit /* 0 => 0, non-zero => 1 */) -{ - pin_on(out_pin); - if (bit) { - delay(base * 2); - } else { - delay(base); - } - pin_off(out_pin); - delay(base); -} - -void spin(uint32_t base, uint8_t c) -{ - uint8_t code; - __IO gpio_port_t* port_b = enable_gpio(GPIO_PORT_B); - gpio_output_pin_t pin3 = set_gpio_pin_output(port_b, PIN_3); - - for (;;) { - code = c; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - code <<= 1; - flash_bit(base, pin3, code & 0x80); - - delay(base * 4); - } -} diff --git a/03-refactor/src/usart.c b/03-refactor/src/usart.c deleted file mode 100644 index 76e93f1..0000000 --- a/03-refactor/src/usart.c +++ /dev/null @@ -1,131 +0,0 @@ -#include "usart.h" -#include "delay.h" -#include "printf.h" -#include "gpio.h" -#include "clock.h" - -void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) -{ - rcc->ccip_r = rcc->ccip_r & (~0x03) | usart_clk_src; -} - -void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) -{ - rcc->ccip_r = rcc->ccip_r & ~(0x03 << 2) | (usart_clk_src << 2); -} - -void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable) -{ - if (enable) { - rcc->apb1en1_r |= BIT(17); - } else { - rcc->apb1en1_r &= ~BIT(17); - } -} - -void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable) -{ - if (enable) { - rcc->apb2en_r |= BIT(14); - } else { - rcc->apb2en_r &= ~BIT(14); - } -} - -void usart_set_parity(__IO usart_t* usart, usart_parity_t parity) -{ - usart->c1.pce = !!parity; - usart->c1.ps = parity & 1; -} - -void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled) -{ - if (!enabled) { - usart->c1.ue = 0; - } else { - /* Set the rx enabled. */ - union USART_CR1 tmp = usart->c1; - - tmp.re = !!(enabled & USART_ENABLE_RX); - tmp.te = !!(enabled & USART_ENABLE_TX); - tmp.ue = 1; - - usart->c1 = tmp; - } -} - -void usart_transmit_byte(__IO usart_t* usart, uint8_t byte) -{ - usart->td_r = byte; - /* Per the manual, when bit 7 of the IS register is set, then the usart - * data has been sent to the shift register. - * - * This bit is cleared by writing to the TD register. */ - while (!(usart->is_r & BIT(7))) - ; -} - -void usart_transmit_bytes(__IO usart_t* usart, const uint8_t* bytes, uint32_t n) -{ - while (n --) { - usart_transmit_byte(usart, *(bytes ++)); - } -} - -void usart_transmit_str(__IO usart_t* usart, const char* str) -{ - while (*str) { - if (*str == '\n') { - usart_transmit_byte(usart, '\r'); - } - usart_transmit_byte(usart, *(str ++)); - } -} - -void usart_printf(__IO usart_t* usart, const char* fmt, ...) -{ - printf_callback_t callback = (printf_callback_t) usart_transmit_byte; - volatile void* closure = usart; - va_list ap; - va_start(ap, fmt); - printf_format(fmt, callback, closure, ap); - va_end(ap); -} - -int usart2_enabled = 0; -int is_usart2_enabled() { - return usart2_enabled; -} - -int enable_usart2(uint32_t baud_rate) -{ - __IO gpio_port_t* port_a = enable_gpio(GPIO_PORT_A); - enable_hsi(&RCC, true); - - // Turn on the clock for the USART2 peripheral - set_usart2_clock_src(&RCC, USART_CLK_SRC_HSI16); - set_usart2_clock_enabled(&RCC, true); - - // Configure the I/O pins. Will use PA2 as TX and PA15 as RX so setup for - // alternate function - set_gpio_pin_mode(port_a, PIN_2, MODE_ALTERNATE); - set_gpio_pin_mode(port_a, PIN_15, MODE_ALTERNATE); - set_gpio_alternate_function(port_a, PIN_2, AFN_7); - set_gpio_alternate_function(port_a, PIN_15, AFN_3); - - // De-assert reset of USART2 - RCC.apb1rst1_r &= ~BIT(17); - - // Configure the USART - // disable USART first to allow setting of other control bits - // This also disables parity checking and enables 16 times oversampling - - USART2.c1.r = 0; - USART2.c2.r = 0; - USART2.c3.r = 0; - - usart_set_divisor(&USART2, 16000000 / baud_rate); - usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX); - - usart2_enabled = 1; -} diff --git a/03-refactor/src/vector.c b/03-refactor/src/vector.c deleted file mode 100644 index e69de29..0000000 diff --git a/Makefile.preamble b/Makefile.preamble new file mode 100644 index 0000000..f6e1370 --- /dev/null +++ b/Makefile.preamble @@ -0,0 +1,25 @@ +OPT?=-O +PREFIX?=arm-unknown-eabi- +CC=$(PREFIX)gcc +LD=$(PREFIX)ld +CFLAGS?=$(OPT) -mcpu=cortex-m4 -mthumb -g -lgcc -static -nostartfiles -Iinclude -Iinclude/arch/arm +LD_FLAGS?=-T linker/linker_script.ld -nostdlib --cref -Map linker/main.map -static + +TEST_PREFIX=x86_64-pc-linux-gnu- +TEST_CFLAGS=-Iinclude -Iinclude/arch/x86_64 -Itest_harness -g3 -ggdb -DFOR_TESTING -Wall + +all: _$(PREFIX)_obs/main.elf + +_$(PREFIX)_obs/main.bin: _$(PREFIX)_obs/main.elf + $(PREFIX)objcopy -O binary _$(PREFIX)_obs/main.elf _$(PREFIX)_obs/main.bin + +flash: _$(PREFIX)_obs/main.bin + st-flash write _$(PREFIX)_obs/main.bin 0x8000000 + +clean: + rm -rf _*_obs + rm -rf tests/build + rm -rf test_harness/*.a test_harness/*.o + +genmake: + ./genmake.pl > Makefile diff --git a/genmake.pl b/genmake.pl new file mode 100755 index 0000000..c4165a6 --- /dev/null +++ b/genmake.pl @@ -0,0 +1,128 @@ +#!/usr/bin/perl + +use File::Basename; +use File::Find; +use Digest::SHA qw(sha1_hex); + +# This script is designed to introspect C files and generate a makefile to use. + +sub header_deps { + my $file = @_[0]; + my @headers; + + if (open(my $fh, '<:encoding(UTF-8)', $file)) { + print STDERR "\x1b[35m[Trace] - Reading file $file\x1b[00m\n"; + push(@headers, $file); + + while (<$fh>) { + /#include\s+"(.*)"\s*$/ && push(@headers, header_deps("include/$1")); + } + } + + return @headers; +} + +my @files; +find(sub { + push @files, "$File::Find::name" if $_ =~ /.*\.c/ + }, "src/"); + +my @test_files; +find(sub { + push @test_files, "$File::Find::name" if $_ =~ /.*\.c/ + }, "tests/"); + +my @header_files; +find(sub { + push @header_files, "$File::Find::name" if $_ =~ /.*\.h/; + }, "include/" ); + +my $idempotency_hash=sha1_hex("@files @test_files @header_files"); + +if ("$ARGV[0]" eq "hash") { + print "$idempotency_hash\n"; + exit 0 +} + +my @obj_files; + +open(my $fh, '<:encoding(UTF-8)', "Makefile.preamble") + or die "Missing Makefile.preamble"; + +while (<$fh>) { + print "$_"; +} + +# Emit a rule that will rerun genmake if the c files do not match. +my $idempotency_cmd_make = + "/usr/bin/perl ./genmake.pl hash"; + +print "IDEMPOTENCY_HASH=$idempotency_hash\n"; + +my $arch_obs_dir = "_\$(PREFIX)_obs"; +print "CHEAT_PRE_MAKE := \$(shell mkdir -p $arch_obs_dir)\n"; + +foreach $file (@files) { + my $c_file = $file; + (my $file_no_ext = $file) =~ s/src\/(.*)\.c$/\1/g; + + my $obj_file = "$arch_obs_dir/${file_no_ext}.o"; + my $s_file = "${file_no_ext}.s"; + + push(@obj_files, $obj_file); + my @deps = header_deps($c_file); + + my $deps_as_join = join(" ", @deps); + + # Emit the rule to make the object file. + print "$obj_file: $deps_as_join\n\t"; + print "\@mkdir -p " . dirname($obj_file) . "\n\t"; + print '$(CC) -c ' . $c_file . ' -o ' . $obj_file . ' $(CFLAGS)' . "\n\n"; + + # Emit the rule to make the assembly file. + print "$s_file: $deps_as_join\n\t"; + print "\@mkdir -p " . dirname($obj_file) . "\n\t"; + print '$(CC) -S ' . $c_file . ' -o ' . $s_file . ' $(CFLAGS)' . "\n\n"; +} + +my $obj_files_deps = join(' ', @obj_files); + +my @tests_tgts; +foreach $file (@test_files) { + my $c_file = $file; + + my($basename, $directories, $suffix) = fileparse($file, qr/\.[^.]*/); + + my $outdir = $directories . "build/"; + my $outbinary = $outdir . $basename; + + my @deps = header_deps($c_file); + my $deps_as_join = join(" ", @deps); + + push (@test_tgts, "${outbinary}"); + print "${outbinary}: $deps_as_join $obj_files_deps test_harness/test_harness.a\n\t"; + print "mkdir -p " . dirname($outbinary) . "\n\t"; + print '$(CC) $(CFLAGS) -o' . ${outbinary} . ' ' . $c_file . ' ' . $obj_files_deps . " test_harness/test_harness.a\n\n"; + + print "$directories$basename:\n\t"; + print 'mkdir -p ' . $outdir . "\n\t"; + print 'PREFIX=$(TEST_PREFIX) CFLAGS="$(TEST_CFLAGS)" $(MAKE) ' . $outbinary . "\n\t"; + print $outbinary . "\n\n"; +} + +print "test_harness/test_harness.a: test_harness/test_harness.h test_harness/test_harness.c\n\t"; +print 'cd test_harness; $(MAKE) test_harness.a; cd ..' . "\n\n"; + +print "tests_: " . join(" ", @test_tgts) . "\n\t"; +print "" . join("\n\t", @test_tgts) . "\n\n"; + +print ".PHONY: tests\n"; +print "tests:\n\t"; +print 'PREFIX=$(TEST_PREFIX) CFLAGS="$(TEST_CFLAGS)" $(MAKE) tests_' . "\n\n"; + +print "FORCE:\n\t\n\n"; +print "$arch_obs_dir/main.elf: FORCE $obj_files_deps linker/linker_script.ld\n\t"; +print "([ \"\$\$($idempotency_cmd_make)\" != \"\$(IDEMPOTENCY_HASH)\" ] " + . "&& ./genmake.pl > Makefile && make $arch_obs_dir/main.elf ) " + . "|| " + . "\$(LD) -o $arch_obs_dir/main.elf \$(LD_FLAGS) $obj_files_deps\n\n"; diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h new file mode 100644 index 0000000..22d0987 --- /dev/null +++ b/include/arch/arm/arch.h @@ -0,0 +1,43 @@ +#ifndef ARCH_H_ +#define ARCH_H_ + +#ifndef ARCH_STM32L4 +#define ARCH_STM32L4 +#endif + +#define CORTEX_M4 + +#define enable_all_interrupts() \ + asm volatile(" cpsie i ") + + +#define DMA1_BASE (0x40020000) +#define DMA2_BASE (0x40020400) + +#define USART1_BASE (0x40013800) +#define USART2_BASE (0x40004400) + +#define GPIOA_BASE (0x48000000) +#define GPIOB_BASE (0x48000400) +#define GPIOC_BASE (0x48000800) +#define GPIOH_BASE (0x48001C00) + +#define SRAM1_BASE (0x20000000) +#define SRAM2_BASE (0x2000C000) + +#define SYSTEM_CONFIG_BLOCK_BASE (0xE000E008) +#define NVIC_BASE (0xE000E004) +#define RCC_BASE (0x40021000) + +#define SPI1_BASE (0x40013000) +#define SPI3_BASE (0x40003C00) + +#include +#ifndef DRY_RUN +_Static_assert(sizeof(void*) == sizeof(uint32_t), "Pointers must be 32 bits"); +#endif + +extern uint32_t DATA_SEGMENT_START; +extern uint32_t DATA_SEGMENT_STOP; + +#endif /* ARCH_H_ */ diff --git a/include/arch/stm32l4xxx/peripherals/apb.h b/include/arch/stm32l4xxx/peripherals/apb.h new file mode 100644 index 0000000..11fa7ab --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/apb.h @@ -0,0 +1,4 @@ +#ifndef H__APB_ +#define H__APB_ + +#endif /* H__APB_ */ diff --git a/include/arch/stm32l4xxx/peripherals/clock.h b/include/arch/stm32l4xxx/peripherals/clock.h new file mode 100644 index 0000000..6f628fd --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/clock.h @@ -0,0 +1,128 @@ +#ifndef CORE_CLOCK_H__ +#define CORE_CLOCK_H__ + +#include +#include "arch/stm32l4xxx/peripherals/rcc.h" + +#define PERIPH_BASE ((uint32_t)0x40000000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) +#define PWR_BASE (PERIPH_BASE + 0x7000) +#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */ + +#ifndef __IO +#define __IO volatile +#endif + +typedef struct { + __IO uint32_t cr; + __IO uint32_t csr; +} pwr_t; + +// typedef struct { +// __IO uint32_t acr; +// __IO uint32_t pecr; +// __IO uint32_t pdkeyr; +// __IO uint32_t pekeyr; +// __IO uint32_t prgkeyr; +// __IO uint32_t optkeyr; +// __IO uint32_t sr; +// __IO uint32_t obr; +// __IO uint32_t wrpr; +// } flash_t; + +// #define FLASH (*(flash_t*) (FLASH_R_BASE)) +#define PWR (*(pwr_t*)(PWR_BASE)) + +/* Valid values for the PLLR/PLLQ bits of the PLLCFG register. */ +typedef enum { + PLL_DIVISOR_2 = 1, + PLL_DIVISOR_4 = 3, + PLL_DIVISOR_6 = 5, + PLL_DIVISOR_8 = 7, + PLL_DIVISOR_OFF = 0, +} pll_divisor_t; + +/* Valid values for the PLLP bits off the PLLCFG register. */ +typedef enum { + PLLP_DIVISOR_7 = 1, + PLLP_DIVISOR_17 = 3, + PLLP_DIVISOR_OFF = 0, +} pllp_divisor_t; + +/* Valid values for the PLLM bits of the PLLCFG register. */ +typedef enum { + PLLM_DIVISOR_1 = 0, + PLLM_DIVISOR_2 = 1, + PLLM_DIVISOR_3 = 2, + PLLM_DIVISOR_4 = 3, + PLLM_DIVISOR_5 = 4, + PLLM_DIVISOR_6 = 5, + PLLM_DIVISOR_7 = 6, + PLLM_DIVISOR_8 = 7, +} pllm_divisor_t; + +/* Possible sources for the input clock. */ +typedef enum { + PLL_SRC_NONE = 0, + PLL_SRC_MSI = 1, + PLL_SRC_HSI = 2, + PLL_SRC_HSE = 3, +} pll_src_t; + +/* Valid sources for the system clock. */ +typedef enum { + SYSTEM_CLOCK_SRC_MSI = 0, + SYSTEM_CLOCK_SRC_HSI = 1, + SYSTEM_CLOCK_SRC_HSE = 2, + SYSTEM_CLOCK_SRC_PLL = 3, +} system_clock_src_t; + +#define E_BADPLLN (-2) +#define E_BADPLLP_DIV (-1) +#define E_TIMEOUT (-3) +#define E_NOT_OFF (-4) +#define E_BAD_ARG (-5) + +#define enable_hsi(rcc, enabled) do { \ + if (enabled) { \ + (rcc)->c_r |= BIT(8); \ + } else { \ + (rcc)->c_r &= ~BIT(8); \ + } \ +} while(0) + +/* + * Sets the system clock to a full 80Mhz. + */ +int set_system_clock_MHz(uint8_t mhz); + +/* + * Set the PLL on. + */ +int pll_on(); + +/* + * Set the PLL off. + */ +int pll_off(); + +/* + * Sets the source of the system clock. + */ +int set_system_clock_src(system_clock_src_t src); + +/* + * Configure the PLL. + */ +int configure_pll( + uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */); + +uint8_t get_clock_mhz(); + +#endif /* CORE_CLOCK_H__ */ diff --git a/include/arch/stm32l4xxx/peripherals/dma.h b/include/arch/stm32l4xxx/peripherals/dma.h new file mode 100644 index 0000000..f62a92b --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/dma.h @@ -0,0 +1,149 @@ +#ifndef CORE_DMA_H_ +#define CORE_DMA_H_ + +/* + * Header file for definining the DMA (Direct Memory Access). + * + * A DMA is used to perform data transfers between segments of memory + * or between memory and peripherals. + * + * There are 2 DMA's on the chip. Each with 7 channels. + */ + +#include "kern/common.h" +#include +#include + +#define DMA1 (* (dma_t*) DMA1_BASE) +#define DMA2 (* (dma_t*) DMA2_BASE) + +typedef enum { + DMA_SIZE_8_BITS = 0, + DMA_SIZE_16_BITS = 1, + DMA_SIZE_32_BITS = 2, +} dma_size_t; + +typedef enum { + DMA_PRIORITY_LEVEL_LOW = 0, + DMA_PRIORITY_LEVEL_MEDIUM = 1, + DMA_PRIORITY_LEVEL_HIGH = 2, + DMA_PRIORITY_LEVEL_VERY_HIGH = 3 +} dma_priority_level_t; + +typedef enum { + READ_FROM_PERIPHERAL = 0, + READ_FROM_MEMORY = 1, +} dma_dir_t; + +typedef struct { + +#define dma_cc_en (1 << 0) // channel enable +#define dma_cc_tcie (1 << 1) // transfer complete interrupt enable +#define dma_cc_htie (1 << 2) // half transfer interrupt enable +#define dma_cc_teie (1 << 3) // transfer error interrupt enable +#define dma_cc_dir (1 << 4) // data transfer direction +#define dma_cc_circ (1 << 5) // circular mode +#define dma_cc_pinc (1 << 6) // peripheral increment mode +#define dma_cc_minc (1 << 7) // memory increment mode +#define dma_cc_psize (3 << 8) // Peripheral size +#define dma_cc_msize (3 << 10) // Memory size +#define dma_cc_pl (3 << 12) // Priority level +#define dma_cc_mem2mem (1 << 14) // Memory to memory mode + + __IO uint32_t cc_r; + + /* Number of data to transfer. Can only store a short. */ + __IO uint32_t cndt_r; + + /* DMA channel peripheral address register. + * Defines a memory address if mem2mem is set. */ + __IO uint32_t cpa_r; + + /* DMA channel memory address register. + * Defines another perpipheral address if peripheral-periphal mode is set. */ + __IO uint32_t cma_r; + + __IO uint32_t reserved; +} dma_channel_config_t; + +typedef struct { + // DMA Interrupt status register. +#define dma_gif1 (1 << 0) // global interrupt flag for channel 1 +#define dma_tcif1 (1 << 1) // transfer complete (TC) flag for channel 1 +#define dma_htif1 (1 << 2) // half transfer (HT) flag for channel 1 +#define dma_teif1 (1 << 3) // transfer error (TE) flag for channel 1 +#define dma_gif2 (1 << 4) // global interrupt flag for channel 2 +#define dma_tcif2 (1 << 5) // transfer complete (TC) flag for channel 2 +#define dma_htif2 (1 << 6) // half transfer (HT) flag for channel 2 +#define dma_teif2 (1 << 7) // transfer error (TE) flag for channel 2 +#define dma_gif3 (1 << 8) // global interrupt flag for channel 3 +#define dma_tcif3 (1 << 9) // transfer complete (TC) flag for channel 3 +#define dma_htif3 (1 << 10) // half transfer (HT) flag for channel 3 +#define dma_teif3 (1 << 11) // transfer error (TE) flag for channel 3 +#define dma_gif4 (1 << 12) // global interrupt flag for channel 4 +#define dma_tcif4 (1 << 13) // transfer complete (TC) flag for channel 4 +#define dma_htif4 (1 << 14) // half transfer (HT) flag for channel 4 +#define dma_teif4 (1 << 15) // transfer error (TE) flag for channel 4 +#define dma_gif5 (1 << 16) // global interrupt flag for channel 5 +#define dma_tcif5 (1 << 17) // transfer complete (TC) flag for channel 5 +#define dma_htif5 (1 << 18) // half transfer (HT) flag for channel 5 +#define dma_teif5 (1 << 19) // transfer error (TE) flag for channel 5 +#define dma_gif6 (1 << 20) // global interrupt flag for channel 6 +#define dma_tcif6 (1 << 21) // transfer complete (TC) flag for channel 6 +#define dma_htif6 (1 << 22) // half transfer (HT) flag for channel 6 +#define dma_teif6 (1 << 23) // transfer error (TE) flag for channel 6 +#define dma_gif7 (1 << 24) // global interrupt flag for channel 7 +#define dma_tcif7 (1 << 25) // transfer complete (TC) flag for channel 7 +#define dma_htif7 (1 << 26) // half transfer (HT) flag for channel 7 +#define dma_teif7 (1 << 27) // transfer error (TE) flag for channel 7 + __IO uint32_t is_r; + + // DMA Interrupt flag clear register +#define dma_cgif1 (1 << 0) // global interrupt flag clear for channel 1 +#define dma_ctcif1 (1 << 1) // transfer complete flag clear for channel 1 +#define dma_chtif1 (1 << 2) // half transfer flag clear for channel 1 +#define dma_cteif1 (1 << 3) // transfer error flag clear for channel 1 +#define dma_cgif2 (1 << 4) // global interrupt flag clear for channel 2 +#define dma_ctcif2 (1 << 5) // transfer complete flag clear for channel 2 +#define dma_chtif2 (1 << 6) // half transfer flag clear for channel 2 +#define dma_cteif2 (1 << 7) // transfer error flag clear for channel 2 +#define dma_cgif3 (1 << 8) // global interrupt flag clear for channel 3 +#define dma_ctcif3 (1 << 9) // transfer complete flag clear for channel 3 +#define dma_chtif3 (1 << 10) // half transfer flag clear for channel 3 +#define dma_cteif3 (1 << 11) // transfer error flag clear for channel 3 +#define dma_cgif4 (1 << 12) // global interrupt flag clear for channel 4 +#define dma_ctcif4 (1 << 13) // transfer complete flag clear for channel 4 +#define dma_chtif4 (1 << 14) // half transfer flag clear for channel 4 +#define dma_cteif4 (1 << 15) // transfer error flag clear for channel 4 +#define dma_cgif5 (1 << 16) // global interrupt flag clear for channel 5 +#define dma_ctcif5 (1 << 17) // transfer complete flag clear for channel 5 +#define dma_chtif5 (1 << 18) // half transfer flag clear for channel 5 +#define dma_cteif5 (1 << 19) // transfer error flag clear for channel 5 +#define dma_cgif6 (1 << 20) // global interrupt flag clear for channel 6 +#define dma_ctcif6 (1 << 21) // transfer complete flag clear for channel 6 +#define dma_chtif6 (1 << 22) // half transfer flag clear for channel 6 +#define dma_cteif6 (1 << 23) // transfer error flag clear for channel 6 +#define dma_cgif7 (1 << 24) // global interrupt flag clear for channel 7 +#define dma_ctcif7 (1 << 25) // transfer complete flag clear for channel 7 +#define dma_chtif7 (1 << 26) // half transfer flag clear for channel 7 +#define dma_cteif7 (1 << 27) // transfer error flag clear for channel 7 + __IO uint32_t ifc_r; + + dma_channel_config_t channel_config[7]; + + __IO uint32_t reserved[5]; + + /* DMA channel selection register. */ +#define dma_c1s (0xF << 0) // DMA channel 1 selection. +#define dma_c2s (0xF << 4) // DMA channel 2 selection. +#define dma_c3s (0xF << 8) // DMA channel 3 selection. +#define dma_c4s (0xF << 12) // DMA channel 4 selection. +#define dma_c5s (0xF << 16) // DMA channel 5 selection. +#define dma_c6s (0xF << 20) // DMA channel 6 selection. +#define dma_c7s (0xF << 24) // DMA channel 7 selection. + __IO uint32_t csel_r; +} dma_t; + +static_assert(offsetof(dma_t, csel_r) == 0xA8, "Offset check failed."); + +#endif /* CORE_DMA_H_ */ diff --git a/include/arch/stm32l4xxx/peripherals/flash.h b/include/arch/stm32l4xxx/peripherals/flash.h new file mode 100644 index 0000000..28a3d6c --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/flash.h @@ -0,0 +1,20 @@ +#ifndef H__FLASH_ +#define H__FLASH_ + +#include "kern/common.h" + +/* + * Header file for dealing with flash. + */ + +#define FLASH_BASE 0x40022000 + +typedef struct { + __IO uint32_t ac_r; /* Flash access control register. */ + + /* TODO fill out the rest. */ +} PACKED flash_t; + +#define FLASH (*(__IO flash_t*)FLASH_BASE) + +#endif /* H__FLASH_ */ diff --git a/include/arch/stm32l4xxx/peripherals/gpio.h b/include/arch/stm32l4xxx/peripherals/gpio.h new file mode 100644 index 0000000..944d725 --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/gpio.h @@ -0,0 +1,66 @@ +#ifndef CORE_GPIO_H__ +#define CORE_GPIO_H__ + +#include "kern/common.h" +#include "arch/stm32l4xxx/peripherals/rcc.h" + +#include + +/* + * Structure defining the layout of the layout of the GPIO registers on the + * stm32l432 development board. + */ +typedef struct GPIO_PORT_STR { + /* Mode of each GPIO pin for this GPIO port. */ +#define gpio_mode_n(off) (3 << ((off) * 2)) + __IO uint32_t mode_r; /* Mode register */ + + /* Output type for each gpio pin in this port. */ +#define gpio_otype_n(off) (1 << (off)) + __IO uint32_t otype_r; + + /* GPIO port output speed. */ +#define gpio_ospeed_n(off) (3 << ((off) * 2)) + __IO uint32_t ospeed_r; + + /* GPIO port pull-up/pull-down register */ +#define gpio_pupd_n(off) (3 << ((off) * 2)) + __IO uint32_t pupd_r; + + /* GPIO port input data register. */ +#define gpio_idr_n(off) (1 << (off)) + __IO uint32_t id_r; + + /* GPIO port output data register. */ +#define gpio_odr_n(off) (1 << (off)) + __IO uint32_t od_r; + + /* GPIO port bit set/reset register. */ +#define gpio_bs_n(off) (1 << (off)) +#define gpio_br_n(off) (1 << (off)) + __IO uint32_t bsr_r; + + /* GPIO port configuration lock register. */ +#define gpio_lck_n(off) (1 << (off)) +#define gpio_lckk (1 << 16) + __IO uint32_t lck_r; + + /* Alternate function low-register. */ +#define gpio_afsel_n(off) (0xf << ((off) * 4)) + __IO uint32_t af_rl; + /* Alternate function high-register. */ + __IO uint32_t af_rh; + + /* GPIO port bit register. */ +#define gpio_br_n(off) (1 << (off)) + __IO uint32_t br_r; + + /* Analog switch control register. */ +#define gpio_asc_n(off) (1 << (off)) + __IO uint32_t asc_r; +} PACKED gpio_port_config_t; + +static_assert( + offsetof(gpio_port_config_t, asc_r) == 0x2C, "Offset check failed"); + +#endif diff --git a/include/arch/stm32l4xxx/peripherals/irq.h b/include/arch/stm32l4xxx/peripherals/irq.h new file mode 100644 index 0000000..52878ca --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/irq.h @@ -0,0 +1,89 @@ +#ifndef CORE_IRQ_H__ +#define CORE_IRQ_H__ + +#include + +/* + * Include file for interrupt service routines. + */ + +typedef enum { +#define IRQ_RESERVED(n) +#define IRQ(name_, uname, num) \ + IRQ_##uname = num, +#include "arch/stm32l4xxx/peripherals//isrs.inc" +#undef IRQ +#undef IRQ_RESERVED +} interrupt_t; + +/* Defines a set of interrupts so they may be enabled all at once. */ +typedef struct { + uint32_t sysirqs; /* System iterrupts. */ + uint32_t irqs[8]; +} interrupt_set_t; + +inline static void interrupt_set_add( + interrupt_set_t* interrupt_set, interrupt_t interrupt) +{ + if (interrupt < 16) { + interrupt_set->sysirqs |= 1 << interrupt; + return; + } + + interrupt -= 16; + int loc = interrupt / 32; + int off = interrupt % 32; + + interrupt_set->irqs[loc] |= 1 << off; +} + +inline static void interrupt_set_remove( + interrupt_set_t* interrupt_set, interrupt_t interrupt) +{ + if (interrupt < 16) { + interrupt_set->sysirqs &= ~(1 << interrupt); + return; + } + + interrupt -= 16; + int loc = interrupt / 32; + int off = interrupt % 32; + + interrupt_set->irqs[loc] &= ~(1 << off); +} + +/* + * The interrupt service routines. These link in the function `main` as the + * main function. + */ +extern const void* vectors[]; + +/* + * Defines an error state. This loops forever and defines a distinct flashing + * pattern to let the user know an unhandled ISR happened. + */ +void unhandled_isr(uint8_t val); + +#define enable_interrupt(val) \ + {interrupt_set_t itrset = { 0 }; \ + interrupt_set_add(&itrset, val); \ + enable_interrupts(&itrset);} + +#define disable_interrupt(val) \ + {interrupt_set_t itrset = { 0 }; \ + interrupt_set_add(&itrset, val); \ + disable_interrupts(&itrset);} + +/* + * Enables the provided interrupt. Note that if the interrupt is one of the + * system interrupts (first 16) this function has no effect because those + * interrupts are always enabled. + */ +void enable_interrupts(interrupt_set_t* interrupts); + +/* + * Enables the provided interrupt + */ +void disable_interrupts(interrupt_set_t* interrupts); + +#endif /* CORE_IRQ_H_ */ diff --git a/include/arch/stm32l4xxx/peripherals/isrs.inc b/include/arch/stm32l4xxx/peripherals/isrs.inc new file mode 100644 index 0000000..0682238 --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/isrs.inc @@ -0,0 +1,112 @@ +/* + * The following is a list of interrupts listed in a way + * that makes it easy to macro-process them by defining + * macro definitions for IRQ and IRQ_RESERVED alike followed + * by including this file. + */ +IRQ(on_reset, RESET, 1) +IRQ(on_nmi, NMI, 2) +IRQ(on_hard_fault, HARD_FAULT, 3) +IRQ(on_mem_manage, MEM_MANAGE, 4) +IRQ(on_bus_fault, BUS_FAULT, 5) +IRQ(on_usage_fault, USAGE_FAULT, 6) +IRQ_RESERVED(7) +IRQ_RESERVED(8) +IRQ_RESERVED(9) +IRQ_RESERVED(10) +IRQ(on_svc, SVC, 11) +IRQ(on_debug_mon, DEBUG_MON, 12) +IRQ_RESERVED(13) +IRQ(on_pendsv, PENDSV, 14) +IRQ(on_systick, SYSTICK, 15) +IRQ(on_wwdg_irq, WWDG_IRQ, 16) +IRQ(on_pvd_irq, PVD_IRQ, 17) +IRQ(on_tamper_stamp_irq, TAMPER_STAMP_IRQ, 18) +IRQ(on_rtc_wkup_irq, RTC_WKUP_IRQ, 19) +IRQ(on_flash_irq, FLASH_IRQ, 20) +IRQ(on_rcc_irq, RCC_IRQ, 21) +IRQ(on_exti0_irq, EXTI0_IRQ, 22) +IRQ(on_exti1_irq, EXTI1_IRQ, 23) +IRQ(on_exti2_irq, EXTI2_IRQ, 24) +IRQ(on_exti3_irq, EXTI3_IRQ, 25) +IRQ(on_exti4_irq, EXTI4_IRQ, 26) +IRQ(on_dma1_channel1_irq, DMA1_CHANNEL1_IRQ, 27) +IRQ(on_dma1_channel2_irq, DMA1_CHANNEL2_IRQ, 28) +IRQ(on_dma1_channel3_irq, DMA1_CHANNEL3_IRQ, 29) +IRQ(on_dma1_channel4_irq, DMA1_CHANNEL4_IRQ, 30) +IRQ(on_dma1_channel5_irq, DMA1_CHANNEL5_IRQ, 31) +IRQ(on_dma1_channel6_irq, DMA1_CHANNEL6_IRQ, 32) +IRQ(on_dma1_channel7_irq, DMA1_CHANNEL7_IRQ, 33) +IRQ(on_adc1_irq, ADC1_IRQ, 34) +IRQ(on_can1_tx, CAN1_TX, 35) +IRQ(on_can1_rx0, CAN1_RX0, 36) +IRQ(on_can1_rx1, CAN1_RX1, 37) +IRQ(on_can1_sce, CAN1_SCE, 38) +IRQ(on_exti9_5, EXTI9_5, 39) +IRQ(on_tim1_brk, TIM1_BRK, 40) +IRQ(on_tim1_up, TIM1_UP, 41) +IRQ(on_tim1_trg_com, TIM1_TRG_COM, 42) +IRQ(on_tim1_cc, TIM1_CC, 43) +IRQ(on_tim2, TIM2, 44) +IRQ(on_tim3, TIM3, 45) +IRQ(on_tim4, TIM4, 46) +IRQ(on_i2c1_ev, I2C1_EV, 47) +IRQ(on_i2c1_er, I2C1_ER, 48) +IRQ(on_i2c2_ev, I2C2_EV, 49) +IRQ(on_i2c2_er, I2C2_ER, 50) +IRQ(on_spi1, SPI1, 51) +IRQ(on_spi2, SPI2, 52) +IRQ(on_usart1, USART1, 53) +IRQ(on_usart2, USART2, 54) +IRQ(on_usart3, USART3, 55) +IRQ(on_exti15_10, EXTI15_10, 56) +IRQ(on_rtc_alarm, RTC_ALARM, 57) +IRQ(on_dfsdm1_flt3, DFSDM1_FLT3, 58) +IRQ(on_tim8_brk, TIM8_BRK, 59) +IRQ(on_tim8_up, TIM8_UP, 60) +IRQ(on_tim8_trg_com, TIM8_TRG_COM, 61) +IRQ(on_tim8_cc, TIM8_CC, 62) +IRQ(on_adc3, ADC3, 63) +IRQ(on_fmc, FMC, 64) +IRQ(on_sdmmc1, SDMMC1, 65) +IRQ(on_tim5, TIM5, 66) +IRQ(on_spi3, SPI3, 67) +IRQ(on_uart4, UART4, 68) +IRQ(on_uart5, UART5, 69) +IRQ(on_tim6_dacunder, TIM6_DACUNDER, 70) +IRQ(on_tim7, TIM7, 71) +IRQ(on_dma2_channel1, DMA2_CHANNEL1_IRQ, 72) +IRQ(on_dma2_channel2, DMA2_CHANNEL2_IRQ, 73) +IRQ(on_dma2_channel3, DMA2_CHANNEL3_IRQ, 74) +IRQ(on_dma2_channel4, DMA2_CHANNEL4_IRQ, 75) +IRQ(on_dma2_channel5, DMA2_CHANNEL5_IRQ, 76) +IRQ(on_dfsdm1_flt0, DFSDM1_FLT0, 77) +IRQ(on_dfsdm1_flt1, DFSDM1_FLT1, 78) +IRQ(on_dfsdm1_flt2, DFSDM1_FLT2, 79) +IRQ(on_comp, COMP, 80) +IRQ(on_lptim1, LPTIM1, 81) +IRQ(on_lptim2, LPTIM2, 82) +IRQ(on_otg_fs, OTG_FS, 83) +IRQ(on_dma2_channel6, DMA2_CHANNEL6, 84) +IRQ(on_dma2_channel7, DMA2_CHANNEL7, 85) +IRQ(on_lpuart1, LPUART1, 86) +IRQ(on_quadspi, QUADSPI, 87) +IRQ(on_i2c3_ev, I2C3_EV, 88) +IRQ(on_i2c3_er, I2C3_ER, 89) +IRQ(on_sai1, SAI1, 90) +IRQ(on_sai2, SAI2, 91) +IRQ(on_swpmi1, SWPMI1, 92) +IRQ(on_tsc, TSC, 93) +IRQ(on_lcd, LCD, 94) +IRQ(on_aes, AES, 95) +IRQ(on_rng, RNG, 96) +IRQ(on_fpu, FPU, 97) +IRQ(on_hash, HASH, 98) +IRQ(on_i2c4_ev, I2C4_EV, 99) +IRQ(on_i2c4_er, I2C4_ER, 100) +IRQ(on_dcmi, DCMI, 101) +IRQ(on_can2_tx, CAN2_TX, 102) +IRQ(on_can2_rx0, CAN2_RX0, 103) +IRQ(on_can2_rx1, CAN2_RX1, 104) +IRQ(on_can2_sce, CAN2_SCE, 105) +IRQ(on_dma2d, DMA2D, 106) diff --git a/include/arch/stm32l4xxx/peripherals/nvic.h b/include/arch/stm32l4xxx/peripherals/nvic.h new file mode 100644 index 0000000..1645a2d --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/nvic.h @@ -0,0 +1,46 @@ +#ifndef NVIC_H_ +#define NVIC_H_ + +#include "arch.h" +#include "kern/common.h" + +typedef __IO struct { +#define nvic_intlinesnum (0x0F << 0) + uint32_t ict_r; /* Interrupt control type register. */ + + uint8_t reserved0[0xF8]; + + uint32_t ise_r[8]; + + uint8_t reserved1[0x60]; + + uint32_t ice_r[8]; + + uint8_t reserved2[0x60]; + + uint32_t isp_r[8]; + + uint8_t reserved3[0x60]; + + uint32_t icp_r[8]; + + uint8_t reserved4[0x60]; + + uint32_t iab_r[8]; + + uint8_t reserved5[0xE0]; + + uint32_t ip_r[60]; +} nvic_t; + +static_assert(offsetof(nvic_t, ise_r) == 0x00FC, "Offset check failed"); +static_assert(offsetof(nvic_t, ice_r) == 0x017C, "Offset check failed"); +static_assert(offsetof(nvic_t, isp_r) == 0x01FC, "Offset check failed"); +static_assert(offsetof(nvic_t, icp_r) == 0x027C, "Offset check failed"); +static_assert(offsetof(nvic_t, iab_r) == 0x02FC, "Offset check failed"); +static_assert(offsetof(nvic_t, ip_r) == 0x03FC, "Offset check failed"); + +#define NVIC (* (nvic_t*) NVIC_BASE) + + +#endif /* NVIC_H_ */ diff --git a/include/arch/stm32l4xxx/peripherals/rcc.h b/include/arch/stm32l4xxx/peripherals/rcc.h new file mode 100644 index 0000000..de7b568 --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/rcc.h @@ -0,0 +1,132 @@ +#ifndef H__RCC_ +#define H__RCC_ + +#include "arch.h" +#include "kern/common.h" +#include + +typedef struct { + __IO uint32_t c_r; /* Clock control register. 0x00 */ + __IO uint32_t icsc_r; /* Internal clock srcs calibration register. 0x04 */ + __IO uint32_t cfg_r; /* clock confguration register. 0x08 */ + __IO uint32_t pllcfg_r; /* PLL Configuration register. 0x0c */ + __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */ + + __IO uint32_t reserved_1; /* Not used. offset 0x14. */ + + __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */ + __IO uint32_t cif_r; /* Clock interrupt flag regiseter. 0x1c */ + __IO uint32_t cic_r; /* Clock interrupt clear register. 0x20 */ + + __IO uint32_t reserved_2; /* Not used. offset 0x24. */ + + __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */ + __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */ + __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */ + + __IO uint32_t reserved_3; /* Not used. offset 0x34. */ + +#define rcc_lptim1rst (1 << 31) // Low Power Timer 1 reset +#define rcc_opamprst (1 << 30) // OPAMP interface reset +#define rcc_dac1rst (1 << 29) // DAC1 interface reset +#define rcc_pwrrst (1 << 28) // Power interface reset +#define rcc_can2rst (1 << 26) // CAN2 reset (this bit is reserved for STM32L47x/L48x devices) +#define rcc_can1rst (1 << 25) // CAN1 reset +#define rcc_crsrst (1 << 24) // CRS reset (this bit is reserved for STM32L47x/L48x devices) +#define rcc_i2c3rst (1 << 23) // I2C3 reset +#define rcc_i2c2rst (1 << 22) // I2C2 reset +#define rcc_i2c1rst (1 << 21) // I2C1 reset +#define rcc_uart5rst (1 << 20) // UART5 reset +#define rcc_uart4rst (1 << 19) // UART4 reset +#define rcc_usart3rst (1 << 18) // USART3 reset +#define rcc_usart2rst (1 << 17) // USART2 reset +#define rcc_reserved (1 << 16) // must be kept at reset value. +#define rcc_spi3rst (1 << 15) // SPI3 reset +#define rcc_spi2rst (1 << 14) // SPI2 reset +#define rcc_lcdrst (1 << 9) // interface reset (this bit is reserved for STM32L471/L4x5 devices) +#define rcc_tim7rst (1 << 5) // timer reset +#define rcc_tim6rst (1 << 4) // timer reset +#define rcc_tim5rst (1 << 3) // timer reset +#define rcc_tim4rst (1 << 2) // timer reset +#define rcc_tim3rst (1 << 1) // timer reset +#define rcc_tim2rst (1 << 0) // timer reset + __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */ + __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */ + __IO uint32_t apb2rst_r; /* APB Peripheral reset register. 0x40 */ + + __IO uint32_t reserved_4; /* Not used. offset 0x44. */ + +#define rcc_dma1en (1 << 0) /* DMA1 clock enable. */ +#define rcc_dma2en (1 << 1) /* DMA2 clock enable. */ +#define rcc_flashen (1 << 8) /* Flash memory interface clock enable. */ +#define rcc_crcen (1 << 12) /* CRC clock enable. */ +#define rcc_tscen (1 << 16) /* Touch sensing controller clock enable. */ +#define rcc_dmad2en (1 << 17) /* DMA2D clock enabled. */ + __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */ + +#define rcc_gpioen(port) (1 << (port)) +#define rcc_otgfsen (1 << 12) +#define rcc_adcen (1 << 13) +#define rcc_dcmien (1 << 14) +#define rcc_assen (1 << 16) +#define rcc_hashen (1 << 17) +#define rcc_rngen (1 << 18) + __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */ + __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */ + + __IO uint32_t reserved_5; /* Not used. offset 0x54. */ + + __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */ + __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */ + __IO uint32_t apb2en_r; /* APB2 Peripheral enable register. 0x60 */ + + __IO uint32_t reserved_6; /* Not used. offset 0x64. */ + + __IO uint32_t ahb1smen_r; /* 0x68 */ + __IO uint32_t ahb2smen_r; /* 0x6c */ + __IO uint32_t ahb3smen_r; /* 0x70 */ + + __IO uint32_t reserved_7; + + __IO uint32_t apb1smen_r1; /* 0x78 */ + __IO uint32_t apb1smen_r2; /* 0x7c */ + __IO uint32_t apb2smen_r; /* 0x80 */ + + __IO uint32_t reserved_8; + + __IO uint32_t ccip_r; /* 0x88 */ +} PACKED rcc_t; + +static_assert(offsetof(rcc_t, ccip_r) == 0x88, "Offset check failed."); + +#define RCC (*(__IO rcc_t*)RCC_BASE) + +/* Macros to operate on the RCC registers. */ + +/* Sets the HSE. rcc is the RCC to use, e is zero for off, non-zero for on. */ +#define set_hse(rcc, e) \ + do { \ + if (e) { \ + (rcc).c_r |= 1 << 16; \ + } else { \ + (rcc).c_r &= ~(1 << 16); \ + } \ + } while (0) + +/* Sets the HSI. rcc is the RCC to use, e is zero for off, non-zero for on. */ +#define set_hsi(rcc, e) \ + do { \ + if (e) { \ + (rcc).c_r |= 1 << 8; \ + } else { \ + (rcc).c_r &= ~(1 << 8); \ + } \ + } while (0) + +/* Checks to see if the hse is ready. */ +#define hse_ready(rcc) ((rcc).c_r & (1 << 17)) + +/* Checks to see if the hse is ready. */ +#define hsi_ready(rcc) ((rcc).c_r & (1 << 10)) + +#endif diff --git a/include/arch/stm32l4xxx/peripherals/spi.h b/include/arch/stm32l4xxx/peripherals/spi.h new file mode 100644 index 0000000..a39a0bb --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/spi.h @@ -0,0 +1,102 @@ +#ifndef CORE_SPI_H_ +#define CORE_SPI_H_ + +#include "kern/common.h" +#include "arch.h" + +#define SPI1 (*((spi_t*)(SPI1_BASE))) +#define SPI3 (*((spi_t*)(SPI3_BASE))) + +typedef enum { + SPI_BAUD_FPCLK_DIV_2 = 0, + SPI_BAUD_FPCLK_DIV_4 = 1, + SPI_BAUD_FPCLK_DIV_8 = 2, + SPI_BAUD_FPCLK_DIV_16 = 3, + SPI_BAUD_FPCLK_DIV_32 = 4, + SPI_BAUD_FPCLK_DIV_64 = 5, + SPI_BAUD_FPCLK_DIV_128 = 6, + SPI_BAUD_FPCLK_DIV_256 = 7, +} spi_baud_rate_t; + +typedef enum { + SPI_DATA_SIZE_NOT_USED_0 = 0, + SPI_DATA_SIZE_NOT_USED_1 = 1, + SPI_DATA_SIZE_NOT_USED_2 = 2, + SPI_DATA_SIZE_4_BITS = 3, + SPI_DATA_SIZE_5_BITS = 4, + SPI_DATA_SIZE_6_BITS = 5, + SPI_DATA_SIZE_7_BITS = 6, + SPI_DATA_SIZE_8_BITS = 7, + SPI_DATA_SIZE_9_BITS = 8, + SPI_DATA_SIZE_10_BITS = 9, + SPI_DATA_SIZE_11_BITS = 10, + SPI_DATA_SIZE_12_BITS = 11, + SPI_DATA_SIZE_13_BITS = 12, + SPI_DATA_SIZE_14_BITS = 13, + SPI_DATA_SIZE_15_BITS = 14, + SPI_DATA_SIZE_16_BITS = 15, +} spi_data_size_t; + +typedef __IO struct { + /* spi control register. */ +#define spi_bidimode (1 << 15) /* Bidirectional data mode enable. */ +#define spi_bidioe (1 << 14) /* Output enable in bidirectional mode */ +#define spi_crcen (1 << 13) /* Hardware CRC calculation enable */ +#define spi_crcnext (1 << 12) /* Transmit CRC next */ +#define spi_crcl (1 << 11) /* CRC length */ +#define spi_rxonly (1 << 10) /* Receive only mode enabled. */ +#define spi_ssm (1 << 9) /* Software slave management */ +#define spi_ssi (1 << 8) /* Internal slave select */ +#define spi_lsbfirst (1 << 7) /* Frame format */ +#define spi_spe (1 << 6) /* SPI enable */ +#define spi_br (7 << 3) /* SPI enable */ +#define spi_mstr (1 << 2) /* Master selection */ +#define spi_cpol (1 << 1) /* Clock polarity */ +#define spi_cpha (1 << 0) /* Clock phase */ + uint32_t c_r1; + + /* spi control register #2 */ +#define spi_ldma_tx (1 << 14) /* Last DMA transfer for transmission */ +#define spi_ldma_rx (1 << 13) /* Last DMA transfer for reception */ +#define spi_frxth (1 << 12) /* FIFO reception threshold */ +#define spi_ds (0xF << 8) /* Data size */ +#define spi_txeie (1 << 7) /* Tx buffer empty interrupt enable */ +#define spi_rxneie (1 << 6) /* RX buffer not empty interrupt enable */ +#define spi_errie (1 << 5) /* Error interrupt enable */ +#define spi_frf (1 << 4) /* Frame format */ +#define spi_nssp (1 << 3) /*: NSS pulse management */ +#define spi_ssoe (1 << 2) /* SS output enable */ +#define spi_txdmaen (1 << 1) /* Tx buffer DMA enable */ +#define spi_rxdmaen (1 << 0) /* Rx buffer DMA enable */ + uint32_t c_r2; + + /* spi status register. */ +#define spi_ftlvl (3 << 11) /* Transmisison level */ +#define spi_frlvl (3 << 9) /* Reception level */ +#define spi_fre (1 << 8) /* Frame format error */ +#define spi_bsy (1 << 7) /* Busy flag */ +#define spi_ovr (1 << 6) /* Overrun flag */ +#define spi_modf (1 << 5) /* Mode fault */ +#define spi_crcerr (1 << 4) /* CRC error flag */ +#define spi_txe (1 << 1) /* Transmit buffer empty */ +#define spi_rxne (1 << 0) /* Receive buffer not empty */ + uint32_t s_r; + + /* spi data register. Really only the least-significant 16 bits are used. + * reading from this register reads from the Rx FIFO while writing to it + * writes to the Tx FIFO. */ + __IO uint32_t d_r; + + /* spi CRC polynomial register. */ + uint32_t crcp_r; + + /* spi rx CRC register. */ + uint32_t rxcrc_r; + + /* spi tx CRC register. */ + uint32_t txcrc_r; +} spi_t; + +static_assert(offsetof(spi_t, txcrc_r) == 0x18, "Offset check failed."); + +#endif /* CORE_SPI_H_ */ diff --git a/include/arch/stm32l4xxx/peripherals/system.h b/include/arch/stm32l4xxx/peripherals/system.h new file mode 100644 index 0000000..b6ff0a6 --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/system.h @@ -0,0 +1,76 @@ +#ifndef CORE_SYSTEM_H_ +#define CORE_SYSTEM_H_ + +#include +#include "kern/common.h" + +typedef __IO struct { + uint32_t actl_r; /* Auxiliary Control Register, ACTLR on page 4-5 */ + + uint32_t reserved0; + +#define scb_enable (1 << 0) +#define scb_tickint (1 << 1) +#define scb_clksource (1 << 2) +#define scb_countflag (1 << 16) + uint32_t stcs_r; /* SysTick Control and Status Register */ + + uint32_t strv_r; /* SysTick Reload Value Register */ + uint32_t stcv_r; /* SysTick Current Value Register */ + uint32_t stc_r; /* SysTick Calibration Value Register */ + + uint8_t reserved1[3296]; + + uint32_t cpuid; /* CPUID Base Register, CPUID on page 4-5 */ + uint32_t ics_r; /* RO 0x00000000 Interrupt Control and State Register */ + uint32_t vto_r; /* Vector Table Offset Register */ + uint32_t airc_r; /* Application Interrupt and Reset Control Register */ + uint32_t sc_r; /* System Control Register */ + uint32_t cc_r; /* Configuration and Control Register. */ + uint32_t shp_r1; /* System Handler Priority Register 1 */ + uint32_t shp_r2; /* System Handler Priority Register 2 */ + uint32_t shp_r3; /* System Handler Priority Register 3 */ + uint32_t shcs_r; /* System Handler Control and State Register */ + uint32_t cfs_r; /* Configurable Fault Status Registers */ + uint32_t hfs_r; /* HardFault Status register */ + uint32_t dfs_r; /* Debug Fault Status Register */ + uint32_t mmfa_r; /* MemManage Address Registerb */ + uint32_t bfa_r; /* BusFault Address Registerb */ + uint32_t afs_r; /* Auxiliary Fault Status Register, AFSR on page 4-6 */ + uint32_t id_pf_r0; /* Processor Feature Register 0 */ + uint32_t id_pf_r1; /* Processor Feature Register 1 */ + uint32_t id_df_r0; /* Debug Features Register 0 */ + uint32_t id_af_r0; /* Auxiliary Features Register 0 */ + uint32_t id_mmf_r0; /* Memory Model Feature Register 0 */ + uint32_t id_mmf_r1; /* 0x00000000 Memory Model Feature Register 1 */ + uint32_t id_mmf_r2; /* Memory Model Feature Register 2 */ + uint32_t id_mmf_r3; /* Memory Model Feature Register 3 */ + uint32_t id_isa_r0; /* Instruction Set Attributes Register 0 */ + uint32_t id_isa_r1; /* Instruction Set Attributes Register 1 */ + uint32_t id_isa_r2; /* Instruction Set Attributes Register 2 */ + uint32_t id_isa_r3; /* Instruction Set Attributes Register 3 */ + uint32_t id_isa_r4; /* Instruction Set Attributes Register 4 */ + + uint8_t reserved2[20]; + + uint32_t cpac_r; /* Coprocessor Access Control Register */ + + uint8_t reserved3[372]; + + uint32_t sti_r; /* Software Triggered Interrupt Register */ +} system_control_block_t; + +#define ARM_SYSCFG_BASE 0xE000E008 +#define CHECK_OFFSET(member, expected) \ + static_assert(ARM_SYSCFG_BASE + offsetof(system_control_block_t, member) == expected, \ + "Offset check failed") + +CHECK_OFFSET(stcs_r, 0xE000E010); +CHECK_OFFSET(cpuid, 0xE000ED00); +CHECK_OFFSET(cpac_r, 0xE000ED88); +CHECK_OFFSET(id_mmf_r3, 0xE000ED5C); +CHECK_OFFSET(sti_r, 0xE000EF00); + +#define SCB (*(system_control_block_t*)SYSTEM_CONFIG_BLOCK_BASE) + +#endif diff --git a/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc new file mode 100644 index 0000000..66d347c --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc @@ -0,0 +1,100 @@ +AFN(CAN1_RX, 9, PA11) +AFN(CAN1_TX, 9, PA12) +AFN(COMP1_OUT, 12, PA0, 12, PB0, 6, PA11, 6, PA6) +AFN(COMP2_OUT, 12, PA2, 12, PA7, 12, PB5) +AFN(I2C1_SCL, 4, PA9, 4, PB6) +AFN(I2C1_SDA, 4, PA10, 4, PB7) +AFN(I2C1_SMBA, 4, PA14, 4, PA1, 4, PB5) +AFN(I2C3_SCL, 4, PA7) +AFN(I2C3_SDA, 4, PB4) +AFN(IR_OUT, 1, PA13) +AFN(JTCK_SWCLK, 0, PA14) +AFN(JTDI, 0, PA15) +AFN(JTDO_TRACESWO, 0, PB3) +AFN(JTMS_SWDIO, 0, PA13) +AFN(LPTIM1_ETR, 1, PB6) +AFN(LPTIM1_IN1, 1, PB5) +AFN(LPTIM1_IN2, 1, PB7) +AFN(LPTIM1_OUT, 1, PA14) +AFN(LPTIM2_ETR, 14, PA5) +AFN(LPTIM2_IN1, 14, PB1) +AFN(LPTIM2_OUT, 14, PA4, 14, PA8) +AFN(LPUART1_CTS, 8, PA6) +AFN(LPUART1_RTS_DE, 8, PB1) +AFN(LPUART1_RX, 8, PA3) +AFN(LPUART1_TX, 8, PA2) +AFN(MCO, 0, PA8) +AFN(NJTRST, 0, PB4) +AFN(QUADSPI_BK1_IO0, 10, PB1) +AFN(QUADSPI_BK1_IO1, 10, PB0) +AFN(QUADSPI_BK1_IO2, 10, PA7) +AFN(QUADSPI_BK1_IO3, 10, PA6) +AFN(QUADSPI_BK1_NCS, 10, PA2) +AFN(QUADSPI_CLK, 10, PA3) +AFN(SAI1_EXTCLK, 13, PA0, 13, PB0) +AFN(SAI1_FS_A, 13, PA9) +AFN(SAI1_FS_B, 13, PA14, 13, PA4, 13, PB6) +AFN(SAI1_MCLK_A, 13, PA3) +AFN(SAI1_MCLK_B, 13, PB4) +AFN(SAI1_SCK_A, 13, PA8) +AFN(SAI1_SCK_B, 13, PB3) +AFN(SAI1_SD_A, 13, PA10) +AFN(SAI1_SD_B, 13, PA13, 13, PB5) +AFN(SPI1_MISO, 5, PA11, 5, PA6, 5, PB4) +AFN(SPI1_MOSI, 5, PA12, 5, PA7, 5, PB5) +AFN(SPI1_NSS, 5, PA15, 5, PA4, 5, PB0) +AFN(SPI1_SCK, 5, PA1, 5, PA5, 5, PB3) +AFN(SPI3_MISO, 6, PB4) +AFN(SPI3_MOSI, 6, PB5) +AFN(SPI3_NSS, 6, PA15, 6, PA4) +AFN(SPI3_SCK, 6, PB3) +AFN(SWPMI1_IO, 12, PA8) +AFN(SWPMI1_RX, 12, PA14) +AFN(SWPMI1_SUSPEND, 12, PA15) +AFN(SWPMI1_TX, 12, PA13) +AFN(TIM15_BKIN, 14, PA9) +AFN(TIM15_CH1, 14, PA2) +AFN(TIM15_CH1N, 14, PA1) +AFN(TIM15_CH2, 14, PA3) +AFN(TIM16_BKIN, 14, PB5) +AFN(TIM16_CH1, 14, PA6) +AFN(TIM16_CH1N, 14, PB6) +AFN(TIM1_BKIN, 1, PA6) +AFN(TIM1_BKIN2, 2, PA11) +AFN(TIM1_BKIN2_COMP1, 12, PA11) +AFN(TIM1_BKIN_COMP2, 12, PA6) +AFN(TIM1_CH1, 1, PA8) +AFN(TIM1_CH1N, 1, PA7) +AFN(TIM1_CH2, 1, PA9) +AFN(TIM1_CH2N, 1, PB0) +AFN(TIM1_CH3, 1, PA10) +AFN(TIM1_CH3N, 1, PB1) +AFN(TIM1_CH4, 1, PA11) +AFN(TIM1_ETR, 1, PA12) +AFN(TIM2_CH1, 1, PA0, 1, PA15, 1, PA5) +AFN(TIM2_CH2, 1, PA1, 1, PB3) +AFN(TIM2_CH3, 1, PA2) +AFN(TIM2_CH4, 1, PA3) +AFN(TIM2_ETR, 14, PA0, 2, PA15, 2, PA5) +AFN(TSC_G2_IO1, 9, PB4) +AFN(TSC_G2_IO2, 9, PB5) +AFN(TSC_G2_IO3, 9, PB6) +AFN(TSC_G2_IO4, 9, PB7) +AFN(TSC_G3_IO1, 9, PA15) +AFN(USART1_CK, 7, PA8, 7, PB5) +AFN(USART1_CTS, 7, PA11, 7, PB4) +AFN(USART1_RTS_DE, 7, PA12, 7, PB3) +AFN(USART1_RX, 7, PA10, 7, PB7) +AFN(USART1_TX, 7, PA9, 7, PB6) +AFN(USART2_CK, 7, PA4) +AFN(USART2_CTS, 7, PA0) +AFN(USART2_RTS_DE, 7, PA1) +AFN(USART2_RX, 3, PA15, 7, PA3) +AFN(USART2_TX, 7, PA2) +AFN(USART3_CK, 7, PB0) +AFN(USART3_CTS, 7, PA6) +AFN(USART3_RTS_DE, 7, PA15, 7, PB1) +AFN(USB_CRS_SYNC, 10, PA10) +AFN(USB_DM, 10, PA11) +AFN(USB_DP, 10, PA12) +AFN(USB_NOE, 10, PA13) diff --git a/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc new file mode 100644 index 0000000..21c7234 --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc @@ -0,0 +1,26 @@ +PORT(A, 0) +PORT(A, 1) +PORT(A, 2) +PORT(A, 3) +PORT(A, 4) +PORT(A, 5) +PORT(A, 6) +PORT(A, 7) +PORT(A, 8) +PORT(A, 9) +PORT(A, 10) +PORT(A, 11) +PORT(A, 12) +PORT(A, 13) +PORT(A, 14) +PORT(A, 15) +PORT(B, 0) +PORT(B, 1) +PORT(B, 3) +PORT(B, 4) +PORT(B, 5) +PORT(B, 6) +PORT(B, 7) +PORT(C, 14) +PORT(C, 15) +PORT(H, 3) diff --git a/include/arch/stm32l4xxx/peripherals/usart.h b/include/arch/stm32l4xxx/peripherals/usart.h new file mode 100644 index 0000000..a1542f4 --- /dev/null +++ b/include/arch/stm32l4xxx/peripherals/usart.h @@ -0,0 +1,204 @@ +#ifndef H__USART_ +#define H__USART_ + +#include +#include +#include + +#include "kern/common.h" +#include "arch/stm32l4xxx/peripherals/rcc.h" +#include + +#define USART1 (* (usart_t*) USART1_BASE) +#define USART2 (* (usart_t*) USART2_BASE) + +/* + * Possible USART clock sources. + */ +typedef enum { + USART_CLK_SRC_PLK = 0, /* Clock derived from the SysClk. */ + USART_CLK_SRC_SYSCLK = 1, /* System clock. */ + USART_CLK_SRC_HSI16 = 2, /* 16MHz oscillator. */ + USART_CLK_SRC_LSE = 3 /* Low power 32kHz clock. */ +} usart_clk_src_t; + +typedef struct { + /* USART configuration registers 0x04 - 0x0c. */ +#define usart_ue (1 << 0) /* UART enable */ +#define usart_uesm (1 << 1) /* UART enabled in stop mode. */ +#define usart_re (1 << 2) /* reciever enabled. */ +#define usart_te (1 << 3) /* transmitter enabled. */ +#define usart_idleie (1 << 4) /* Idle interrupt enabled. */ +#define usart_rxneie (1 << 5) /* RXNEIE RXNE interrupt enable. */ +#define usart_tcie (1 << 6) +#define usart_txeie (1 << 7) +#define usart_peie (1 << 8) +#define usart_ps (1 << 9) +#define usart_pce (1 << 10) +#define usart_wake (1 << 11) +#define usart_m0 (1 << 12) +#define usart_mme (1 << 13) +#define usart_cmie (1 << 14) +#define usart_over8 (1 << 15) +#define usart_dedt (0xF << 16) +#define usart_deat (0xF << 21) +#define usart_rtoie (1 << 26) +#define usart_eobie (1 << 27) +#define usart_m1 (1 << 28) + __IO uint32_t c_r1; + __IO uint32_t c_r2; + + +#define usart_eie (1 << 0) // Error interrupt enable. +#define usart_iren (1 << 1) // IrDA mode enabled +#define usart_irlp (1 << 2) // IrDA low power +#define usart_hdsel (1 << 3) // Half duplex selection +#define usart_nack (1 << 4) // Smartcard NACK enable +#define usart_scen (1 << 5) // Smartocard mode enable +#define usart_dmar (1 << 6) // DMA enable reciever +#define usart_dmat (1 << 7) // DMA enable transmitter +#define usart_rtse (1 << 8) // RTS enable +#define usart_ctse (1 << 9) // CTS enable +#define usart_ctsie (1 << 10) // CTS interrupt enable +#define usart_onebit (1 << 11) // One sample bit method enable +#define usart_ovrdis (1 << 12) // Overrun disable +#define usart_ddre (1 << 13) // DMA Disable on reception error +#define usart_dem (1 << 14) // Driver enable mode +#define usart_dep (1 << 15) // Driver enable polarity selection +#define usart_scarcnt0 (1 << 17) +#define usart_scarcnt1 (1 << 18) +#define usart_scarcnt2 (1 << 19) +#define usart_wus0 (1 << 20) // Wakeup from STOP mode interrept flag selection +#define usart_wus1 (1 << 21) // Wakeup from STOP mode interrept flag selection +#define usart_wufie (1 << 22) // Wakeup from STOP mode interrup enable +#define usart_ucesm (1 << 23) // USART clock enable in STOP mode. +#define usart_tcbgtie (1 << 24) // Transmission complete before guard time interrupt + __IO uint32_t c_r3; + + /* USART baud rate register. */ + uint32_t br_r; + uint32_t gtp_r; + uint32_t rto_r; + uint32_t rq_r; + + /* USART ISR register. Offset = 0x1c*/ +#define usart_pe (1 << 0) // Parity error +#define usart_fe (1 << 1) // Framing error +#define usart_nf (1 << 2) // START bit noise detection flag. +#define usart_ore (1 << 3) // Overrun error +#define usart_dlie (1 << 4) // Idle line detected +#define usart_rxne (1 << 5) // Read data register not empty +#define usart_tc (1 << 6) // Transmission complete +#define usart_txe (1 << 7) // Transmit data register empty +#define usart_lbdf (1 << 8) // LIN break detection flag +#define usart_ctsif (1 << 9) // CTS interrupt flag +#define usart_cts (1 << 10) // CTS flag. +#define usart_rtof (1 << 11) // Receiever timeout +#define usart_eobf (1 << 12) // End of block flag +#define usart_abre (1 << 14) // Auto baud rate error +#define usart_abrf (1 << 15) // Auto baud rate flag +#define usart_busy (1 << 16) // Busy flag +#define usart_cmf (1 << 17) // Character match flag +#define usart_sbkf (1 << 18) // send break flag +#define usart_rwu (1 << 19) // receiver wakeup frlom mute mode. +#define usart_wuf (1 << 20) // Wakeup from stop mode flag +#define usart_teack (1 << 21) // Transmit enable acknowledge flag. +#define usart_reack (1 << 22) // Receieve enable acknowledge flag. +#define usart_tcbgt (1 << 25) // Transmission completer before guard time completion. + __IO uint32_t is_r; /* Interrupt service register. */ + +#define usart_pecf (1 << 0) // Parity error clear flag +#define usart_fecf (1 << 1) // Framing error clear flag +#define usart_ncf (1 << 2) // Noise detected clear flag +#define usart_orecf (1 << 3) // Overrun error clear flag +#define usart_idlecf (1 << 4) // Idle line detected clear flag +#define usart_tccf (1 << 6) // Transmission complete clear flag +#define usart_tcbgtcf (1 << 7) // Transmission completed before guard time clear flag +#define usart_lbdcf (1 << 8) // LIN break detection clear flag +#define usart_ctscf (1 << 9) // CTS clear flag +#define usart_rtocf (1 << 11) // Receiver timeout clear flag +#define usart_eobcf (1 << 12) // End of block clear flag +#define usart_cmcf (1 << 17) // Character match clear flag +#define usart_wucf (1 << 20) // Wakeup from Stop mode clear flag. + __IO uint32_t ic_r; + uint32_t rd_r; + uint32_t td_r; +} usart_t; + +static_assert(offsetof(usart_t, ic_r) == 0x20, "Offset assertion failed."); +static_assert(offsetof(usart_t, rd_r) == 0x24, "Offset assertion failed."); + +typedef enum { + OVERSAMPLE_8, + OVERSAMPLE_16 +} oversampling_mode_t; + +static inline void usart_set_divisor( + __IO usart_t* usart, + uint32_t usartdiv) +{ + if (usart->c_r1 & (1 << 15)) { + /* OVER8 is set. */ + usart->br_r = + (usartdiv & ~7) | + ((usartdiv & 7) >> 1); + } else { + /* OVER8 is not set. */ + usart->br_r = usartdiv; + } +} + +static inline void usart_set_oversampling_mode( + __IO usart_t* usart, + oversampling_mode_t mode) +{ + if (mode == OVERSAMPLE_8) { + usart->c_r1 |= 1 << 15; + } else { + usart->c_r1 &= ~(1 << 15); + } +} + +typedef enum { + USART_PARITY_DISABLED = 0, + USART_PARITY_EVEN = 2 << 9, + USART_PARITY_ODD = 3 << 9, +} usart_parity_t; + +typedef enum { + USART_ENABLE_TX = 0x02, + USART_ENABLE_RX = 0x01, + USART_ENABLE_DISABLED = 0x00, +} usart_enable_t; + +void usart_set_parity(__IO usart_t* usart, usart_parity_t parity); + +void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled); + +void usart_enable_dma(__IO usart_t* usart, usart_enable_t enabled); + +/* + * Send a byte on the usart, This command blocks until the data + * is fully sent. + */ +void usart_transmit_byte_sync(__IO usart_t* usart, uint8_t byte); + +void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); + +void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable); + +void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src); + +void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable); + +void usart_transmit_bytes_sync( + __IO usart_t* usart, const uint8_t* bytes, uint32_t n); + +void usart_transmit_str_sync(__IO usart_t* usart, const char* str); + +void usart_printf(__IO usart_t* usart, const char* fmt, ...); + +void usart_vprintf(__IO usart_t* usart, const char* fmt, va_list l); + + +#endif /* H__USART_ */ diff --git a/include/arch/x86_64/arch.h b/include/arch/x86_64/arch.h new file mode 100644 index 0000000..c17721d --- /dev/null +++ b/include/arch/x86_64/arch.h @@ -0,0 +1,37 @@ +#ifndef ARCH_H_ +#define ARCH_H_ + +#include "fake_env.h" + +#define ARCH_PC +#define enable_all_interrupts() do {} while(0) + +#define RCC_BASE (load_fake_rcc__()) + +#define DMA1_BASE (load_fake_ahb1__() + 0x0) +#define DMA2_BASE (load_fake_ahb1__() + 0x400) + +#define USART1_BASE (load_fake_apb2__() + 0x3800) +#define USART2_BASE (load_fake_apb1__() + 0x4400) + +#define GPIOA_BASE (load_fake_ahb2__() + 0x0) +#define GPIOB_BASE (load_fake_ahb2__() + 0x400) +#define GPIOC_BASE (load_fake_ahb2__() + 0x800) +#define GPIOH_BASE (load_fake_ahb2__() + 0x1C00) + +#define SRAM1_BASE (load_fake_sram1__() + 0x0) +#define SRAM2_BASE (load_fake_sram2__() + 0x0) + +#define SYSTEM_CONFIG_BLOCK_BASE (load_fake_scb__()) +#define NVIC_BASE (load_fake_nvic__()) + +#define SPI1_BASE (load_fake_spi1__()) +#define SPI3_BASE (load_fake_spi3__()) + +// Pretend there's a data segement at the start of SRAM1 for more accurate +// testing. +#define GHOST_DATA_SEGMENT_SIZE 1234 +#define DATA_SEGMENT_START (*((uint8_t*)SRAM1_BASE)) +#define DATA_SEGMENT_STOP (*(((uint8_t*)SRAM1_BASE) + GHOST_DATA_SEGMENT_SIZE)) + +#endif /* ARCH_H_ */ diff --git a/include/kern/common.h b/include/kern/common.h new file mode 100644 index 0000000..653279e --- /dev/null +++ b/include/kern/common.h @@ -0,0 +1,50 @@ +#ifndef COMMON__H +#define COMMON__H + +#include +#include +#include + +#define WEAK __attribute__((weak)) +#define NORETURN __attribute__((noreturn)) + +#ifndef static_assert +#define static_assert(a, b) +#endif + +/* Define __IO to be volatile if it's not already. */ +#ifndef __IO +#define __IO volatile +#endif + +#define CTZ(n) __builtin_ctz(n) + +#define bool int +#ifndef __cplusplus +#define true 1 +#define false 0 +#endif + +#define PACKED __attribute__((packed)) +#define BIT(n) (1 << (n)) + +#define RESERVED_CONCAT_IMPL(x, y) x ## y +#define RESERVED_MACRO_CONCAT(x, y) RESERVED_CONCAT_IMPL(x, y) +#define RESERVED(n) \ + bits_t RESERVED_MACRO_CONCAT(_r, __COUNTER__) :n + +#define RESERVE(type) \ + __IO type RESERVED_MACRO_CONCAT(_r, __COUNTER__) + +#define ptr2reg(ptr) \ + ((uint32_t) (ptrdiff_t) (ptr)) + +typedef __IO uint32_t bits_t; + +#define regset(reg, mask, val) \ + ((reg) = ((reg) & ~mask) | (val << CTZ(mask))) + +#define regget(reg, mask) \ + (((reg) & mask) >> (CTZ(mask))) + +#endif /* COMMON_H */ diff --git a/include/kern/delay.h b/include/kern/delay.h new file mode 100644 index 0000000..65a26d6 --- /dev/null +++ b/include/kern/delay.h @@ -0,0 +1,12 @@ +#ifndef H__DELAY__ +#define H__DELAY__ + +#include + +/* + * Loops and count-downs the delay, the time this takes depends on the speed + * of the clock. + */ +void delay(uint32_t delay); + +#endif /* H__DELAY__ */ diff --git a/include/kern/dma/dma_manager.h b/include/kern/dma/dma_manager.h new file mode 100644 index 0000000..0d17bd5 --- /dev/null +++ b/include/kern/dma/dma_manager.h @@ -0,0 +1,279 @@ +#ifndef PERI_DMA_H_ +#define PERI_DMA_H_ + +#include "kern/common.h" +#include "arch/stm32l4xxx/peripherals/dma.h" /* Access to the DMA registers. */ +#include "arch/stm32l4xxx/peripherals/irq.h" + +#define DMA_ERROR_CHANNEL_IN_USE 1 + +#define CAT2(x, y) x ## y +#define CAT1(v, c) CAT2(v, c) +#define DMA_RESERVED(dma) CAT1(dma ## _PERIPH_RESERVED, __COUNTER__) + +#define ALTERNATE0 0x0000 +#define ALTERNATE1 0x0100 +#define ALTERNATE2 0x0200 +#define ALTERNATE3 0x0300 + +#define DMA_N_CHANNELS 7 +typedef enum { + DMA1_PERIPH_ADC1 = 0, + DMA1_PERIPH_ADC2 = 1, + DMA1_PERIPH_ADC3 = 2, + DMA1_PERIPH_DFSDM1_FLT0 = 3, + DMA1_PERIPH_DFSDM1_FLT1 = 4, + DMA1_PERIPH_DFSDM1_FLT2 = 5, + DMA1_PERIPH_DFSDM1_FLT3 = 6, + + DMA_RESERVED(DMA1) = 7, + DMA1_PERIPH_SPI1_RX = 8, + DMA1_PERIPH_SPI1_TX = 9, + DMA1_PERIPH_SPI2_RX = 10, + DMA1_PERIPH_SPI2_TX = 11, + DMA1_PERIPH_SAI2_A = 12, + DMA1_PERIPH_SAI2_B = 13, + + DMA_RESERVED(DMA1) = 14, + DMA1_PERIPH_USART3_TX = 15, + DMA1_PERIPH_USART3_RX = 16, + DMA1_PERIPH_USART1_TX = 17, + DMA1_PERIPH_USART1_RX = 18, + DMA1_PERIPH_USART2_RX = 19, + DMA1_PERIPH_USART2_TX = 20, + + DMA_RESERVED(DMA1) = 21, + DMA1_PERIPH_I2C3_TX = 22, + DMA1_PERIPH_I2C3_RX = 23, + DMA1_PERIPH_I2C2_TX = 24, + DMA1_PERIPH_I2C2_RX = 25, + DMA1_PERIPH_I2C1_TX = 26, + DMA1_PERIPH_I2C1_RX = 27, + + DMA1_PERIPH_TIM2_CH3 = 28, + DMA1_PERIPH_TIM2_UP = 29, + DMA1_PERIPH_TIM16_CH1_1 = 30 | ALTERNATE0, + DMA1_PERIPH_TIM16_UP_1 = 30 | ALTERNATE1, /* Same as TIM16_CH1. */ + DMA_RESERVED(DMA1) = 31, + DMA1_PERIPH_TIM2_CH1 = 32, + DMA1_PERIPH_TIM16_CH1_2 = 33, + DMA1_PERIPH_TIM16_UP_2 = 33 | ALTERNATE1, /* Same as TIM16_CH1. */ + DMA1_PERIPH_TIM2_CH2 = 34, + DMA1_PERIPH_TIM2_CH4 = 34 | ALTERNATE1, /* Same as TIM2_CH2. */ + + + DMA1_PERIPH_TIM17_CH1_1 = 35, + DMA1_PERIPH_TIM17_UP_1 = 35 | ALTERNATE1, /* Same as TIM17_CH1 */ + DMA1_PERIPH_TIM3_CH3 = 36, + DMA1_PERIPH_TIM3_CH4 = 37, + DMA1_PERIPH_TIM3_UP = 37 | ALTERNATE1, /* Same as TIM3_CH4 */ + DMA1_PERIPH_TIM7_UP = 38, + DMA1_PERIPH_DAC_CH2 = 38 | ALTERNATE1, /* Same as TIM7_UP */ + DMA1_PERIPH_QUADSPI = 39, + DMA1_PERIPH_TIM3_CH1 = 40, + DMA1_PERIPH_TIM3_TRIG = 40 | ALTERNATE1, /* Same as TIM3_CH1 */ + DMA1_PERIPH_TIM17_CH1_2 = 41, + DMA1_PERIPH_TIM17_UP_2 = 41 | ALTERNATE1, /* Same as TIM17_CH1 */ + + DMA1_PERIPH_TIM4_CH1 = 42, + DMA_RESERVED(DMA1) = 43, + DMA1_PERIPH_TIM6_UP = 44, + DMA1_PERIPH_DAC_CH1 = 44 | ALTERNATE1, /* Same as TIM6_UP */ + DMA1_PERIPH_TIM4_CH2 = 45, + DMA1_PERIPH_TIM4_CH3 = 46, + DMA_RESERVED(DMA1) = 47, + DMA1_PERIPH_TIM4_UP = 48, + + DMA_DMA1_PERIHP_RESERVED5 = 49, + DMA1_PERIPH_TIM1_CH1 = 50, + DMA1_PERIPH_TIM1_CH2 = 51, + DMA1_PERIPH_TIM1_CH4 = 52, + DMA1_PERIPH_TIM1_TRIG = 52 | ALTERNATE1, /* Same as TIM1_TRIG */ + DMA1_PERIPH_TIM1_COM = 52 | ALTERNATE2, /* Same as TIM1_TRIG */ + DMA1_PERIPH_TIM15_CH1 = 53, + DMA1_PERIPH_TIM15_UP = 53 | ALTERNATE1, /* Same as TIM15_CH1 */ + DMA1_PERIPH_TIM15_TRIG = 53 | ALTERNATE2, /* Same as TIM15_CH1 */ + DMA1_PERIPH_TIM15_COM = 53 | ALTERNATE3, /* Same as TIM15_CH1 */ + DMA1_PERIPH_TIM1_UP = 54, + DMA1_PERIPH_TIM1_CH3 = 55, + + DMA2_DMA1_SWITCH__ = 56, + + DMA2_PERIPH_I2C4_RX = 56, + DMA2_PERIPH_I2C4_TX = 57, + DMA2_PERIPH_ADC1 = 58, + DMA2_PERIPH_ADC2 = 59, + DMA2_PERIPH_ADC3 = 60, + DMA2_PERIPH_DCMI_1 = 61, + DMA_RESERVED(DMA2) = 62, + + DMA2_PERIPH_SAI1_A_1 = 63, + DMA2_PERIPH_SAI1_B_1 = 64, + DMA2_PERIPH_SAI2_A = 65, + DMA2_PERIPH_SAI2_B = 66, + DMA_RESERVED(DMA2) = 67, + DMA2_PERIPH_SAI1_A_2 = 68, + DMA2_PERIPH_SAI1_B_2 = 69, + + DMA2_PERIPH_UART5_TX = 70, + DMA2_PERIPH_UART5_RX = 71, + DMA2_PERIPH_UART4_TX = 72, + DMA_RESERVED(DMA2) = 73, + DMA2_PERIPH_UART4_RX = 74, + DMA2_PERIPH_USART1_TX = 75, + DMA2_PERIPH_USART1_RX = 76, + + DMA2_PERIPH_SPI3_RX = 77, + DMA2_PERIPH_SPI3_TX = 78, + DMA_RESERVED(DMA2) = 79, + DMA2_PERIPH_TIM6_UP = 80, + DMA2_PERIPH_DAC_CH1 = 80 | ALTERNATE1, /* Same as TIM6_UP */ + DMA2_PERIPH_TIM7_UP = 81, + DMA2_PERIPH_DAC_CH2 = 81 | ALTERNATE1, /* Same as TIM7_UP */ + DMA_RESERVED(DMA2) = 82, + DMA2_PERIPH_QUADSPI = 83, + + DMA2_PERIPH_SWPMI1_RX = 84, + DMA2_PERIPH_SWPMI1_TX = 85, + DMA2_PERIPH_SPI1_RX = 86, + DMA2_PERIPH_SPI1_TX = 87, + DMA2_PERIPH_DCMI_2 = 88, + DMA2_PERIPH_LPUART1_TX = 89, + DMA2_PERIPH_LPUART1_RX = 90, + + + DMA2_PERIPH_TIM5_CH4 = 91, + DMA2_PERIPH_TIM5_TRIG = 91 | ALTERNATE1, /* Same as TIM5_CH4 */ + DMA2_PERIPH_TIM5_CH3 = 92, + DMA2_PERIPH_TIM5_UP = 92 | ALTERNATE1, /* Same as TIM5_CH3 */ + DMA_RESERVED(DMA2) = 93, + DMA2_PERIPH_TIM5_CH2 = 94, + DMA2_PERIPH_TIM5_CH1 = 95, + DMA2_PERIPH_I2C1_RX = 96, + DMA2_PERIPH_I2C1_TX = 97, + + DMA2_PERIPH_AES_IN_1 = 98, + DMA2_PERIPH_AES_OUT_1 = 99, + DMA2_PERIPH_AES_OUT_2 = 100, + DMA_RESERVED(DMA2) = 101, + DMA2_PERIPH_AES_IN_2 = 102, + DMA_RESERVED(DMA2) = 103, + DMA2_PERIPH_HASH_IN = 104, + + DMA2_PERIPH_TIM8_CH3 = 105, + DMA2_PERIPH_TIM8_UP = 105 | ALTERNATE1, /* Same as TIM8_CH3 */ + DMA2_PERIPH_TIM8_CH4 = 106, + DMA2_PERIPH_TIM8_TRIG = 106 | ALTERNATE1, /* Same as TIM8_CH4 */ + DMA2_PERIPH_TIM8_COM = 106 | ALTERNATE2, /* Same as TIM8_CH4 */ + DMA_RESERVED(DMA2) = 107, + DMA2_PERIPH_SDMMC1_1 = 108, + DMA2_PERIPH_SDMMC1_2 = 109, + DMA2_PERIPH_TIM8_CH1 = 110, + DMA2_PERIPH_TIM8_CH2 = 111, + + + DMA_PERIPH_SENTINEL, +} dma_peripheral_t; + + +/* Defines a DMA channel. */ +typedef struct { + uint8_t dma; /* 0 = DMA1, 1 = DMA2 */ + uint8_t chan; /* 0 - 6 */ +} dma_channel_t; + + +/* + * Defines a DMA channel allocated for memory-to-peripheral transfers. This + * structure is only nominally different from dma_channel_t in order to provide + * rudimentary type-checking. + */ +typedef struct { + dma_channel_t c_; +} dma_mem2p_channel_t; + +/* + * Defines a DMA channel allocated for peripheral-to-memory transfers. This + * structure is only nominally different from dma_channel_t in order to provide + * rudimentary type-checking. + */ +typedef struct { + dma_channel_t c_; +} dma_p2mem_channel_t; + +/* Defines a DMA channel allocated for mem2mem transfers. + * This structure is only nominally different from dma_channel_t + * in order to provide rudimentary type-checking. + */ +typedef struct { + dma_channel_t c_; +} dma_mem2mem_channel_t; + +#define DMA_CHAN_ERROR ((dma_channel_t) { .dma = 0xff, .chan = 0xff }) + +typedef struct { + bool transfer_complete_interrupt_enable; + bool half_transfer_interrupt_enable; + bool transfer_error_interrupt_enable; + + bool circular_mode; + bool peripheral_increment; + bool memory_increment; + + dma_size_t peripheral_block_size; + dma_size_t memory_block_size; + + dma_priority_level_t priority; +} dma_opts_t; + +#define DEFAULT_DMA_OPTS \ + ((dma_opts_t) { .memory_increment = 1, \ + .peripheral_increment = 0, \ + .transfer_complete_interrupt_enable = 0, \ + .half_transfer_interrupt_enable = 0, \ + .transfer_error_interrupt_enable = 0, \ + .circular_mode = 0, \ + .peripheral_block_size = DMA_SIZE_8_BITS, \ + .memory_block_size = DMA_SIZE_8_BITS, \ + .priority = DMA_PRIORITY_LEVEL_MEDIUM }) + +dma_p2mem_channel_t select_dma_channel_p2mem( + dma_peripheral_t peripheral, + dma_opts_t* opts_in, + int* error); + +dma_mem2p_channel_t select_dma_channel_mem2p( + dma_peripheral_t peripheral, + dma_opts_t* opts_in, + int* error); + +/* Returns a dma channel used for memory-to-memory transfers. + * + * channel - the channel this dma should use. The channel should + * be on the range [0-13]. The channels [0-6] refer to the 7 channels + * on DMA1, where channels [7-13] refer to the 7 channels on DMA2. + * + * If `channel` is -1, then the highest unused dma channel is selected. + */ +dma_mem2mem_channel_t select_dma_channel_mem2mem( + int channel, + dma_opts_t* opts, + int* error_out); + +void dma_mem2p_initiate_transfer( + dma_mem2p_channel_t chan, const void* from_loc, uint16_t nblocks); + +void dma_p2mem_initiate_transfer( + dma_p2mem_channel_t chan, void* to_loc, uint16_t nblocks); + +void dma_mem2mem_initiate_transfer( + dma_mem2mem_channel_t chan, + void* to_loc, + const void* from_loc, + uint16_t nblocks); + +void release_dma_channel(dma_channel_t chan); + +interrupt_t dma_channel_get_interrupt(dma_channel_t chan); + +#endif diff --git a/include/kern/gpio/gpio_manager.h b/include/kern/gpio/gpio_manager.h new file mode 100644 index 0000000..922a423 --- /dev/null +++ b/include/kern/gpio/gpio_manager.h @@ -0,0 +1,187 @@ +#ifndef KERN_GPIO_GPIO_MANAGE_H_ +#define KERN_GPIO_GPIO_MANAGE_H_ + +#include "kern/common.h" +#include "arch/stm32l4xxx/peripherals/gpio.h" + +#define GPIO_ERROR_IN_USE 1 +#define GPIO_ERROR_INVALID_PIN_FOR_ALTERNATE_FUNCTION 2 +#define GPIO_ERROR_INVALID_PIN 3 + +typedef enum { +/* Creates vaules GPIO_PIN_ i.e. GPIO_PIN_A0 */ +#define PORT(p, pn) \ + GPIO_PIN_P ## p ## pn, +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" +#undef PORT + + N_GPIO_PINS +} gpio_pin_t; + +/* Alternate functions. */ +typedef enum { +#define AFN(fn, ...) \ + GPIO_ALTERNATE_FUNCTION_ ## fn, +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc" +#undef AFN + GPIO_ALTERNATE_FUNCTION_EVENTOUT, +} gpio_alternate_function_t; + +#define gpio_pin_for_alternate_function(af) ((af) / 16) +#define gpio_pin_out_of_range(pin) \ + ((pin) < 0 || (pin) >= N_GPIO_PINS) + +typedef enum { + GPIO_PORT_A, + GPIO_PORT_B, + GPIO_PORT_C, + GPIO_PORT_D, + GPIO_PORT_E, + GPIO_PORT_F, + GPIO_PORT_G, + GPIO_PORT_H, + GPIO_PORT_I, + + N_GPIO_PORTS, +} gpio_port_t; + +typedef enum { + GPIO_MODE_INPUT, + GPIO_MODE_OUTPUT, + GPIO_MODE_ALTERNATE, + GPIO_MODE_ANALOG +} gpio_mode_t; + +/* + * Enum defining the pin speeds that are possible. + */ +typedef enum { + SPEED_2MHZ = 0, + SPEED_10MHZ = 1, + SPEED_50MHZ = 3, +} gpio_speed_t; + +typedef enum { + GPIO_OUTPUT_TYPE_PUSH_PULL, + GPIO_OUTPUT_TYPE_OPEN_DRAIN +} gpio_output_type_t; + +typedef enum { + GPIO_OUTPUT_SPEED_LOW, + GPIO_OUTPUT_SPEED_MEDIUM, + GPIO_OUTPUT_SPEED_HIGH, + GPIO_OUTPUT_SPEED_VERY_HIGH, +} gpio_output_speed_t; + +typedef enum { + GPIO_PULL_DIR_NONE, + GPIO_PULL_DIR_UP, + GPIO_PULL_DIR_DOWN, +} gpio_pull_dir_t; + +/* Returns the appropriate gpio_port for the provided pin. */ +inline static gpio_port_t get_port_for_pin(gpio_pin_t pin) +{ + switch (pin) { +#define PORT(p, pn) \ + case GPIO_PIN_P ## p ## pn: return GPIO_PORT_ ## p; +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" +#undef PORT + case N_GPIO_PINS: return N_GPIO_PORTS; + } + + /* Should be unreachable. */ +} + +#define DEFAULT_GPIO_OPTS_OUTPUT \ + (gpio_pin_opts_t) { \ + .mode = GPIO_MODE_OUTPUT, \ + .pull_dir = GPIO_PULL_DIR_DOWN, \ + .output_opts.speed = GPIO_OUTPUT_SPEED_MEDIUM, \ + .output_opts.type = GPIO_OUTPUT_TYPE_PUSH_PULL, \ + } + +#define DEFAULT_GPIO_OPTS_INPUT \ + (gpio_pin_opts_t) { \ + .mode = GPIO_MODE_OUTPUT, \ + .pull_dir = GPIO_PULL_DIR_DOWN, \ + } + +typedef struct { + gpio_mode_t mode; + gpio_pull_dir_t pull_dir; + + union { + struct { + } input_opts; + + struct { + gpio_output_speed_t speed; + gpio_output_type_t type; + } output_opts; + + struct { + uint8_t function; + } alternate_opts; + + struct { + } analog_opts; + }; +} gpio_pin_opts_t; + +/* Differentiates at compile-time from the a gpio_pin_t enum value and a pin + * that's been reserved. */ +typedef struct { + gpio_pin_t v_; +} gpio_reserved_pin_t; + +/* Returns a pointer to the GPIO pin bus and offset. This is useful for when + * raw access to the values are needed. I.e. time critical applications. */ +void get_gpio_pin_port_off( + gpio_pin_t pin, gpio_port_config_t** out_cfg, int* out_off); + +/* Sets the given GPIO pin to high. */ +void set_gpio_pin_high(gpio_reserved_pin_t pin); + +/* Sets the given GPIO pin to low. */ +void set_gpio_pin_low(gpio_reserved_pin_t pin); + +/** returns true if a GPIO pin is in use. */ +bool gpio_pin_in_use(gpio_pin_t pin); + +/* + * Reserve the provided GPIO pin using the opts provided. + * + * sets error_out to GPIO_ERROR_IN_USE if the GPIO pin could not be reserved + * because it already has been reserved. + * + * The function will automatically enable the correct GPIO port bus. + */ +gpio_reserved_pin_t reserve_gpio_pin( + gpio_pin_t pin, gpio_pin_opts_t* opts, int* error_out); + +/* Enables and returns the pin reserved for the alternate function. + * + * If the `hint` parameter is defined (non -1) the manager will try + * to reserve that pin for the alternate function and fail if it can't. + * + * If `hint` is -1 then the first available pin for that alternate function + * will be reserved and returned. + * + * + */ +gpio_reserved_pin_t gpio_enable_alternate_function( + gpio_alternate_function_t fn, + gpio_pin_t hint, + int* error_out); + +/* + * Releases the GPIO pin so it can be reserved again in the future. + * + * The pin is reset during this process and if there are no more reserved pins + * on the corresponding port this function will disable the port. (last one out + * gets the lights.). + */ +void release_gpio_pin(gpio_reserved_pin_t gpio_pin); + +#endif /* KERN_GPIO_GPIO_MANAGE_H_ */ diff --git a/include/kern/gpio/sysled.h b/include/kern/gpio/sysled.h new file mode 100644 index 0000000..b2c9056 --- /dev/null +++ b/include/kern/gpio/sysled.h @@ -0,0 +1,11 @@ +/* + * Headers for interacting and managing the system LED. + */ +#ifndef SYSLED_H_ +#define SYSLED_H_ + +#include "kern/gpio/gpio_manager.h" + +gpio_reserved_pin_t get_sysled(); + +#endif diff --git a/include/kern/init.h b/include/kern/init.h new file mode 100644 index 0000000..737b85f --- /dev/null +++ b/include/kern/init.h @@ -0,0 +1,67 @@ +#ifndef INIT_H_ +#define INIT_H_ + +/** Globals annotated with _no_init will not be set during init1 bootup + * where the data segement is loaded from flash and the bss segment is + * cleared. + * + * This is useful for routines that run in the init0 boot procedure + * that need persistent globals. + * + * Note that initializing a global annotated with _no_init will have + * no effect as the variable will remain uninitialized until explicitly + * set by by the program. + */ +#define _no_init \ + __attribute((__section__(".noinit"))) + +#define init0 \ + static void init0fn(); \ + static __attribute((__section__(".init0"))) \ + __attribute((__used__)) \ + void(*init0_ptr)() = init0fn; \ + static void init0fn +#define init1 \ + static void init1fn(); \ + static __attribute((__section__(".init1"))) \ + __attribute((__used__)) \ + void(*init1_ptr)() = init1fn; \ + static void init1fn +#define init2 \ + static void init2fn(); \ + static __attribute((__section__(".init2"))) \ + __attribute((__used__)) \ + void(*init2_ptr)() = init2fn; \ + static void init2fn +#define init3 \ + static void init3fn(); \ + static __attribute((__section__(".init3"))) \ + __attribute((__used__)) \ + void(*init3_ptr)() = init3fn; \ + static void init3fn +#define init4 \ + static void init4fn(); \ + static __attribute((__section__(".init4"))) \ + __attribute((__used__)) \ + void(*init4_ptr)() = init4fn; \ + static void init4fn +#define init5 \ + static void init5fn(); \ + static __attribute((__section__(".init5"))) \ + __attribute((__used__)) \ + void(*init5_ptr)() = init5fn; \ + static void init5fn +#define init6 \ + static void init6fn(); \ + static __attribute((__section__(".init6"))) \ + __attribute((__used__)) \ + void(*init6_ptr)() = init6fn; \ + static void init6fn +#define init7 \ + static void init7fn(); \ + static __attribute((__section__(".init7"))) \ + __attribute((__used__)) \ + void(*init7_ptr)() = init7fn; \ + static void init7fn + +#endif /* INIT_H_ */ diff --git a/include/kern/lib.h b/include/kern/lib.h new file mode 100644 index 0000000..be0e8e9 --- /dev/null +++ b/include/kern/lib.h @@ -0,0 +1,10 @@ +#ifndef LIB_H_ +#define LIB_H_ + +#include + +void hexify(uint32_t v, char* into); + +void decimalify(int v, char* into); + +#endif diff --git a/include/kern/log.h b/include/kern/log.h new file mode 100644 index 0000000..5e49def --- /dev/null +++ b/include/kern/log.h @@ -0,0 +1,12 @@ +#ifndef LOG_H_ +#define LOG_H_ + +/* + * Defines logging capabilities. This logging unit will enable logging on + * the systems main USART output. + */ + +/** Similar to fprintf, but with a stripped-down format-string DSL. */ +void klogf(const char* fmt, ...); + +#endif diff --git a/include/kern/mem.h b/include/kern/mem.h new file mode 100644 index 0000000..c0999f5 --- /dev/null +++ b/include/kern/mem.h @@ -0,0 +1,32 @@ +#ifndef MEM_H_ +#define MEM_H_ + +#include "arch.h" +#include + +#define DATA_SEGMENT_STOP_ADDR ((uint8_t*) &DATA_SEGMENT_STOP) +#define DATA_SEGMENT_START_ADDR ((uint8_t*) &DATA_SEGMENT_START) + +#define MAX_HEAP_SIZE \ + ((16384 - (DATA_SEGMENT_STOP_ADDR - DATA_SEGMENT_START_ADDR)) / 4 * 4) + +/* allocates memory on the head, which is stored in sram2 */ +void* halloc(size_t n); + +/* Frees the memory allocated by halloc. */ +void hfree(void* mem); + +#ifdef FOR_TESTING + +void* debug_halloc_get_next_ptr(void* ptr); + +void* debug_halloc_get_prev_ptr(void* ptr); + +int debug_halloc_assert_consistency(char* error, size_t len); + +void debug_print_blocks(); + +#endif + + +#endif diff --git a/include/kern/string.h b/include/kern/string.h new file mode 100644 index 0000000..3c9f0b4 --- /dev/null +++ b/include/kern/string.h @@ -0,0 +1,6 @@ +#ifndef STRING_H_ +#define STRING_H_ + +void kstrcpy(char* into, const char* from); + +#endif /* STRING_H_ */ diff --git a/linker/linker_script.ld b/linker/linker_script.ld new file mode 100644 index 0000000..9a9f5b3 --- /dev/null +++ b/linker/linker_script.ld @@ -0,0 +1,55 @@ +MEMORY +{ + flash : org = 0x08000000, len = 256k + sram1 : org = 0x20000000, len = 48k + sram2 : org = 0x10000000, len = 16k +} + +SECTIONS +{ + /* This is where the code goes. */ + . = ORIGIN(flash); + .text : { + *(.vectors); /* All .vector sections go here. */ + *(.text); /* All .text sections go here. */ + } >flash + + .data : { + /* Data segment as defined in the flash. */ + INIT_DATA_VALUES = LOADADDR(.data); + + /* Data segment where it will be in memory. */ + DATA_SEGMENT_START = .; + *(.data); + DATA_SEGMENT_STOP = .; + + INIT_ROUTINES_FLASH_START = + LOADADDR(.data) + (DATA_SEGMENT_STOP - DATA_SEGMENT_START); + + INITS_START = .; + *(.init0); + *(.init1); + *(.init2); + *(.init3); + *(.init4); + *(.init5); + *(.init6); + *(.init7); + INITS_END = .; + + INIT_ROUTINES_FLASH_STOP = + LOADADDR(.data) + (INITS_END - DATA_SEGMENT_START); + + /* Align by 4 so we can optimize the copier to use uint32's. */ + . = ALIGN(0x04); + + *(.noinit); + } >sram1 AT>flash + + BSS_START = .; + .bss : { + *(.bss); + . = ALIGN(0x04); + } > sram1 + BSS_END = .; +} diff --git a/src/arch/stm32l4xxx/peripherals/clock.c b/src/arch/stm32l4xxx/peripherals/clock.c new file mode 100644 index 0000000..9051572 --- /dev/null +++ b/src/arch/stm32l4xxx/peripherals/clock.c @@ -0,0 +1,117 @@ +/* + * This file sets the system clock to its full glory of 80Mhz + */ + +#include "arch/stm32l4xxx/peripherals/clock.h" +#include "arch/stm32l4xxx/peripherals/flash.h" + +#include "kern/init.h" + +#include + +#define TIMEOUT 10000 + + +int pll_off() +{ + uint32_t c; + + RCC.c_r &= ~BIT(24); /* Turn off pll. */ + for (c = 0; c < TIMEOUT && RCC.c_r & BIT(25); ++c) + ; /* Wait for OFF. */ + + if (c == TIMEOUT) { + return E_TIMEOUT; + } + + return 0; +} + +int pll_on() +{ + uint32_t c; + + RCC.c_r |= BIT(24); /* Turn on PLL. */ + for (c = 0; c < TIMEOUT && !(RCC.c_r & BIT(25)); ++c) + ; /* Wait for RDY. */ + + if (c == TIMEOUT) { + return E_TIMEOUT; + } + + return 0; +} + +int configure_pll( + uint8_t pllp_div_factor, pll_divisor_t pllr, /* System clock divisor. */ + pll_divisor_t pllq, /* Divison factor for PLL48M1CLK. */ + pllp_divisor_t pllp, /* Divison factor for PLLSAI2CLK. */ + uint8_t plln, /* PLL numerator. */ + pllm_divisor_t pllm, /* PLL denominator. */ + pll_src_t pllsrc /* PLL source */) +{ + if (RCC.c_r & BIT(25)) { + /* PLL must be off to configure it. */ + return E_NOT_OFF; + } + + /* Make sure inputs are valid. */ + if (pllp_div_factor == 1 || pllp_div_factor > 31) { + return E_BADPLLP_DIV; + } + if (plln < 8 || plln > 86) { + return E_BADPLLN; + } + + RCC.pllcfg_r = (pllp_div_factor << 27) | (pllr << 24) | (pllq << 20) | + (pllp << 16) | (plln << 8) | (pllm << 4) | (pllsrc << 0); + + return 0; +} + +static _no_init uint8_t clock_mHz; +uint8_t get_clock_mhz() +{ + return clock_mHz; +} + +int set_system_clock_MHz(uint8_t mhz) +{ + clock_mHz = mhz; + + /* Set the source of the system colck to MSI temporarily. */ + set_system_clock_src(SYSTEM_CLOCK_SRC_MSI); + + if (mhz <= 8 || mhz > 80) { + return E_BAD_ARG; + } + + pll_off(); + + configure_pll( + 0 /* pllp_div_factor */, PLL_DIVISOR_4 /* pllr: VCO / 4 = mhz MHz. */, + PLL_DIVISOR_4 /* pllq: VCO / 4 = mhz MHz */, PLLP_DIVISOR_7 /* pllp */, + + /* The following set the frequency of VCO to (mhz*4)MHz: mhz * 1 * 4MHz. + */ + mhz /* plln | mhz */, PLLM_DIVISOR_1 /* pllm | 01 */, + PLL_SRC_MSI /* pll src | 04 Mhz */); + + pll_on(); + + /* Configure the flash to have 4 wait states. This is required at + * 80 MHz. */ + FLASH.ac_r &= ~0x07; + FLASH.ac_r |= 0x04; + + /* Set the source of the system colck to PLL. */ + set_system_clock_src(SYSTEM_CLOCK_SRC_PLL); + return 0; +} + +int set_system_clock_src(system_clock_src_t src) +{ + uint8_t value = RCC.cfg_r & ~0x03; + RCC.cfg_r = value | src; + return 0; +} diff --git a/src/arch/stm32l4xxx/peripherals/irq.c b/src/arch/stm32l4xxx/peripherals/irq.c new file mode 100644 index 0000000..364b9a7 --- /dev/null +++ b/src/arch/stm32l4xxx/peripherals/irq.c @@ -0,0 +1,96 @@ +#include "arch/stm32l4xxx/peripherals/irq.h" +#include "arch/stm32l4xxx/peripherals/gpio.h" +#include "arch/stm32l4xxx/peripherals/nvic.h" + +#include "arch.h" +#include "kern/delay.h" +#include "kern/gpio/gpio_manager.h" + +#define IRQ_RESERVED(n) +#define IRQ(name, uname_, n) \ + void WEAK name () { \ + unhandled_isr(n); \ + } +#include "arch/stm32l4xxx/peripherals/isrs.inc" +#undef IRQ_RESERVED +#undef IRQ + +void isr_simple_pin_on() +{ + int ec; + gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; + gpio_reserved_pin_t pin3 = reserve_gpio_pin(GPIO_PIN_PB3, &opts, &ec); + + set_gpio_pin_high(pin3); +} + +#define IRQ_RESERVED(n) 0, +#define IRQ(name, uname_, n) name, +const void* vectors[] __attribute__((section(".vectors"))) = { + (void*)0x2000c000, /* Top of stack at top of sram1. 48k */ +#include "arch/stm32l4xxx/peripherals/isrs.inc" +}; +#undef IRQ_RESERVED +#undef IRQ + +/* Encodes the provided number as a series of flashes on the on-board + * LED. The flashes follow as such: + * + * Before the bits of the code are flashed, a rapid succession of 20 flashes + * followed by a pause will occur indicating that the next 8 flashes indicate + * the bits of the provided code. + * + * Eoch of the next eight flashes indicate either a 1 or 0 depending on the + * length of flash. The first flash is the least-significant bit, the next the + * second least, the third third least, etc. + * + * - A quick flash followed by a long pause indicates a 0 bit. + * - A "long" flash followed by a equally long pause indicates a 1 bit. + */ +void unhandled_isr(uint8_t number) +{ + int ec; + gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; + gpio_reserved_pin_t pin3 = reserve_gpio_pin(GPIO_PIN_PB3, &opts, &ec); + + for (;;) { + for (int i = 0; i < 20; ++ i) { + set_gpio_pin_high(pin3); + delay(1000000); + set_gpio_pin_low(pin3); + delay(1000000); + } + delay(50000000); + + int n = number; + for (int i = 0; i < 8; ++ i) { + if (n & 1) { + // LSB is a 1 + set_gpio_pin_high(pin3); + delay(15000000); + set_gpio_pin_low(pin3); + delay(15000000); + } else { + // LSB is a 0 + set_gpio_pin_high(pin3); + delay(1000000); + set_gpio_pin_low(pin3); + delay(29000000); + } + + n >>= 1; + } + } +} + +void enable_interrupts(interrupt_set_t* interrupts) +{ + for (int i = 0; i < sizeof(NVIC.ise_r) / sizeof(uint32_t); ++ i) + NVIC.ise_r[i] = interrupts->irqs[i]; +} + +void disable_interrupts(interrupt_set_t* interrupts) +{ + for (int i = 0; i < sizeof(NVIC.ise_r) / sizeof(uint32_t); ++ i) + NVIC.ice_r[i] = interrupts->irqs[i]; +} diff --git a/src/arch/stm32l4xxx/peripherals/usart.c b/src/arch/stm32l4xxx/peripherals/usart.c new file mode 100644 index 0000000..7309b48 --- /dev/null +++ b/src/arch/stm32l4xxx/peripherals/usart.c @@ -0,0 +1,152 @@ +#include "arch/stm32l4xxx/peripherals/usart.h" +#include "kern/delay.h" +#include "kern/lib.h" +#include + +void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) +{ + rcc->ccip_r = (rcc->ccip_r & (~0x03)) | usart_clk_src; +} + +void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src) +{ + rcc->ccip_r = (rcc->ccip_r & ~(0x03 << 2)) | (usart_clk_src << 2); +} + +void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable) +{ + if (enable) { + rcc->apb1en1_r |= BIT(17); + } else { + rcc->apb1en1_r &= ~BIT(17); + } +} + +void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable) +{ + if (enable) { + rcc->apb2en_r |= BIT(14); + } else { + rcc->apb2en_r &= ~BIT(14); + } +} + +void usart_set_parity(__IO usart_t* usart, usart_parity_t parity) +{ + uint32_t c_r1 = usart->c_r1; + c_r1 &= ~(0x3 << 9); + c_r1 |= parity; + usart->c_r1 = c_r1; +} + +void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled) +{ + if (!enabled) { + regset(usart->c_r1, usart_ue, 0); + } else { + /* Set the rx enabled. */ + regset(usart->c_r1, usart_re, !!(enabled & USART_ENABLE_RX)); + regset(usart->c_r1, usart_te, !!(enabled & USART_ENABLE_TX)); + regset(usart->c_r1, usart_ue, 1); + } +} + +void usart_transmit_byte_sync(__IO usart_t* usart, uint8_t byte) +{ + usart->td_r = byte; + /* Per the manual, when bit 7 of the IS register is set, then the usart + * data has been sent to the shift register. + * + * This bit is cleared by writing to the TD register. */ + while (!(usart->is_r & BIT(7))) + ; +} + +void usart_transmit_bytes_sync(__IO usart_t* usart, const uint8_t* bytes, uint32_t n) +{ + while (n --) { + usart_transmit_byte_sync(usart, *(bytes ++)); + } +} + +void usart_transmit_str_sync(__IO usart_t* usart, const char* str) +{ + while (*str) { + if (*str == '\n') { + usart_transmit_byte_sync(usart, '\r'); + } + usart_transmit_byte_sync(usart, *(str ++)); + } +} + +void usart_enable_dma(__IO usart_t* usart, usart_enable_t enabled) +{ + switch(enabled) { + case USART_ENABLE_DISABLED: + regset(usart->c_r3, usart_dmar, 0); + regset(usart->c_r3, usart_dmat, 0); + break; + + case USART_ENABLE_TX: + regset(usart->c_r3, usart_dmat, 1); + break; + + case USART_ENABLE_RX: + regset(usart->c_r3, usart_dmar, 1); + break; + }; +} + +void usart_vprintf(__IO usart_t* usart, const char* fmt, va_list l) +{ + union { + void* ptr; + char* str; + int i; + } b; + char buf[128]; + + while (*fmt != 0) { + if (*fmt == '%') { + switch (*(++fmt)) { + case 0: + goto end; + case '%': + usart_transmit_byte_sync(usart, '%'); + break; + case 'p': + b.ptr = va_arg(l, void*); + hexify(ptr2reg(b.ptr), buf); + usart_transmit_str_sync(usart, "0x"); + usart_transmit_str_sync(usart, buf); + break; + case 'd': + case 'i': + b.i = va_arg(l, int); + decimalify(b.i, buf); + usart_transmit_str_sync(usart, buf); + break; + case 's': + b.str = va_arg(l, char*); + usart_transmit_str_sync(usart, b.str); + } + ++ fmt; + } else { + if (*fmt == '\n') { + usart_transmit_byte_sync(usart, '\r'); + } + usart_transmit_byte_sync(usart, *(fmt ++)); + } + } + +end: + va_end(l); +} + +void usart_printf(__IO usart_t* usart, const char* fmt, ...) +{ + va_list l; + va_start(l, fmt); + + usart_vprintf(usart, fmt, l); +} diff --git a/src/kern/delay.c b/src/kern/delay.c new file mode 100644 index 0000000..28ef710 --- /dev/null +++ b/src/kern/delay.c @@ -0,0 +1,9 @@ +#include "kern/delay.h" + +void delay(uint32_t delay) +{ + while (delay--) { + /* needed to keep the compiler from optimizing away the loop. */ + asm volatile(""); + } +} diff --git a/src/kern/dma/dma_manager.c b/src/kern/dma/dma_manager.c new file mode 100644 index 0000000..00e9f3d --- /dev/null +++ b/src/kern/dma/dma_manager.c @@ -0,0 +1,311 @@ +#include "kern/dma/dma_manager.h" +#include "arch/stm32l4xxx/peripherals/dma.h" +#include "arch/stm32l4xxx/peripherals/usart.h" +#include "arch/stm32l4xxx/peripherals/rcc.h" + + +/* Bitmask of DMA2 channels in use. */ +static uint8_t dma_inuse[2]; + +static inline dma_t* get_dma(int dma) +{ + if (dma) { + return &DMA2; + } else { + return &DMA1; + } +} + +static dma_t* get_raw_dma(dma_channel_t chan) +{ + return get_dma(chan.dma); +} + +static dma_channel_config_t* get_raw_channel_config(dma_channel_t chan) +{ + dma_t* dma = get_raw_dma(chan); + return &dma->channel_config[chan.chan]; +} + +static uint32_t get_periph_location(dma_peripheral_t operipheral) +{ +#define CASE(p, n) case p: return ptr2reg(n); + switch (operipheral) { + CASE(DMA1_PERIPH_USART1_RX, &USART1.rd_r) + CASE(DMA1_PERIPH_USART1_TX, &USART1.td_r) + CASE(DMA1_PERIPH_USART2_RX, &USART2.rd_r) + CASE(DMA1_PERIPH_USART2_TX, &USART2.td_r) + + default: + return 0; + }; +#undef CASE +} + +static dma_channel_t allocate_dma_channel( + dma_peripheral_t operipheral, int* modesel) +{ + dma_peripheral_t peripheral = operipheral & 0xff; + int dmasel = peripheral >= DMA2_DMA1_SWITCH__; + if (dmasel) { + peripheral -= DMA2_DMA1_SWITCH__; + } + int chan = peripheral % DMA_N_CHANNELS; + + *modesel = peripheral / 7; + return (dma_channel_t) { + .dma = dmasel, + .chan = chan + }; +} + +/* + * Atomically reserves the DMA channel so other calls + * cannot erroneously reserve the same DMA channel. + * + * Returns 0 if this function was unable to reserve + * the channel. + */ +static int try_reserve_dma_channel( + dma_channel_t chan) +{ + int in_use = __sync_fetch_and_or( + &dma_inuse[chan.dma], 1 << chan.chan); + + return !(in_use & (1 << chan.chan)); +} + +void release_dma_channel(dma_channel_t chan) +{ + dma_channel_config_t* config = get_raw_channel_config(chan); + regset(config->cc_r, dma_cc_en, 0); /* Disable the register. */ + dma_inuse[chan.dma] &= ~(1 << chan.chan); /* Release the DMA. */ + + if (!dma_inuse[chan.dma]) { + /* Power-down the DMA if not in use. */ + if (chan.dma) { + regset(RCC.ahb1en_r, rcc_dma2en, 0); + } else { + regset(RCC.ahb1en_r, rcc_dma1en, 0); + } + } +} + +void configure_dma_channel( + dma_channel_t chan, + dma_peripheral_t operipheral, + dma_opts_t* opts, + dma_dir_t dir, + int selmode, + bool mem2mem, + int* error_out) +{ + if (chan.dma) { + regset(RCC.ahb1en_r, rcc_dma2en, 1); + } else { + regset(RCC.ahb1en_r, rcc_dma1en, 1); + } + + dma_t* dma = get_raw_dma(chan); + regset(dma->csel_r, 0xF << (4 * chan.chan), selmode); + dma_channel_config_t* config = + &dma->channel_config[chan.chan]; + + uint32_t reg = 0; + + regset(reg, dma_cc_dir, dir); + regset(reg, dma_cc_tcie, opts->transfer_complete_interrupt_enable); + regset(reg, dma_cc_htie, opts->half_transfer_interrupt_enable); + regset(reg, dma_cc_teie, opts->transfer_error_interrupt_enable); + regset(reg, dma_cc_circ, opts->circular_mode); + regset(reg, dma_cc_pinc, opts->peripheral_increment); + regset(reg, dma_cc_minc, opts->memory_increment); + regset(reg, dma_cc_psize, opts->peripheral_block_size); + regset(reg, dma_cc_msize, opts->memory_block_size); + regset(reg, dma_cc_pl, opts->priority); + regset(reg, dma_cc_mem2mem, mem2mem); + + config->cc_r = reg; + config->cpa_r = get_periph_location(operipheral); + + *error_out = 0; +} + +dma_mem2mem_channel_t select_dma_channel_mem2mem( + int channel, + dma_opts_t* opts, + int* error_out) +{ + +#define WRAP(c) ((dma_mem2mem_channel_t) { .c_ = c }) + // TODO this should probably be in a critical section. + dma_channel_t chan; + if (channel == -1) { + chan.dma = 1; + if ((dma_inuse[chan.dma] & 0x7F) == 0x7F) { + chan.dma = 0; + } + + if ((dma_inuse[chan.dma] & 0x7F) == 0x7F) { + *error_out = DMA_ERROR_CHANNEL_IN_USE; + return WRAP(DMA_CHAN_ERROR); + } + + uint8_t t = ~(dma_inuse[chan.dma] << 1); + chan.chan = 6 - (__builtin_clz(t) - 24); + } else { + if (channel < 7) { + chan.dma = 0; + chan.chan = channel; + } else { + chan.dma = 0; + chan.chan = channel - 7; + } + } + + if (!try_reserve_dma_channel(chan)) { + *error_out = DMA_ERROR_CHANNEL_IN_USE; + return WRAP(DMA_CHAN_ERROR); + } + + int ec = 0; + configure_dma_channel( + chan, + -1 /* No peripheral */, + opts, + READ_FROM_PERIPHERAL, + /* selmode = */ 0x8, + /* mem2mem = */ true, + &ec); + + if (ec) { + *error_out = ec; + return WRAP(DMA_CHAN_ERROR); + } + + *error_out = 0; + return WRAP(chan); +#undef WRAP +} + +dma_mem2p_channel_t select_dma_channel_mem2p( + dma_peripheral_t peripheral, + dma_opts_t* opts_in, + int* error_out) +{ +#define WRAP(c) ((dma_mem2p_channel_t) { .c_ = c }) + *error_out = 0; + + int modesel; + dma_channel_t ret = + allocate_dma_channel(peripheral, &modesel); + + if (!try_reserve_dma_channel(ret)) { + *error_out = DMA_ERROR_CHANNEL_IN_USE; + return WRAP(DMA_CHAN_ERROR); + } + + configure_dma_channel( + ret, + peripheral, + opts_in, + READ_FROM_MEMORY, + modesel, + /* mem2mem = */ false, + error_out); + + if (*error_out) { + return WRAP(DMA_CHAN_ERROR); + } + + *error_out = 0; + return WRAP(ret); +#undef WRAP +} + +dma_p2mem_channel_t select_dma_channel_p2mem( + dma_peripheral_t peripheral, + dma_opts_t* opts_in, + int* error_out) +{ +#define WRAP(c) ((dma_p2mem_channel_t) { .c_ = c }) + *error_out = 0; + + int modesel; + dma_channel_t ret = + allocate_dma_channel(peripheral, &modesel); + + if (!try_reserve_dma_channel(ret)) { + *error_out = DMA_ERROR_CHANNEL_IN_USE; + return WRAP(DMA_CHAN_ERROR); + } + + configure_dma_channel( + ret, + peripheral, + opts_in, + READ_FROM_PERIPHERAL, + modesel, + /* mem2mem = */ false, + error_out); + + if (*error_out) { + return WRAP(DMA_CHAN_ERROR); + } + + *error_out = 0; + return WRAP(ret); +#undef WRAP +} + + +void dma_mem2p_initiate_transfer( + dma_mem2p_channel_t chan, const void* from_loc, uint16_t nblocks) +{ + dma_channel_config_t* config = get_raw_channel_config(chan.c_); + config->cma_r = ptr2reg(from_loc); + config->cndt_r = nblocks; + + regset(config->cc_r, dma_cc_en, 1); +} + +void dma_mem2mem_initiate_transfer( + dma_mem2mem_channel_t chan, + void* to_loc, + const void* from_loc, + uint16_t nblocks) +{ + dma_channel_config_t* config = get_raw_channel_config(chan.c_); + config->cma_r = ptr2reg(to_loc); + config->cpa_r = ptr2reg(from_loc); + config->cndt_r = nblocks; + + regset(config->cc_r, dma_cc_en, 1); +} + +void dma_p2mem_initiate_transfer( + dma_p2mem_channel_t chan, void* to_loc, uint16_t nblocks) +{ + dma_channel_config_t* config = get_raw_channel_config(chan.c_); + + config->cma_r = ptr2reg(to_loc); + config->cndt_r = nblocks; + + regset(config->cc_r, dma_cc_en, 1); +} + +interrupt_t dma_channel_get_interrupt(dma_channel_t chan) +{ + if (chan.dma == 0) { + return IRQ_DMA1_CHANNEL1_IRQ + chan.chan; + } else { + switch (chan.chan) { + case 5: + return IRQ_DMA1_CHANNEL6_IRQ; + case 6: + return IRQ_DMA1_CHANNEL7_IRQ; + default: + return IRQ_DMA2_CHANNEL1_IRQ + chan.chan; + } + } +} diff --git a/src/kern/gpio/gpio_manager.c b/src/kern/gpio/gpio_manager.c new file mode 100644 index 0000000..82dd0ba --- /dev/null +++ b/src/kern/gpio/gpio_manager.c @@ -0,0 +1,402 @@ +#include "kern/gpio/gpio_manager.h" + +#include "arch/stm32l4xxx/peripherals/irq.h" +#include "arch/stm32l4xxx/peripherals/rcc.h" + +/* A list of whether the pins are in use or not as a bitmask. */ +uint32_t pins_inuse[N_GPIO_PINS / 32 + (N_GPIO_PINS % 32 != 0)]; + +struct gpio_afn_and_pin { + int8_t afn_number; + gpio_pin_t gpio_pin; +}; + +/* + * Returns which (pin, afn) pairs provide the given alternate function. + * The out array needs to have 5 positions. + * + * This function will use afn_number = -1 as the terminal. + * + * Note that EVENTOUT is a special case because all pins have an event out + * at afn=15 and should be assumed by other logic and thus is not handled + * by this function. + */ +static void get_ports_and_pins_for_alternate_function( + gpio_alternate_function_t afn, struct gpio_afn_and_pin* out) +{ + switch (afn) { +#define AFN1(fn, ...) \ + static_assert(false, "Unable to parse afn_table at " #fn); +#define AFN3(fn, ...) \ + static_assert(false, "Unable to parse afn_table at " #fn); +#define AFN5(fn, ...) \ + static_assert(false, "Unable to parse afn_table at " #fn); +#define AFN7(fn, ...) \ + static_assert(false, "Unable to parse afn_table at " #fn); + +#define AFN2(fn, afn, pin) \ + out[0].afn_number = afn; \ + out[0].gpio_pin = GPIO_PIN_ ## pin + +#define AFN4(fn, afn0, pin0, afn1, pin1) \ + AFN2(fn, afn0, pin0); \ + out[1].afn_number = afn1; \ + out[1].gpio_pin = GPIO_PIN_ ## pin1 + +#define AFN6(fn, afn0, pin0, afn1, pin1, afn2, pin2) \ + AFN4(fn, afn0, pin0, afn1, pin1); \ + out[2].afn_number = afn2; \ + out[2].gpio_pin = GPIO_PIN_ ## pin2 + +#define AFN8(fn, afn0, pin0, afn1, pin1, afn2, pin2, afn3, pin3) \ + AFN6(fn, afn0, pin0, afn1, pin1, afn2, pin2); \ + out[2].afn_number = afn3; \ + out[2].gpio_pin = GPIO_PIN_ ## pin3 + +#define GET_MACRO(_1, _2, _3, _4, _5, _6, _7, _8, NAME, ...) NAME +#define GET_N(_1, _2, _3, _4, _5, _6, _7, _8, NAME, ...) NAME +#define AFN(fn, ...) \ + case GPIO_ALTERNATE_FUNCTION_ ## fn: \ + GET_MACRO(__VA_ARGS__, AFN8, AFN7, AFN6, AFN5, AFN4, AFN3, AFN2, AFN1)\ + (fn, __VA_ARGS__); \ + out[GET_N(__VA_ARGS__, 4, 4, 3, 3, 2, 2, 1, 1)] = \ + (struct gpio_afn_and_pin){-1, -1}; \ + break; + +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/afn_table.inc" + case GPIO_ALTERNATE_FUNCTION_EVENTOUT: + return; + } +} + +static inline int offset_for_gpio_pin(gpio_pin_t pin) +{ + switch (pin) { +#define PORT(p, pn) \ + case GPIO_PIN_P ## p ## pn: return pn; +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" +#undef PORT + case N_GPIO_PINS: return -1; + } + + /* Should be unreachable. */ + return -1; +} + +inline bool gpio_pin_in_use(gpio_pin_t pin) +{ + return !!(pins_inuse[pin / 32] & (1 << (pin % 32))); +} + +#define A(...) +#define B(...) +#define C(...) +#define D(...) +#define E(...) +#define F(...) +#define G(...) +#define H(...) +#define I(...) +#define SELECT_MACRO(PORT) PORT +#define PORT(port, pin) \ + SELECT_MACRO(port)(GPIO_PIN_P ## port ## pin, pin) +static int gc_port_a() +{ + return 0 +#undef A +#define A(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef A +#define A(...) +} + +static int gc_port_b() +{ + return 0 +#undef B +#define B(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef B +#define B(...) +} + +static int gc_port_c() +{ + return 0 +#undef C +#define C(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef C +#define C(...) +} + +static int gc_port_d() +{ + return 0 +#undef D +#define D(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef D +#define D(...) +} + +static int gc_port_e() +{ + return 0 +#undef E +#define E(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef E +#define E(...) +} + +static int gc_port_f() +{ + return 0 +#undef F +#define F(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef F +#define F(...) +} + +static int gc_port_g() +{ + return 0 +#undef G +#define G(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef G +#define G(...) +} + +static int gc_port_h() +{ + return 0 +#undef H +#define H(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef H +#define H(...) +} + +static int gc_port_i() +{ + return 0 +#undef I +#define I(abspin, relpin) \ + | (gpio_pin_in_use(abspin) << (relpin)) +#include "arch/stm32l4xxx/peripherals/tables/stm32l432xx/gpio/port_table.inc" + ; +#undef I +#define I(...) +} + + +static inline bool gpio_pin_try_reserve(gpio_pin_t pin) +{ + int in_use = __sync_fetch_and_or( + &pins_inuse[pin / 32], 1 << (pin % 32)); + return !(in_use & (1 << (pin % 32))); +} + +inline static gpio_port_config_t* get_gpio_port_config(gpio_port_t port) +{ + switch(port) { + case GPIO_PORT_A: return (gpio_port_config_t*) GPIOA_BASE; + case GPIO_PORT_B: return (gpio_port_config_t*) GPIOB_BASE; + case GPIO_PORT_C: return (gpio_port_config_t*) GPIOC_BASE; + case GPIO_PORT_H: return (gpio_port_config_t*) GPIOH_BASE; + default: return NULL; + } +} + +inline static gpio_port_config_t* get_gpio_port_config_for_pin(gpio_pin_t pin) +{ + gpio_port_t port = get_port_for_pin(pin); + return get_gpio_port_config(port); +} + +gpio_reserved_pin_t reserve_gpio_pin( + gpio_pin_t pin, gpio_pin_opts_t* opts, int* error_out) +{ + *error_out = 0; + if (!gpio_pin_try_reserve(pin)) { + *error_out = GPIO_ERROR_IN_USE; + return (gpio_reserved_pin_t) { .v_ = -1 }; + } + + gpio_port_t port = get_port_for_pin(pin); + regset(RCC.ahb2en_r, rcc_gpioen(port), 1); + + gpio_port_config_t* port_config = get_gpio_port_config(port); + + + int off = offset_for_gpio_pin(pin); + + regset(port_config->mode_r, gpio_mode_n(off), opts->mode); + regset(port_config->pupd_r, gpio_pupd_n(off), opts->pull_dir); + + switch(opts->mode) { + case GPIO_MODE_INPUT: + break; + + case GPIO_MODE_OUTPUT: + regset(port_config->ospeed_r, gpio_ospeed_n(off), opts->output_opts.speed); + regset(port_config->otype_r, gpio_otype_n(off), opts->output_opts.type); + break; + + case GPIO_MODE_ALTERNATE: + if (off < 8) { + regset( + port_config->af_rl, + gpio_afsel_n(off), + opts->alternate_opts.function); + } else { + regset( + port_config->af_rh, + gpio_afsel_n(off - 8), + opts->alternate_opts.function); + } + break; + + case GPIO_MODE_ANALOG: + regset(port_config->asc_r, gpio_asc_n(off), 1); + break; + } + + return (gpio_reserved_pin_t) { .v_ = pin }; +} + +gpio_reserved_pin_t gpio_enable_alternate_function( + gpio_alternate_function_t fn, + gpio_pin_t hint, + int* error_out) +{ + int i = 0; + gpio_pin_opts_t opts; + struct gpio_afn_and_pin afn_and_pin[5]; + + if (gpio_pin_out_of_range(hint) && hint != -1) { + *error_out = GPIO_ERROR_INVALID_PIN; + return (gpio_reserved_pin_t) { .v_ = -1 }; + } + + opts.mode = GPIO_MODE_ALTERNATE; + + if (fn == GPIO_ALTERNATE_FUNCTION_EVENTOUT) { + afn_and_pin[i].afn_number = GPIO_ALTERNATE_FUNCTION_EVENTOUT; + if (hint == -1) { + hint = GPIO_PIN_PA0; + } + afn_and_pin[i].gpio_pin = hint; + } else { + get_ports_and_pins_for_alternate_function(fn, afn_and_pin); + + if (hint == -1) { + hint = afn_and_pin[0].gpio_pin; + } + + for(i = 0; + i < 5 + && afn_and_pin[i].gpio_pin != hint + && afn_and_pin[i].gpio_pin != -1; + ++ i); + + if (afn_and_pin[i].gpio_pin == -1 || i == 5) { + *error_out = GPIO_ERROR_INVALID_PIN_FOR_ALTERNATE_FUNCTION; + return (gpio_reserved_pin_t) { .v_ = -1 }; + } + } + + opts.alternate_opts.function = afn_and_pin[i].afn_number; + return reserve_gpio_pin(afn_and_pin[i].gpio_pin, &opts, error_out); +} + +void release_gpio_pin(gpio_reserved_pin_t rpin) +{ + gpio_pin_t pin = rpin.v_; + // TODO this should be a critical section. + gpio_port_t port = get_port_for_pin(pin); + pins_inuse[pin / 32] &= ~(1 << (pin % 32)); + + int used; + switch(port) { + case GPIO_PORT_A: + used = gc_port_a(); + break; + case GPIO_PORT_B: + used = gc_port_b(); + break; + case GPIO_PORT_C: + used = gc_port_c(); + break; + case GPIO_PORT_D: + used = gc_port_d(); + break; + case GPIO_PORT_E: + used = gc_port_e(); + break; + case GPIO_PORT_F: + used = gc_port_f(); + break; + case GPIO_PORT_G: + used = gc_port_g(); + break; + case GPIO_PORT_H: + used = gc_port_h(); + break; + case GPIO_PORT_I: + used = gc_port_i(); + break; + + case N_GPIO_PORTS: + used = 1; + break; + } + + if (!used) { + regset(RCC.ahb2en_r, rcc_gpioen(port), 0); + } +} + +inline void get_gpio_pin_port_off( + gpio_pin_t pin, gpio_port_config_t** out_cfg, int* out_off) +{ + *out_cfg = get_gpio_port_config_for_pin(pin); + *out_off = offset_for_gpio_pin(pin); +} + +void set_gpio_pin_high(gpio_reserved_pin_t pin) +{ + int off; + gpio_port_config_t* portcfg; + get_gpio_pin_port_off(pin.v_, &portcfg, &off); + + regset(portcfg->od_r, (1 << off), 1); +} + +void set_gpio_pin_low(gpio_reserved_pin_t pin) +{ + int off; + gpio_port_config_t* portcfg; + get_gpio_pin_port_off(pin.v_, &portcfg, &off); + + regset(portcfg->od_r, (1 << off), 0); +} diff --git a/src/kern/gpio/sysled.c b/src/kern/gpio/sysled.c new file mode 100644 index 0000000..a728da3 --- /dev/null +++ b/src/kern/gpio/sysled.c @@ -0,0 +1,14 @@ +#include "kern/gpio/sysled.h" + +#define SYSLED GPIO_PIN_PB3 + +gpio_reserved_pin_t get_sysled() +{ + if (gpio_pin_in_use(SYSLED)) { + return (gpio_reserved_pin_t) { .v_ = SYSLED }; + } + + int ec; + gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; + return reserve_gpio_pin(SYSLED, &opts, &ec); +} diff --git a/src/kern/init.c b/src/kern/init.c new file mode 100644 index 0000000..2531ca9 --- /dev/null +++ b/src/kern/init.c @@ -0,0 +1,82 @@ +#include "kern/init.h" + +#include "arch.h" +#include "arch/stm32l4xxx/peripherals/system.h" +#include "arch/stm32l4xxx/peripherals/clock.h" + +#include "kern/log.h" + +/* Forward-declare the main function. This is implemented in main.c. */ +int main(); + +/* These are defined in the linker script. */ + +#ifdef ARCH_STM32L4 +extern uint32_t INIT_DATA_VALUES; +extern uint32_t DATA_SEGMENT_START; +extern uint32_t DATA_SEGMENT_STOP; +extern uint32_t BSS_START; +extern uint32_t BSS_END; + +extern void(*INIT_ROUTINES_FLASH_START)(); +extern void(*INIT_ROUTINES_FLASH_STOP)(); + +init0() +{ + /* Enable a higher clock speed. This is the first thing we do + * beacuse it will boost the boot up time. */ + set_system_clock_MHz(80); +} + +init1() +{ + /* Next, we'll copy the data sections from flash to ram. */ + uint32_t* src; + uint32_t* dest; + + src = &INIT_DATA_VALUES; + dest = &DATA_SEGMENT_START; + + /* Copy the values from flash into the data segment. */ + while (dest != &DATA_SEGMENT_STOP) { + *(dest++) = *(src++); + } + + /* Everything in the BSS segment is set to zero. */ + dest = &BSS_START; + while (dest != &BSS_END) { + *(dest++) = 0; + } +} + +init3() +{ + klogf("--- System Restart ---\n"); + klogf("Setting the vector offset table to point to the start of flash.\n"); + + /* Set the vector offset table to be at the start + * of FLASH memory. */ + SCB.vto_r = 0x08000000; +} + +/* + * Runs before main. Initializes the data and bss segments by loading them + * into memory. + */ +_Noreturn void on_reset() +{ + void (**initfn)(); + for(initfn = &INIT_ROUTINES_FLASH_START; + initfn < &INIT_ROUTINES_FLASH_STOP; + ++ initfn) { + + (*initfn)(); + } + + /* Jump to main. */ + main(); + + for(;;); +} + +#endif /* ARCH_STM32L4 */ diff --git a/src/kern/lib.c b/src/kern/lib.c new file mode 100644 index 0000000..88188cc --- /dev/null +++ b/src/kern/lib.c @@ -0,0 +1,56 @@ +#include "kern/lib.h" + +#define nybble_to_hex(n) \ + ((n) < 10 ? 0x30 + (n) : ('A' + ((n) - 10))) + +void hexify(uint32_t v, char* into) +{ + into += 8; + + *(into--) = 0; + + *(into--) = nybble_to_hex(v & 0x0F); + v >>= 4; + *(into--) = nybble_to_hex(v & 0x0F); + v >>= 4; + *(into--) = nybble_to_hex(v & 0x0F); + v >>= 4; + *(into--) = nybble_to_hex(v & 0x0F); + v >>= 4; + + *(into--) = nybble_to_hex(v & 0x0F); + v >>= 4; + *(into--) = nybble_to_hex(v & 0x0F); + v >>= 4; + *(into--) = nybble_to_hex(v & 0x0F); + v >>= 4; + *into = nybble_to_hex(v & 0x0F); + v >>= 4; +} + +void decimalify(int v, char* into) +{ + int c = 0; + int i; + + if (v == 0) { + *(into ++) = '0'; + *into = 0; + return; + } else { + while (v > 0) { + *(into ++) = 0x30 + (v % 10); + v /= 10; + ++ c; + } + } + *into = 0; + + into -= c; + for (i = 0; i < c / 2; ++ i) { + char tmp = into[i]; + into[i] = into[c - i - 1]; + into[c - i - 1] = tmp; + } + +} diff --git a/src/kern/log.c b/src/kern/log.c new file mode 100644 index 0000000..a217183 --- /dev/null +++ b/src/kern/log.c @@ -0,0 +1,55 @@ +#include "arch/stm32l4xxx/peripherals/usart.h" +#include "arch/stm32l4xxx/peripherals/clock.h" + +#include "kern/log.h" +#include "kern/init.h" +#include "kern/gpio/gpio_manager.h" + +#include "kern/common.h" + +void setup_usart2(uint32_t baud_rate); + +/** This module requires an initialization routine. This is a level2 routine, + * so anything running at level3 or lower is guaranteed to have access + * to the klong. */ +init2() +{ + setup_usart2(115200); + regset(USART2.c_r1, usart_txeie, 1); + regset(USART2.c_r1, usart_rxneie, 1); + usart_set_enabled(&USART2, USART_ENABLE_TX | USART_ENABLE_RX); + + klogf("klog() enabled on USART2\n"); +} + +void klogf(const char* fmt, ...) +{ + va_list l; + va_start(l, fmt); + + usart_vprintf(&USART2, fmt, l); +} + +void setup_usart2(uint32_t baud_rate) +{ + enable_hsi(&RCC, true); + + int ec = 0; + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_USART2_TX, GPIO_PIN_PA2, &ec); + + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_USART2_RX, GPIO_PIN_PA15, &ec); + + set_usart2_clock_src(&RCC, USART_CLK_SRC_HSI16); + set_usart2_clock_enabled(&RCC, USART_CLK_SRC_HSI16); + + /* De-assert reset of USART2 */ + regset(RCC.apb1rst1_r, rcc_usart2rst, 0); + + USART2.c_r1 = 0; + USART2.c_r2 = 0; + USART2.c_r3 = 0; + + usart_set_divisor(&USART2, 16000000 / baud_rate); +} diff --git a/src/kern/main.c b/src/kern/main.c new file mode 100644 index 0000000..ebb2164 --- /dev/null +++ b/src/kern/main.c @@ -0,0 +1,29 @@ +#include "arch.h" +#include "kern/log.h" + +#include "arch/stm32l4xxx/peripherals/system.h" +#include "arch/stm32l4xxx/peripherals/clock.h" + +void on_systick() /* Overrides weak-symbol on_systick. */ +{ + klogf("Systick\n"); +} + +#ifdef ARCH_STM32L4 + +/* Main function. This gets executed from the interrupt vector defined above. */ +int main() +{ + klogf("Hello, World! Clock Mhz: %d\n", (uint32_t) get_clock_mhz()); + + /* Set the countdown to start from 10,000,0000. */ + SCB.strv_r = 10000000; + + /* Enable interrupts. */ + regset(SCB.stcs_r, scb_tickint, 1); + + /* Start the systick. */ + regset(SCB.stcs_r, scb_enable, 1); +} + +#endif diff --git a/src/kern/mem.c b/src/kern/mem.c new file mode 100644 index 0000000..5234fff --- /dev/null +++ b/src/kern/mem.c @@ -0,0 +1,280 @@ +#include "arch.h" +#include "kern/mem.h" +#include "kern/common.h" + +#ifdef ARCH_STM32L4 +/* Provide a definition for memset() when not provided for the + * microcontroller. */ +void* memset(void* dest, int c, size_t n) +{ + uint8_t c8 = (uint8_t) c; + uint8_t* dest8 = (uint8_t*) dest; + uint8_t* to = dest8 + n; + + while(dest8 < to) { + *(dest8 ++) = c8; + } + + return dest; +} + +#else + +void* memset(void* dest, int c, size_t n); + +#endif + +typedef uint16_t halloc_off_t; + +#define CANARY 0x5a + +// The sizes will count the number of WORDS allocated. +// Since there's a max size of 16k, only 12 bits will be +// needed for this. +typedef struct HALLOC_NODE { + union { + uint32_t header; + struct { + /* Is this memory block currently in use (hasn't been hfree'd) */ + uint8_t used:1; + /* Number of words allocated. Does not include the header. */ + uint16_t size:12; + /* The location of the previous block (in WORDS from offest) */ + halloc_off_t prev:12; + uint8_t canary:7; + } PACKED; + }; + + uint8_t mem[]; /* The memory to use. */ +} halloc_node_t; + +static_assert(offsetof(halloc_node_t, mem) == 4, "Offset check failed."); + +halloc_node_t* halloc_start; + +#define halloc_node_out_of_range(node) \ + ((uint8_t*) (node) == ((uint8_t*)&DATA_SEGMENT_STOP) + MAX_HEAP_SIZE) + +#define halloc_node_next(cur) \ + ((halloc_node_t*)(((uint8_t*)(cur)) + (((cur)->size + 1) * 4))) + +#define halloc_node_prev(cur) halloc_node_at_off(cur->prev) + +#define halloc_node_at_off(offset) \ + ((halloc_node_t*)(((uint8_t*) halloc_start) + (offset) * 4)) + +#define halloc_node_get_off(node) \ + (((uint32_t)(((uint8_t*)(node)) - ((uint8_t*)(halloc_start)))) / 4) + +#define get_halloc_node(mem) \ + ((halloc_node_t*)(((uint8_t*)mem) - 4)) + +#define size_for(n) \ + (((n) / 4) + ((n) % 4 != 0)) + +void* halloc(size_t size) +{ + if (!halloc_start) { + halloc_start = (halloc_node_t*) DATA_SEGMENT_STOP_ADDR; + memset(halloc_start, 0, sizeof(halloc_node_t)); + halloc_start->size = (MAX_HEAP_SIZE / 4) - 1; + halloc_start->canary = CANARY; + } + + size_t realsz = size_for(size); /* Clip the size to the nearest word. */ + halloc_off_t offset = 0; + while (offset < (MAX_HEAP_SIZE / 4)) { + halloc_node_t* cur = halloc_node_at_off(offset); + + if (!cur->used && (cur->size >= realsz)) { + cur->used = true; + size_t orig_size = cur->size; + cur->size = realsz; + + if (orig_size > realsz) { + /* This halloc node needs to split into two blocks. */ + halloc_node_t* next = halloc_node_next(cur); + next->used = 0; + next->size = orig_size - realsz - sizeof(halloc_node_t) / 4; + next->prev = offset; + next->canary = CANARY; + + halloc_node_t* nextnext = halloc_node_next(next); + if (halloc_node_get_off(nextnext) < (MAX_HEAP_SIZE / 4)) { + nextnext->prev = halloc_node_get_off(next); + } + } + + return (void*) cur->mem; + } + + offset += (sizeof(halloc_node_t) / 4) + cur->size; + } + + return NULL; +} + + +/* Joins this node with the previous and next nodes if they're free. */ +static void coalesce(halloc_node_t* cur) +{ + halloc_node_t* orig = cur; + halloc_node_t* last_freed; + halloc_node_t* next_used; + + /* Find the earliest contiguous free'd block. */ + while (!cur->used && cur != halloc_start) { + cur = halloc_node_prev(cur); + } + + if (cur == halloc_start && !cur->used) { + last_freed = cur; + } else { + last_freed = halloc_node_next(cur); + } + + /* Find the next used block. */ + cur = orig; + while (!cur->used && !halloc_node_out_of_range(cur)) { + cur = halloc_node_next(cur); + } + + next_used = cur; + + if (!halloc_node_out_of_range(next_used)) { + next_used->prev = halloc_node_get_off(last_freed); + } + + last_freed->size = ((uint8_t*) next_used - (last_freed->mem)) / 4; +} + +#ifdef FOR_TESTING +#include +#include +void panic(const char* x) +{ + fprintf(stderr, "%s\n", x); + assert(0); +} +#else +void panic(const char* x) +{ + for(;;); +} +#endif + +void hfree(void* mem) +{ + /* Like normal free(), do nothing on free'ing NULL */ + if (!mem) return; + + halloc_node_t* header = get_halloc_node(mem); + if (!header->used) { + panic("Heap double free or corruption!\n"); + return; + } + + header->used = 0; + coalesce(header); +} + +#ifdef FOR_TESTING + +#include + +void* debug_halloc_get_next_ptr(void* ptr) +{ + halloc_node_t* node = ptr - sizeof(halloc_node_t); + halloc_node_t* next = halloc_node_next(node); + + return next->mem; +} + +void* debug_halloc_get_prev_ptr(void* ptr) +{ + halloc_node_t* node = ptr - sizeof(halloc_node_t); + halloc_node_t* prev = halloc_node_prev(node); + + return prev->mem; +} + +void debug_print_blocks() +{ + printf("------ Print Blocks -------\n"); + halloc_node_t* cur = halloc_node_at_off(0); + + while (!halloc_node_out_of_range(cur)) { + printf("header (%04x) {used=%d, size=%5d, prev=%04x, canary=%02x}\n", + halloc_node_get_off(cur), cur->used, cur->size, cur->prev, cur->canary); + cur = halloc_node_next(cur); + } +} + +/* Tests that we can walk up and down the allocated blocks and that they + * are properly aligned. */ +int debug_halloc_assert_consistency(char* error, size_t len) +{ + halloc_node_t* cur = halloc_node_at_off(0); + size_t total_size = 0; + size_t loop_check = 0; + size_t n_blocks = 1; + size_t n_blocks_back = 1; + + while(1) { + if (cur->canary != CANARY) { + snprintf(error, len, "Node has corrupted canary. %02x vs expected %02x\n", + cur->canary, CANARY); + return 1; + } + + total_size += cur->size + 1; + + halloc_node_t* next = halloc_node_next(cur); + if ((uint8_t*) next == ((uint8_t*)&DATA_SEGMENT_STOP) + MAX_HEAP_SIZE) { + break; + } else if ((uint8_t*) next > (uint8_t*)DATA_SEGMENT_STOP_ADDR + MAX_HEAP_SIZE){ + snprintf( + error, len, "Next node points is out of bounds. %p vs max of %p\n", + next, + (void*)(DATA_SEGMENT_STOP_ADDR + MAX_HEAP_SIZE)); + return 1; + } + + cur = next; + ++ n_blocks; + } + + if (total_size * 4 != MAX_HEAP_SIZE) { + snprintf( + error, len, "Total recorded size is inconsistent. %lu vs %lu\n", + total_size * 4, MAX_HEAP_SIZE); + return 1; + } + + if (cur == halloc_start) { + return 0; + } + + while (loop_check < 10000) { + halloc_node_t* prev = halloc_node_prev(cur); + ++ n_blocks_back; + + if (prev == halloc_start) { + if (n_blocks != n_blocks_back) { + snprintf( + error, len, "Different number of blocks found on the way back. Found %lu on the way back vs %lu up.\n", + n_blocks_back, n_blocks); + return 1; + } + return 0; + } + + cur = prev; + ++ loop_check; + } + + snprintf(error, len, "Loop check failed.\n"); + return 1; +} + +#endif diff --git a/src/kern/stdlibrepl.c b/src/kern/stdlibrepl.c new file mode 100644 index 0000000..2d9d839 --- /dev/null +++ b/src/kern/stdlibrepl.c @@ -0,0 +1,13 @@ +/* + * Replacement for common stdlib functions that don't exist + * on the ARM bare-metal compilation environment. + */ + +#include + +size_t strlen(char* ch) +{ + size_t ret = 0; + while(*(ch ++) != 0) ++ ret; + return ret; +} diff --git a/src/kern/string.c b/src/kern/string.c new file mode 100644 index 0000000..4afa228 --- /dev/null +++ b/src/kern/string.c @@ -0,0 +1,9 @@ +#include "kern/string.h" + +void kstrcpy(char* into, const char* from) +{ + while(*from) { + *(into ++) = *(from ++); + } + *into = 0; +} diff --git a/src/kern/vector.c b/src/kern/vector.c new file mode 100644 index 0000000..e69de29 diff --git a/test_harness/Makefile b/test_harness/Makefile new file mode 100644 index 0000000..443292b --- /dev/null +++ b/test_harness/Makefile @@ -0,0 +1,9 @@ +CC=gcc +CFLAGS=-g3 -ggdb -Wall + +test_harness.a: test_harness.c test_harness.h fake_env.o + gcc -o test_harness.o -c test_harness.c $(CFLAGS) + ar r test_harness.a test_harness.o fake_env.o + +fake_env.o: fake_env.c fake_env.h + gcc -o fake_env.o -c fake_env.c $(CFLAGS) diff --git a/test_harness/fake_env.c b/test_harness/fake_env.c new file mode 100644 index 0000000..6a32c99 --- /dev/null +++ b/test_harness/fake_env.c @@ -0,0 +1,63 @@ +#include "fake_env.h" + +#include +#include + +struct fakeenv_memseg { + const char* name; + void* segment; +}; + +#define DEFINE_MEMORY_SEGMENT(seg, start_addr, end_addr) \ + static __attribute((__section__("fakeenv"))) \ + struct fakeenv_memseg fake_##seg = { \ + .name = #seg, \ + .segment = NULL, \ + }; \ + void* load_fake_##seg##__ () \ + { \ + if (fake_##seg .segment == NULL) { \ + fake_##seg .segment = malloc((end_addr) - (start_addr)); \ + assert(fake_##seg .segment != NULL); \ + } \ + return fake_##seg.segment; \ + } + +extern struct fakeenv_memseg __start_fakeenv; +extern struct fakeenv_memseg __stop_fakeenv; + +void wipeout_fake_env() +{ + for (struct fakeenv_memseg* iter = &__start_fakeenv; + iter < &__stop_fakeenv; + ++ iter) { + free(iter->segment); + iter->segment = NULL; + } +} + +/* Reset and clock control. */ +DEFINE_MEMORY_SEGMENT(rcc, 0x40021000, 0x400210A0) + +/* Peripheral buses */ +DEFINE_MEMORY_SEGMENT(apb1, 0x40000000, 0x40010000) +DEFINE_MEMORY_SEGMENT(apb2, 0x40010000, 0x40020000) +DEFINE_MEMORY_SEGMENT(ahb1, 0x40020000, 0x40024400) +DEFINE_MEMORY_SEGMENT(ahb2, 0x48000000, 0x50060C00) + +/* System Control Block */ +DEFINE_MEMORY_SEGMENT(scb, 0xE000E008, 0xE000EF04) + +/* Nested Vector Interrupt Controller (NVIC) */ +/* Note that this memory space acutally overlaps with the SCB, but + * they are functionally distinct entitites and such are modeled as + * separate structures in memeory. */ +DEFINE_MEMORY_SEGMENT(nvic, 0xE000E004, 0xE000E4F0) + +/* SRAM */ +DEFINE_MEMORY_SEGMENT(sram1, 0x20000000, 0x2000C000) +DEFINE_MEMORY_SEGMENT(sram2, 0x2000C000, 0x20018000) + +/* Serial Peripheral Interface */ +DEFINE_MEMORY_SEGMENT(spi1, 0x40013000, 0x400133FF) +DEFINE_MEMORY_SEGMENT(spi3, 0x40003C00, 0x40003FFF) diff --git a/test_harness/fake_env.h b/test_harness/fake_env.h new file mode 100644 index 0000000..34056f4 --- /dev/null +++ b/test_harness/fake_env.h @@ -0,0 +1,20 @@ +#ifndef FAKE_ENV_H_ +#define FAKE_ENV_H_ + +/* Functions which wil lazily load fake chunks of memory + * corresponding to the*/ +void* load_fake_ahb1__(); +void* load_fake_ahb2__(); +void* load_fake_apb1__(); +void* load_fake_apb2__(); +void* load_fake_sram1__(); +void* load_fake_sram2__(); +void* load_fake_scb__(); +void* load_fake_nvic__(); +void* load_fake_rcc__(); +void* load_fake_spi1__(); +void* load_fake_spi3__(); + +void wipeout_fake_env(); + +#endif /* FAKE_ENV_H_ */ diff --git a/test_harness/test_harness.c b/test_harness/test_harness.c new file mode 100644 index 0000000..bf9249c --- /dev/null +++ b/test_harness/test_harness.c @@ -0,0 +1,181 @@ +#include "test_harness.h" +#include "fake_env.h" + +#include +#include +#include +#include +#include +#include +#include + + +static jmp_buf jmpbuf; + +volatile test_t dummy + __attribute((__section__("tests"))) + __attribute((__used__)) = { + "dummy", + "dummy", + NULL +}; + +extern unsigned char __data_start; +extern unsigned char _end; +extern test_t __start_tests; +extern test_t __stop_tests; + +test_t* iter = &__start_tests; + +static int execute_test(test_t* test); + +void test_printll(size_t sz, long long v1, long long v2) +{ + fprintf(stderr, "%lld == %lld\n", v1, v2); +} +void test_printul(size_t sz, unsigned long v1, unsigned long v2) +{ + fprintf(stderr, "%lu == %lu\n", v1, v2); +} +void test_printd(size_t sz, int v1, int v2) +{ + fprintf(stderr, "%d == %d\n", v1, v2); +} +void test_printl(size_t sz, long v1, long v2) +{ + fprintf(stderr, "%lu == %lu\n", v1, v2); +} +void test_printui(size_t sz, unsigned int v1, unsigned int v2) +{ + fprintf(stderr, "%u == %u\n", v1, v2); +} +void test_prints(size_t sz, short v1, short v2) +{ + fprintf(stderr, "%hu == %hu\n", v1, v2); +} +void test_printus(size_t sz, unsigned short v1, unsigned short v2) +{ + fprintf(stderr, "%hu == %hu\n", v1, v2); +} +void test_printc(size_t sz, char v1, char v2) +{ + fprintf(stderr, "'%c' == '%c'\n", v1, v2); +} +void test_printf(size_t sz, double v1, double v2) +{ + fprintf(stderr, "%f == %f\n", v1, v2); +} +void test_printp(size_t sz, void* v1, void* v2) +{ + fprintf(stderr, "%p == %p\n", v1, v2); +} +void test_printuc( + size_t sz, unsigned char v1, unsigned char v2) +{ + fprintf(stderr, "%02x == %02x\n", (int) v1, (int) v2); +} + +static int do_fork = 1; +static size_t saved_data_size; +static unsigned char* saved_data = NULL; + +int main(int argc, char** argv) { + /* Save all initialized data. */ + saved_data_size = &_end - &__data_start; + saved_data = malloc(saved_data_size); + memcpy(saved_data, &__data_start, saved_data_size); + + + if (argc > 1 && strcmp(argv[1], "--nofork") == 0) { + do_fork = 0; + } + + for( ; iter < &__stop_tests; ++ iter) { + if (iter->fn_ptr != NULL) { + execute_test(iter); + } + } +} + +void test_harness_abort(int ec) +{ + longjmp(jmpbuf, ec); + assert("Long jump failed.\n"); +} + +/* + * When nofork is true, this function will be called after each + * test to try and make each test hermetic. + * + * It does this by reseting the data segment to what it was when + * the program was first initialized. + * + * Of course, without forking, there's no way to guarantee hermetic + * testing in C. In fact a simple segementation fault will break + * the hermetic testing, but this does a pretty good job of at least + * reseting the environment so tests don't directly depend on eachother. + */ +static void nofork_reset() +{ + wipeout_fake_env(); + + /* Reset the data segment to what it was before. */ + memcpy(&__data_start, saved_data, saved_data_size); +} + +static int execute_test(test_t* test) +{ + char fullname[512]; + int status; + int ec = 0; + pid_t pid; + + snprintf( + fullname, sizeof(fullname), "%s::%s", iter->test_suite, iter->test_name); + + if (!do_fork) { + if ((ec = setjmp(jmpbuf)) == 0) { + test->fn_ptr(); + printf(GREEN "[PASS]" RESET " %s\n", fullname); + nofork_reset(); + return 0; + } else { + printf(RED "[FAIL] (%d)" RESET " %s\n", ec, fullname); + nofork_reset(); + return ec; + } + } + + if (!(pid = fork())) { + // child + + if ((ec = setjmp(jmpbuf))) { + exit(ec); + } else { + test->fn_ptr(); + exit(0); + } + } else { + if (waitpid(pid, &status, 0) == -1) { + fprintf(stderr, "waitpid() failed\n"); + return 1; + } + + if (WIFEXITED(status)) { + switch ((ec = WEXITSTATUS(status))) { + case 0: + printf(GREEN "[PASS]" RESET " %s\n", fullname); + return 0; + default: + printf(RED "[FAIL] (%d)" RESET " %s\n", ec, fullname); + return ec; + } + } else if (WIFSIGNALED(status)) { + int ec = WTERMSIG(status); + printf("%s " RED "[FAIL] signaled %d" RESET "\n", fullname, ec); + return ec; + } + + return ec; + } +} diff --git a/test_harness/test_harness.h b/test_harness/test_harness.h new file mode 100644 index 0000000..698e2da --- /dev/null +++ b/test_harness/test_harness.h @@ -0,0 +1,101 @@ +#ifndef TEST_HARNESS_H_ +#define TEST_HARNESS_H_ + +#include +#include + +#define YELLOW "\x1b[00;33m" +#define GREEN "\x1b[01;32m" +#define RED "\x1b[01;31m" +#define RESET "\x1b[0m" + +typedef struct { + const char* test_suite; + const char* test_name; + int (*fn_ptr)(); + void* alignment; +} test_t; + +#define GENPR(fmt, v1, v2) \ + fprintf(stderr, fmt "\n", v1, v2) + +void test_printll(size_t sz, long long v1, long long v2); +void test_printul(size_t sz, unsigned long v1, unsigned long v2); +void test_printd(size_t sz, int v1, int v2); +void test_printl(size_t sz, long v1, long v2); +void test_printui(size_t sz, unsigned int v1, unsigned int v2); +void test_prints(size_t sz, short v1, short v2); +void test_printus(size_t sz, unsigned short v1, unsigned short v2); +void test_printc(size_t sz, char v1, char v2); +void test_printf(size_t sz, double v1, double v2); +void test_printp(size_t sz, void* v1, void* v2); +void test_printuc(size_t sz, unsigned char v1, unsigned char v2); + +#define FORMAT_STRING(v1, v2) \ + _Generic((v1), \ + long long: test_printll, \ + unsigned long: test_printul, \ + int: test_printd, \ + long: test_printl, \ + unsigned int: test_printui, \ + short: test_prints, \ + unsigned short: test_printus, \ + char: test_printc, \ + unsigned char: test_printuc, \ + double: test_printf, \ + default: test_printp)(sizeof(v1), v1, v2) \ + +#define TRY_PRINT_TYPE(v1, v2, type, fmt) \ + else if (__builtin_types_compatible_p(typeof (v1), type)) { \ + fprintf(stderr, fmt " == " fmt "\n", v1, v2); \ + } + +#define TYPE_STR(t) #t + +#define ASSERT_TRUE(x) \ + do { \ + if (!(x)) { \ + fprintf(stderr, RED "ASSERT_TRUE FAILED!\n" RESET); \ + fprintf(stderr, " - " YELLOW "In expression ASSERT_TRUE(" #x ")\n"); \ + fprintf(stderr, RESET " - " YELLOW "At " __FILE__ ":%d\n" RESET, __LINE__); \ + test_harness_abort(1); \ + } \ + } while (0) + +#define ASSERT_EQ(x, y) \ + do { \ + if ((x) != (y)) { \ + fprintf(stderr, RED "ASSERT_EQ FAILED! " RESET "Not true that "); \ + FORMAT_STRING((x), (y)); \ + fprintf(stderr, " - " YELLOW "In expression ASSERT_EQ(" #x ", " #y ")\n"); \ + fprintf(stderr, RESET " - " YELLOW "At " __FILE__ ":%d\n" RESET, __LINE__); \ + test_harness_abort(1); \ + } \ + } while (0) + +#define ASSERT_EQ_STR(x, y) \ + do { \ + if (strcmp(x, y)) { \ + fprintf(stderr, \ + RED "ASSSERT_EQ_STR FAILED! " RESET "Not true that \"%s\" equals \"%s\"", \ + x, y); \ + fprintf(stderr, " - " YELLOW "In expression ASSERT_EQ_STR(" #x ", " #y ")\n"); \ + fprintf(stderr, RESET " - " YELLOW "At " __FILE__":%d\n" RESET, __LINE__); \ + test_harness_abort(1); \ + } \ + } while (0) + + +#define TEST(test_suite, test_name) \ + int test_suite ## _ ## test_name ## _fn (void); \ + volatile test_t test_suite ## _ ## test_name ## _testing_struct__ \ + __attribute((__section__("tests"))) __attribute((__used__)) = \ + {#test_suite, #test_name, test_suite ## _ ## test_name ## _fn}; \ + int test_suite ## _ ## test_name ## _fn (void) + +void test_harness_abort(int ec); + + +void wipeout_fake_env(); + +#endif diff --git a/tests/metatest.c b/tests/metatest.c new file mode 100644 index 0000000..1024156 --- /dev/null +++ b/tests/metatest.c @@ -0,0 +1,22 @@ +#include "test_harness.h" + +/* Tests the test harness itself. */ + +static int my_variable; +static int my_initialized_variable = 5; + +TEST(meta, clobbers_variables) +{ + my_variable = 6; + my_initialized_variable = 5; + + return 0; +} + +TEST(meta, variables_reset) +{ + ASSERT_EQ(my_variable, 0); + ASSERT_EQ(my_initialized_variable, 5); + + return 0; +} diff --git a/tests/test_dma.c b/tests/test_dma.c new file mode 100644 index 0000000..50cdb5b --- /dev/null +++ b/tests/test_dma.c @@ -0,0 +1,189 @@ +#include "test_harness.h" +#include "arch/stm32l4xxx/peripherals/dma.h" +#include "arch/stm32l4xxx/peripherals/rcc.h" +#include "arch/stm32l4xxx/peripherals/usart.h" +#include "kern/dma/dma_manager.h" + +#include +#include +#include + +TEST(dma, smoke) +{ + dma_t* dma = &DMA1; + memset(dma, 0, sizeof(dma_t)); + + regset(dma->is_r, dma_tcif1, 1); + ASSERT_EQ(dma->is_r, 2); + + regset(dma->is_r, dma_htif7, 1); + ASSERT_EQ(dma->is_r, 67108866); + return 0; +} + +TEST(dma, cc_regset) +{ + dma_t* dma = &DMA1; + memset(dma, 0, sizeof(dma_t)); + + dma_channel_config_t* channel_config = &dma->channel_config[2]; + regset(channel_config->cc_r, dma_cc_msize, DMA_SIZE_32_BITS); + + ASSERT_EQ(channel_config->cc_r, 1 << 11); + return 0; +} + +TEST(dma, correct_align) +{ + dma_t dma; + + // Assert the DMA registers are aligned with what the spec says. + ASSERT_EQ((long)(&dma.csel_r) - (long)(&dma), 0xA8); + + return 0; +} + +TEST(dma, regset_pl) +{ + uint32_t reg = 0; + + regset(reg, dma_cc_pl, DMA_PRIORITY_LEVEL_MEDIUM); + + ASSERT_EQ(reg, (1 << 12)); + + ASSERT_EQ( + regget(reg, dma_cc_pl), + DMA_PRIORITY_LEVEL_MEDIUM); + return 0; +} + +TEST(dma_peri, select_peripheral) +{ + dma_opts_t opts = DEFAULT_DMA_OPTS; + int ec; + + dma_mem2p_channel_t chan = + select_dma_channel_mem2p( + DMA1_PERIPH_USART2_TX, + &opts, + &ec); + + ASSERT_EQ(DMA1.channel_config[6].cpa_r, ptr2reg(&USART2.td_r)); + + ASSERT_EQ( + regget(DMA1.channel_config[6].cc_r, dma_cc_dir), + READ_FROM_MEMORY); + + ASSERT_EQ( + regget(DMA1.channel_config[6].cc_r, dma_cc_minc), + 1); + + ASSERT_EQ( + regget(DMA1.channel_config[6].cc_r, dma_cc_pl), + DMA_PRIORITY_LEVEL_MEDIUM); + + ASSERT_EQ(regget(DMA1.csel_r, dma_c7s), 0x2); + + ASSERT_EQ(regget(RCC.ahb1en_r, rcc_dma1en), 1); + + release_dma_channel(chan.c_); + + ASSERT_EQ(regget(RCC.ahb1en_r, rcc_dma1en), 0); + return 0; +} + +TEST(dma_peri, unable_to_realloc) +{ + dma_opts_t opts = DEFAULT_DMA_OPTS; + + int ec = 0; + + dma_mem2p_channel_t chan = + select_dma_channel_mem2p( + DMA1_PERIPH_USART2_TX, + &opts, + &ec); + + ASSERT_EQ(ec, 0); + + select_dma_channel_p2mem( + DMA1_PERIPH_USART2_TX, + &opts, + &ec); + + ASSERT_EQ(ec, DMA_ERROR_CHANNEL_IN_USE); + + release_dma_channel(chan.c_); + + chan = select_dma_channel_mem2p( + DMA1_PERIPH_USART2_TX, + &opts, + &ec); + + ASSERT_EQ(ec, 0); + + release_dma_channel(chan.c_); + return 0; +} + +TEST(dma_peri, select_mem2mem) +{ + int ec = 0; + dma_opts_t opts = DEFAULT_DMA_OPTS; + dma_mem2mem_channel_t chan = + select_dma_channel_mem2mem(-1, &opts, &ec); + + ASSERT_EQ(ec, 0); + + ASSERT_EQ(chan.c_.dma, 1); + ASSERT_EQ(chan.c_.chan, 6); + + dma_mem2mem_channel_t chan2 = + select_dma_channel_mem2mem(-1, &opts, &ec); + + ASSERT_EQ(ec, 0); + + ASSERT_EQ(chan2.c_.dma, 1); + ASSERT_EQ(chan2.c_.chan, 5); + + release_dma_channel(chan.c_); + + dma_mem2mem_channel_t chan3 = + select_dma_channel_mem2mem(-1, &opts, &ec); + + ASSERT_EQ(chan3.c_.dma, 1); + ASSERT_EQ(chan3.c_.chan, 6); + + release_dma_channel(chan2.c_); + release_dma_channel(chan3.c_); + return 0; +} + +TEST(dma_peri, select_mem2mem_2) +{ + dma_opts_t opts = DEFAULT_DMA_OPTS; + dma_mem2mem_channel_t chans[14]; + int ec; + + for (int i = 0; i < 14; ++ i) { + chans[i] = select_dma_channel_mem2mem( + -1, &opts, &ec); + + ASSERT_EQ(ec, 0); + } + + select_dma_channel_mem2mem(-1, &opts, &ec); + ASSERT_EQ(ec, DMA_ERROR_CHANNEL_IN_USE); + + for (int i = 0; i < 14; ++ i) { + if (i < 7) { + ASSERT_EQ(chans[i].c_.chan, 6 - i); + ASSERT_EQ(chans[i].c_.dma, 1); + } else { + ASSERT_EQ(chans[i].c_.chan, 6 - (i - 7)); + ASSERT_EQ(chans[i].c_.dma, 0); + } + release_dma_channel(chans[i].c_); + } + return 0; +} diff --git a/tests/test_gpio.c b/tests/test_gpio.c new file mode 100644 index 0000000..bcb953c --- /dev/null +++ b/tests/test_gpio.c @@ -0,0 +1,194 @@ +#include "test_harness.h" + +#include "arch/stm32l4xxx/peripherals/rcc.h" +#include "kern/gpio/gpio_manager.h" + +TEST(gpio_manager, smell) +{ + gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; + int ec = 5; + gpio_reserved_pin_t some_pin = reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); + ASSERT_EQ(ec, 0); + ASSERT_TRUE(gpio_pin_in_use(GPIO_PIN_PA15)); + + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); + release_gpio_pin(some_pin); + + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); + return 0; +} + +TEST(gpio_manager, multiplereserve) +{ + int ec; + gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; + reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); + ASSERT_TRUE(ec == 0); + + reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); + ASSERT_EQ(ec, GPIO_ERROR_IN_USE); + + return 0; +} + +TEST(gpio_manager, alternate) +{ + int ec; + + /* Pretending to start the USART. */ + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_USART2_TX, GPIO_PIN_PA2, &ec); + + ASSERT_EQ(ec, 0); + + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_USART2_RX, GPIO_PIN_PA15, &ec); + + ASSERT_EQ(ec, 0); + + gpio_port_config_t* gpioa = (gpio_port_config_t*) GPIOA_BASE; + + ASSERT_EQ(regget(gpioa->mode_r, gpio_mode_n(15)), GPIO_MODE_ALTERNATE); + ASSERT_EQ(regget(gpioa->mode_r, gpio_mode_n(2)), GPIO_MODE_ALTERNATE); + + ASSERT_EQ(regget(gpioa->af_rl, gpio_afsel_n(2)), 7); + ASSERT_EQ(regget(gpioa->af_rh, gpio_afsel_n(7)), 3); + + return 0; +} + +TEST(gpio_manager, bad_alternate) +{ + int ec; + + /* Pretending to start the USART. */ + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_USART2_RX, GPIO_PIN_PA2, &ec); + + ASSERT_EQ(ec, GPIO_ERROR_INVALID_PIN_FOR_ALTERNATE_FUNCTION); + + return 0; +} + +TEST(gpio_manager, bad_pin) +{ + int ec; + + /* Pretending to start the USART. */ + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_USART2_RX, 99, &ec); + + ASSERT_EQ(ec, GPIO_ERROR_INVALID_PIN); + + return 0; +} + +TEST(gpio_manager, alternate_then_reserve_fail) +{ + int ec; + + /* Pretending to start the USART. */ + gpio_enable_alternate_function( + GPIO_ALTERNATE_FUNCTION_USART2_TX, GPIO_PIN_PA2, &ec); + + ASSERT_EQ(ec, 0); + + gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; + reserve_gpio_pin(GPIO_PIN_PA2, &opts, &ec); + + ASSERT_EQ(ec, GPIO_ERROR_IN_USE); + + return 0; +} + +TEST(gpio_manager, get_gpio_pin_port_off) +{ + + gpio_port_config_t* cfg; + int off; + get_gpio_pin_port_off(GPIO_PIN_PA5, &cfg, &off); + + ASSERT_EQ(cfg, (void*)(GPIOA_BASE)); + ASSERT_EQ(off, 5); + + return 0; +} + +TEST(gpio_manager, sets_gpio_settings) +{ + gpio_pin_opts_t opts; + int ec; + + opts.mode = GPIO_MODE_OUTPUT; + opts.pull_dir = GPIO_PULL_DIR_NONE; + opts.output_opts.speed = GPIO_OUTPUT_SPEED_VERY_HIGH; + opts.output_opts.type = GPIO_OUTPUT_TYPE_PUSH_PULL; + + reserve_gpio_pin(GPIO_PIN_PA2, &opts, &ec); + ASSERT_EQ(ec, 0); + + gpio_port_config_t* gpioa = (gpio_port_config_t*) GPIOA_BASE; + + ASSERT_EQ(regget(gpioa->mode_r, gpio_mode_n(2)), GPIO_MODE_OUTPUT); + ASSERT_EQ(regget(gpioa->pupd_r, gpio_pupd_n(2)), GPIO_PULL_DIR_NONE); + ASSERT_EQ(regget(gpioa->ospeed_r, gpio_ospeed_n(2)), GPIO_OUTPUT_SPEED_VERY_HIGH); + ASSERT_EQ(regget(gpioa->otype_r, gpio_otype_n(2)), GPIO_OUTPUT_TYPE_PUSH_PULL); + + return 0; +} + +TEST(gpio_manager, gc) +{ + int ec; + gpio_pin_opts_t opts = DEFAULT_GPIO_OPTS_OUTPUT; + + gpio_reserved_pin_t p1 = reserve_gpio_pin(GPIO_PIN_PA0, &opts, &ec); + ASSERT_EQ(ec, 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); + + gpio_reserved_pin_t p2 = reserve_gpio_pin(GPIO_PIN_PA1, &opts, &ec); + ASSERT_EQ(ec, 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); + + gpio_reserved_pin_t p3 = reserve_gpio_pin(GPIO_PIN_PA15, &opts, &ec); + ASSERT_EQ(ec, 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); + + gpio_reserved_pin_t p4 = reserve_gpio_pin(GPIO_PIN_PB3, &opts, &ec); + ASSERT_EQ(ec, 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + gpio_reserved_pin_t p5 = reserve_gpio_pin(GPIO_PIN_PB1, &opts, &ec); + ASSERT_EQ(ec, 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + gpio_reserved_pin_t p6 = reserve_gpio_pin(GPIO_PIN_PB0, &opts, &ec); + ASSERT_EQ(ec, 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + release_gpio_pin(p1); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + release_gpio_pin(p2); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 1); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + release_gpio_pin(p3); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + release_gpio_pin(p4); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + release_gpio_pin(p5); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 1); + + release_gpio_pin(p6); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_A)), 0); + ASSERT_EQ(regget(RCC.ahb2en_r, rcc_gpioen(GPIO_PORT_B)), 0); + + return 0; +} diff --git a/tests/test_irq.c b/tests/test_irq.c new file mode 100644 index 0000000..3c4ee9c --- /dev/null +++ b/tests/test_irq.c @@ -0,0 +1,43 @@ +#include "test_harness.h" + +#include "arch/stm32l4xxx/peripherals/irq.h" +#include "arch/stm32l4xxx/peripherals/nvic.h" + +TEST(irq, nvic) +{ + interrupt_set_t is = { 0 }; + + interrupt_set_add(&is, IRQ_USART2); + interrupt_set_add(&is, IRQ_USART3); + + enable_interrupts(&is); + + ASSERT_EQ(is.irqs[1], 0xC0); + ASSERT_EQ(NVIC.ise_r[1], 0xC0); + + return 0; +} + +TEST(irq, nvic_edgecase) +{ + interrupt_set_t is = { 0 }; + interrupt_set_add(&is, IRQ_WWDG_IRQ); + interrupt_set_add(&is, IRQ_I2C1_ER); + + enable_interrupts(&is); + + ASSERT_EQ(is.irqs[0], 1); + ASSERT_EQ(NVIC.ise_r[0], 1); + ASSERT_EQ(is.irqs[1], 1); + ASSERT_EQ(NVIC.ise_r[1], 1); + + return 0; +} + +TEST(irq, enable_single_interrupt) +{ + enable_interrupt(IRQ_USART2); + ASSERT_EQ(NVIC.ise_r[1], 0x40); + + return 0; +} diff --git a/tests/test_lib.c b/tests/test_lib.c new file mode 100644 index 0000000..33076c2 --- /dev/null +++ b/tests/test_lib.c @@ -0,0 +1,21 @@ +#include "test_harness.h" +#include "kern/lib.h" + +TEST(lib, hexify) +{ + char buf[10]; + + hexify(0xaaaaaaaa, buf); + ASSERT_EQ_STR(buf, "AAAAAAAA"); + + hexify(0xdddddddd, buf); + ASSERT_EQ_STR(buf, "DDDDDDDD"); + + hexify(0x02468ace, buf); + ASSERT_EQ_STR(buf, "02468ACE"); + + hexify(0xdeadbeef, buf); + ASSERT_EQ_STR(buf, "DEADBEEF"); + + return 0; +} diff --git a/tests/test_memory.c b/tests/test_memory.c new file mode 100644 index 0000000..04e9289 --- /dev/null +++ b/tests/test_memory.c @@ -0,0 +1,378 @@ +#ifndef FOR_TESTING +#define FOR_TESTING +#endif + +#include + +#include "arch.h" +#include "test_harness.c" +#include "kern/common.h" +#include "kern/mem.h" + +struct TEST_STRUCT { + uint32_t array[3]; +}; + +struct TEST_STRUCT2 { + uint32_t array[10]; +}; + +/* Copy of the node structure. */ +typedef struct HALLOC_NODE { + union { + uint32_t header; + struct { + /* Is this memory block currently in use (hasn't been hfree'd) */ + bool used:1; + /* Number of words allocated. Does not include the header. */ + uint16_t size:12; + /* The location of the previous block (in WORDS from offest) */ + uint16_t prev:12; + uint8_t canary:7; + } PACKED; + }; + + uint8_t mem[]; /* The memory to use. */ +} halloc_node_t; + +extern halloc_node_t* halloc_start; + +static void wipeout_halloc() +{ + memset(halloc_start, 0, 1024); + halloc_start = NULL; +} + + +static struct TEST_STRUCT* new_test_struct() +{ + struct TEST_STRUCT* ret = halloc(sizeof(struct TEST_STRUCT)); + + ret->array[0] = 1; + ret->array[1] = 2; + ret->array[2] = 3; + + return ret; +} + +static struct TEST_STRUCT2* new_test_struct2() +{ + struct TEST_STRUCT2* ret = halloc(sizeof(struct TEST_STRUCT2)); + + for (int i = 0; i < 10; ++ i) { + ret->array[i] = i; + } + + return ret; +} + +#define ASSERT_CHAIN(t1, t2) \ + ASSERT_EQ(V(t1) + sizeof(*t1) + 4, V(t2)) + +TEST(memory, halloc) +{ + +#define V(x) ((void*)(x)) + struct TEST_STRUCT* test1 = new_test_struct(); + struct TEST_STRUCT2* test2 = new_test_struct2(); + struct TEST_STRUCT* test3 = new_test_struct(); + struct TEST_STRUCT2* test4 = new_test_struct2(); + struct TEST_STRUCT2* test5 = new_test_struct2(); + + ASSERT_TRUE(V(test1) != V(test2)); + ASSERT_TRUE(V(test2) != V(test3)); + ASSERT_TRUE(V(test3) != V(test1)); + ASSERT_TRUE(V(test2) != V(test5)); + ASSERT_TRUE(V(test4) != V(test5)); + + ASSERT_CHAIN(test1, test2); + ASSERT_CHAIN(test2, test3); + ASSERT_CHAIN(test3, test4); + ASSERT_CHAIN(test4, test5); + + + char buf[1024]; + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf( + stderr, + "Consistency check failed. (%s:%d)\n", + __FILE__, + __LINE__); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + + wipeout_halloc(); + + return 0; +} + +struct UNEVEN_STRUCT { + uint8_t arr[5]; +}; + +struct UNEVEN_STRUCT* new_uneven_struct() +{ + struct UNEVEN_STRUCT* ret = halloc(sizeof(struct UNEVEN_STRUCT)); + + ret->arr[0] = 1; + ret->arr[1] = 2; + ret->arr[2] = 3; + ret->arr[3] = 4; + ret->arr[4] = 5; + + return ret; +} + +#define size_for(n) \ + (((n) / 4) + ((n) % 4 != 0)) + +TEST(memory, uneven_halloc) +{ + if (halloc_start) { + wipeout_halloc(); + } + + struct UNEVEN_STRUCT* test1 = new_uneven_struct(); + struct UNEVEN_STRUCT* test2 = new_uneven_struct(); + + ASSERT_EQ(V(test1) + 12, test2); + + wipeout_halloc(); + + return 0; +} + +TEST(memory, halloc_free) +{ + if (halloc_start) { + wipeout_halloc(); + } + + struct TEST_STRUCT* test1 = new_test_struct(); + struct TEST_STRUCT2* test2 = new_test_struct2(); + struct TEST_STRUCT* test3 = new_test_struct(); + struct TEST_STRUCT2* test4 = new_test_struct2(); + struct TEST_STRUCT2* test5 = new_test_struct2(); + + hfree(test2); + hfree(test4); + hfree(test3); + hfree(test1); + hfree(test5); + + ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); + + test1 = new_test_struct(); + test2 = new_test_struct2(); + test3 = new_test_struct(); + test4 = new_test_struct2(); + test5 = new_test_struct2(); + + hfree(test1); + hfree(test3); + hfree(test2); + hfree(test4); + hfree(test5); + + ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); + + test1 = new_test_struct(); + test2 = new_test_struct2(); + test3 = new_test_struct(); + test4 = new_test_struct2(); + test5 = new_test_struct2(); + + hfree(test4); + hfree(test3); + hfree(test1); + hfree(test2); + hfree(test5); + + ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); + + wipeout_halloc(); + + return 0; +} + +TEST(memory, halloc_free_alloc2) +{ + if (halloc_start) { + wipeout_halloc(); + } + + struct TEST_STRUCT2* test1 = new_test_struct2(); + struct TEST_STRUCT2* test2 = new_test_struct2(); + + hfree(test1); + + struct TEST_STRUCT* test3 = new_test_struct(); + struct TEST_STRUCT* test4 = new_test_struct(); + + ASSERT_EQ(debug_halloc_get_next_ptr(test3), V(test4)); + + ASSERT_EQ( + // There should be a free block after test4. + debug_halloc_get_next_ptr(debug_halloc_get_next_ptr(test4)), + V(test2)); + + ASSERT_EQ( + // There should be a free block after test4. + debug_halloc_get_prev_ptr(debug_halloc_get_prev_ptr(test2)), + V(test4)); + + char buf[1024]; + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf(stderr, "Consistency check failed.\n"); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + + return 0; +} + +TEST(memory, relink_backref_after_free) +{ + if (halloc_start) { + wipeout_halloc(); + } + + struct TEST_STRUCT* test2 = new_test_struct(); + struct TEST_STRUCT* test3 = new_test_struct(); + + hfree(test2); + hfree(test3); + + char buf[1024]; + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf(stderr, "Consistency check failed.\n"); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + + return 0; +} + +TEST(memory, consistency_stress) +{ +#define NRUNS 500 + if (halloc_start) { + wipeout_halloc(); + } + + int i; + void* allocd[NRUNS] = { 0 }; + char buf[1024]; + + for (i = 0; i < NRUNS; ++ i) { + size_t nalloc = rand() % 20; + allocd[i] = halloc(nalloc); + + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf( + stderr, + "Consistency check failed. (At index=%d, %s:%d)\n", + i, + __FILE__, + __LINE__); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + + ASSERT_TRUE(allocd[i]); + + memset(allocd[i], 0xFF, nalloc); + size_t idx = rand() % NRUNS; + + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf( + stderr, + "Consistency check failed. (At index=%d, %s:%d)\n", + i, + __FILE__, + __LINE__); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + + hfree(allocd[idx]); + allocd[idx] = NULL; + + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf( + stderr, + "Consistency check failed. (At index=%d, %s:%d)\n", + i, + __FILE__, + __LINE__); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + + idx = rand() % NRUNS; + hfree(allocd[idx]); + allocd[idx] = NULL; + + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf( + stderr, + "Consistency check failed. (At index=%d, %s:%d)\n", + i, + __FILE__, + __LINE__); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + } + + for(i = 0; i < NRUNS; ++ i) { + if (allocd[i]) { + hfree(allocd[i]); + } + + if (debug_halloc_assert_consistency(buf, 1024)) { + fprintf( + stderr, + "Consistency check failed. (At index=%d, %s:%d)\n", + i, + __FILE__, + __LINE__); + fprintf(stderr, buf); + ASSERT_TRUE(false); + } + } + ASSERT_EQ((int) halloc_start->size * 4, MAX_HEAP_SIZE - 4); + + return 0; +} + +TEST(memory, halloc_free_alloc) +{ + if (halloc_start) { + wipeout_halloc(); + } + + new_test_struct(); + struct TEST_STRUCT2* test2 = new_test_struct2(); + new_test_struct(); + struct TEST_STRUCT2* test4 = new_test_struct2(); + new_test_struct2(); + + hfree(test4); + + struct TEST_STRUCT2* test6 = new_test_struct2(); + + // test_6 should have been allocated in test_4's spot. + ASSERT_EQ(test6, test4); + + hfree(test2); + struct TEST_STRUCT* test7 = new_test_struct(); + struct TEST_STRUCT* test8 = new_test_struct(); + + // Test 2 was large enough to accomodate 3 smaller structs. + ASSERT_EQ(V(test7), V(test2)); + ASSERT_EQ(V(test8), V(test2) + sizeof(*test7) + 4); + + return 0; +} diff --git a/tests/test_spi.c b/tests/test_spi.c new file mode 100644 index 0000000..cc25d6e --- /dev/null +++ b/tests/test_spi.c @@ -0,0 +1,11 @@ +#include "test_harness.h" + +#include "arch/stm32l4xxx/peripherals/spi.h" + +TEST(spi, smoke) +{ + __IO spi_t* spi = &SPI1; + spi->s_r = 1; + + return 0; +} diff --git a/tests/test_usart.c b/tests/test_usart.c new file mode 100644 index 0000000..b19d687 --- /dev/null +++ b/tests/test_usart.c @@ -0,0 +1,22 @@ +#include "test_harness.h" +#include "arch/stm32l4xxx/peripherals/usart.h" + +#include + +TEST(usart, enable_dma) +{ + __IO usart_t* usart = &USART1; + + usart->c_r3 = 0; + + usart_enable_dma(usart, USART_ENABLE_TX); + ASSERT_EQ(usart->c_r3, 128); + + usart_enable_dma(usart, USART_ENABLE_RX); + ASSERT_EQ(usart->c_r3, 192); + + usart_enable_dma(usart, USART_ENABLE_DISABLED); + ASSERT_EQ(usart->c_r3, 0); + + return 0; +} -- cgit