From 9e349913f728e47e09852a20a7e16c405d30cd7b Mon Sep 17 00:00:00 2001 From: Josh Rahm Date: Thu, 3 Dec 2020 22:45:47 -0700 Subject: Double the SPI bandwith by writing only 8 bits to the spi data register instead of 16 (with 8 leading 0's). --- include/arch/stm32l4xxx/peripherals/spi.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'include/arch') diff --git a/include/arch/stm32l4xxx/peripherals/spi.h b/include/arch/stm32l4xxx/peripherals/spi.h index e5b44fe..478664e 100644 --- a/include/arch/stm32l4xxx/peripherals/spi.h +++ b/include/arch/stm32l4xxx/peripherals/spi.h @@ -92,7 +92,15 @@ typedef __IO struct { /* spi data register. Really only the least-significant 16 bits are used. * reading from this register reads from the Rx FIFO while writing to it * writes to the Tx FIFO. */ - __IO uint32_t d_r; + union { + /* The lower 8 its of the spi data register. */ + __IO uint8_t dl_r; + + /* The data register. */ + __IO uint16_t d_r; + }; + + __IO uint16_t unused; /* spi CRC polynomial register. */ uint32_t crcp_r; -- cgit