#ifndef DMA_H_ #define DMA_H_ /* * Header file for definining the DMA (Direct Memory Access). * * A DMA is used to perform data transfers between segments of memory * or between memory and peripherals. * * There are 2 DMA's on the chip. Each with 7 channels. */ #include "common.h" #include #include #define DMA1 (* (dma_t*) DMA1_BASE) #define DMA2 (* (dma_t*) DMA2_BASE) typedef enum { DMA_SIZE_8_BITS = 0, DMA_SIZE_16_BITS = 1, DMA_SIZE_32_BITS = 2, } dma_size_t; typedef enum { DMA_PRIORITY_LEVEL_LOW = 0, DMA_PRIORITY_LEVEL_MEDIUM = 1, DMA_PRIORITY_LEVEL_HIGH = 2, DMA_PRIORITY_LEVEL_VERY_HIGH = 3 } dma_priority_level; typedef enum { READ_FROM_PERIPHERAL = 0, READ_FROM_MEMORY = 1, } dma_dir_t; typedef struct { union { __IO uint32_t cc_r; struct { bits_t en:1; // channel enable bits_t tcie:1; // transfer complete interrupt enable bits_t htie:1; // half transfer interrupt enable bits_t teie:1; // transfer error interrupt enable bits_t dir:1; // data transfer direction bits_t circ:1; // circular mode bits_t pinc:1; // peripheral increment mode bits_t minc:1; // memory increment mode bits_t psize:2; // Peripheral size bits_t msize:2; // Memory size bits_t pl:2; // Priority level bits_t mem2mem:1; // Memory to memory mode bits_t reserved:17; } PACKED cc_bf; }; /* Number of data to transfer. */ union { __IO uint32_t cndt_r; struct { bits_t ndt:16; // Number of data to transfer. bits_t reserved:16; } cndt_bf; }; /* DMA channel peripheral address register. * Defines a memory address if mem2mem is set. */ __IO uint32_t cpa_r; /* DMA channel memory address register. * Defines another perpipheral address if peripheral-periphal mode is set. */ __IO uint32_t cma_r; __IO uint32_t reserved; } dma_channel_config_t; typedef struct { // DMA Interrupt status register. union { __IO uint32_t is_r; struct { bits_t gif1:1; // global interrupt flag for channel 1 bits_t tcif1:1; // transfer complete (TC) flag for channel 1 bits_t htif1:1; // half transfer (HT) flag for channel 1 bits_t teif1:1; // transfer error (TE) flag for channel 1 bits_t gif2:1; // global interrupt flag for channel 2 bits_t tcif2:1; // transfer complete (TC) flag for channel 2 bits_t htif2:1; // half transfer (HT) flag for channel 2 bits_t teif2:1; // transfer error (TE) flag for channel 2 bits_t gif3:1; // global interrupt flag for channel 3 bits_t tcif3:1; // transfer complete (TC) flag for channel 3 bits_t htif3:1; // half transfer (HT) flag for channel 3 bits_t teif3:1; // transfer error (TE) flag for channel 3 bits_t gif4:1; // global interrupt flag for channel 4 bits_t tcif4:1; // transfer complete (TC) flag for channel 4 bits_t htif4:1; // half transfer (HT) flag for channel 4 bits_t teif4:1; // transfer error (TE) flag for channel 4 bits_t gif5:1; // global interrupt flag for channel 5 bits_t tcif5:1; // transfer complete (TC) flag for channel 5 bits_t htif5:1; // half transfer (HT) flag for channel 5 bits_t teif5:1; // transfer error (TE) flag for channel 5 bits_t gif6:1; // global interrupt flag for channel 6 bits_t tcif6:1; // transfer complete (TC) flag for channel 6 bits_t htif6:1; // half transfer (HT) flag for channel 6 bits_t teif6:1; // transfer error (TE) flag for channel 6 bits_t gif7:1; // global interrupt flag for channel 7 bits_t tcif7:1; // transfer complete (TC) flag for channel 7 bits_t htif7:1; // half transfer (HT) flag for channel 7 bits_t teif7:1; // transfer error (TE) flag for channel 7 bits_t reserved:4; } PACKED is_bf; }; // DMA Interrupt flag clear register union { __IO uint32_t ifc_r; struct { bits_t cgif1:1; // global interrupt flag clear for channel 1 bits_t ctcif1:1; // transfer complete flag clear for channel 1 bits_t chtif1:1; // half transfer flag clear for channel 1 bits_t cteif1:1; // transfer error flag clear for channel 1 bits_t cgif2:1; // global interrupt flag clear for channel 2 bits_t ctcif2:1; // transfer complete flag clear for channel 2 bits_t chtif2:1; // half transfer flag clear for channel 2 bits_t cteif2:1; // transfer error flag clear for channel 2 bits_t cgif3:1; // global interrupt flag clear for channel 3 bits_t ctcif3:1; // transfer complete flag clear for channel 3 bits_t chtif3:1; // half transfer flag clear for channel 3 bits_t cteif3:1; // transfer error flag clear for channel 3 bits_t cgif4:1; // global interrupt flag clear for channel 4 bits_t ctcif4:1; // transfer complete flag clear for channel 4 bits_t chtif4:1; // half transfer flag clear for channel 4 bits_t cteif4:1; // transfer error flag clear for channel 4 bits_t cgif5:1; // global interrupt flag clear for channel 5 bits_t ctcif5:1; // transfer complete flag clear for channel 5 bits_t chtif5:1; // half transfer flag clear for channel 5 bits_t cteif5:1; // transfer error flag clear for channel 5 bits_t cgif6:1; // global interrupt flag clear for channel 6 bits_t ctcif6:1; // transfer complete flag clear for channel 6 bits_t chtif6:1; // half transfer flag clear for channel 6 bits_t cteif6:1; // transfer error flag clear for channel 6 bits_t cgif7:1; // global interrupt flag clear for channel 7 bits_t ctcif7:1; // transfer complete flag clear for channel 7 bits_t chtif7:1; // half transfer flag clear for channel 7 bits_t cteif7:1; // transfer error flag clear for channel 7 } PACKED ifc_bf; }; dma_channel_config_t channel_config[7]; __IO uint32_t reserved[5]; /* DMA channel selection register. */ union { __IO uint32_t csel_r; struct { bits_t c1s:4; // DMA channel 1 selection. bits_t c2s:4; // DMA channel 2 selection. bits_t c3s:4; // DMA channel 3 selection. bits_t c4s:4; // DMA channel 4 selection. bits_t c5s:4; // DMA channel 5 selection. bits_t c6s:4; // DMA channel 6 selection. bits_t c7s:4; // DMA channel 7 selection. bits_t reserved:4; } PACKED csel_bf; }; } dma_t; static_assert(offsetof(dma_t, csel_r) == 0xA8, "Offset check failed."); #endif /* DMA_H_ */