#ifndef H__RCC_
#define H__RCC_

#include "common.h"
#include <stdint.h>

#define RCC_BASE ((uint32_t)0x40021000)

typedef enum {
  SYS_CLK_SW_MSI,
  SYS_CLK_SW_HSI,
  SYS_CLK_SW_HSE,
  SYS_CLK_SW_PLL,
} sys_clk_sw_t;

typedef enum {
  PLL_SRC_NONE,
  PLL_SRC_MSI,
  PLL_SRC_HSI,
  PLL_SRC_HSE
} pll_src_t;

typedef struct {
  /* Clock control register. Offset 0x00. */
  union RCC_CR {
    __IO uint32_t r; /* 32 bit register. */

    /* Bit field for the c_r */
    struct {
      bits_t msion:1;    /* Turn on teh MSI. */
      bits_t msirdy:1;   /* Is the MSI ready? */
      bits_t msipllen:1; /* Enabled/disable the PLL part of MSI. */
      bits_t msirgsel:1; /* MSI clock range selection. */
      bits_t msirange:4; /* MSI range. */

      bits_t hsion:1;    /* Enable the HSI16 clock. */
      bits_t hsikeron:1; /* Force the HSI16 ON even in stop modes. */
      bits_t hsirdy:1;   /* Is the hsi ready? */
      bits_t hsiasfs:1;  /* HSI automatic start from STOP. */
      RESERVED(4);
      
      bits_t hseon:1;    /* Enable the HSE. */
      bits_t hserdy:1;   /* Is the HSE ready? */
      bits_t hsebyp:1;   /* Use an external HSE. */
      bits_t csson:1;    /* Clock security system enabled. */
      RESERVED(4);

      bits_t pllon:1;     /* Enable the main PLL. */
      bits_t pllrdy:1;    /* Is the PLL ready? */
      bits_t pllsai1on:1; /* Enable the SAI1 PLL. */
      bits_t pllsai1rdy:1; /* Enable the SAI1 PLL. */
      RESERVED(4);
    } PACKED;
  } __IO c;

  /* Internal clock sources calibration register (RCC_ICSCR) Offset 0x04. */
  union RCC_ICSCR {
    __IO uint32_t r; /* 32 bit register. */

    /* Bit field for icsc_r. */
    struct {
      bits_t msical:8;
      bits_t msitrim:8;
      bits_t hsical:8;
      bits_t hsitrim:5;

      RESERVED(3);
    } PACKED;
  } __IO icscr;


  /* Clock configuration register. */
  union RCC_CFGR {
    __IO uint32_t r;

    /* Bitfields for cfg_r. */
    struct {
      sys_clk_sw_t sw:2;   /* System clock switch. @see sys_clk_sw_t enum. */
      sys_clk_sw_t sws:2;  /* System clock switch status. */

      bits_t hpre:4; /* AHB prescaler. */
      bits_t ppre:3; /* APB low-speed prescaller. */

      RESERVED(1);

      bits_t stopwuck:1; /* Wakeup from Stop and CSS backup clock selection. */
      bits_t mcosel:4;   /* Microcontroller clock output. */
      bits_t mcopre:3;   /* MCO prescaller. */

      RESERVED(1);
    } PACKED __IO;
  } __IO cfg;

  /* PLL Configuration register. Offset 0x0c */
  union RCC_PLLCFGR {
    __IO uint32_t r;

    /* Bitfields for pllcfg_r */
    struct {
      pll_src_t pllsrc:2; /* PLL input source clock. */

      RESERVED(2);

      bits_t    pllm:3;   /* Divisions factor for the main PLL and audio PLL */

      RESERVED(1);

      bits_t    plln:7;   /* main PLL multiplication factor for VCO, must be
                           * on interval [8, 86] inclusive */
      RESERVED(1);

      bits_t    pllpen:1;  /* Main PLL PLLSAI1CLK output enable. */
      bits_t    pllp:1;    /* Main division factor for PLLP.
                            * 0 = 7, 1 = 17 */
      RESERVED(2);

      bits_t    pllqen:1;  /* Main PLL PLL48M1CLK output enabled. */
      bits_t    pllq:2;    /* PLLQ division factor. in 2^x. */

      RESERVED(1);

      bits_t    pllren:1;  /* PLL PLLCLK enabled. */
      bits_t    pllr:2;  ; /* main pll divion factor. 2^x. */

      bits_t    pllpdiv:5; /* PLLP division factor. 0 to be handled by PLLP. */

    } PACKED __IO;
  } __IO pllcfg;

  __IO uint32_t pllsai1cfg_r; /* PLLSAI1 configuration register. 0x10 */

  __IO uint32_t reserved_1; /* Not used. offset 0x14. */

  __IO uint32_t cie_r; /* Clock interrupt enable register. 0x18 */
  __IO uint32_t cif_r; /* Clock interrupt flag regiseter.  0x1c */
  __IO uint32_t cic_r; /* Clock interrupt clear register.  0x20 */

  __IO uint32_t reserved_2; /* Not used. offset 0x24. */

  __IO uint32_t ahb1rst_r; /* AHB Peripheral 1 reset register. 0x28 */
  __IO uint32_t ahb2rst_r; /* AHB Peripheral 2 reset register. 0x2c */
  __IO uint32_t ahb3rst_r; /* AHB Peripheral 3 reset register. 0x30 */

  __IO uint32_t reserved_3; /* Not used. offset 0x34. */

  __IO uint32_t apb1rst1_r; /* APB Peripheral reset register 1. 0x38 */
  __IO uint32_t apb1rst2_r; /* APB Peripheral reset register 2. 0x3C */
  __IO uint32_t apb2rst_r;  /* APB Peripheral reset register.   0x40 */

  __IO uint32_t reserved_4; /* Not used. offset 0x44. */

  __IO uint32_t ahb1en_r; /* AHB1 Peripheral enable register. 0x48 */
  __IO uint32_t ahb2en_r; /* AHB2 Peripheral enable register. 0x4C */
  __IO uint32_t ahb3en_r; /* AHB3 Peripheral enable register. 0x50 */

  __IO uint32_t reserved_5; /* Not used. offset 0x54. */

  __IO uint32_t apb1en1_r; /* APB1 Peripheral enable register 1. 0x58 */
  __IO uint32_t apb1en2_r; /* APB1 Peripheral enable register 2. 0x5C */
  __IO uint32_t apb2en_r;  /* APB2 Peripheral enable register.   0x60 */

  __IO uint32_t reserved_6; /* Not used. offset 0x64. */

  __IO uint32_t ahb1smen_r; /* 0x68 */
  __IO uint32_t ahb2smen_r; /* 0x6c */
  __IO uint32_t ahb3smen_r; /* 0x70 */

  __IO uint32_t reserved_7;

  __IO uint32_t apb1smen_r1; /* 0x78 */
  __IO uint32_t apb1smen_r2; /* 0x7c */
  __IO uint32_t apb2smen_r;  /* 0x80 */

  __IO uint32_t reserved_8;

  __IO uint32_t ccip_r; /* 0x88 */
} PACKED rcc_t;

#define RCC (*(__IO rcc_t*)RCC_BASE)

#endif