#include "usart.h"
#include "delay.h"

void set_usart1_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src)
{
  rcc->ccip_r = rcc->ccip_r & (~0x03) | usart_clk_src;
}

void set_usart2_clock_src(__IO rcc_t* rcc, usart_clk_src_t usart_clk_src)
{
  rcc->ccip_r = rcc->ccip_r & ~(0x03 << 2) | (usart_clk_src << 2);
}

void set_usart2_clock_enabled(__IO rcc_t* rcc, bool enable)
{
  if (enable) {
    rcc->apb1en1_r |= BIT(17);
  } else {
    rcc->apb1en1_r &= ~BIT(17);
  }
}

void set_usart1_clock_enabled(__IO rcc_t* rcc, bool enable)
{
  if (enable) {
    rcc->apb2en_r |= BIT(14);
  } else {
    rcc->apb2en_r &= ~BIT(14);
  }
}

void usart_set_parity(__IO usart_t* usart, usart_parity_t parity)
{
  usart->c1.pce = !!parity;
  usart->c1.ps  = parity & 1;
}

void usart_set_enabled(__IO usart_t* usart, usart_enable_t enabled)
{
  if (!enabled) {
    usart->c1.ue = 0;
  } else {
    /* Set the rx enabled. */
    union USART_CR1 tmp = usart->c1;

    tmp.re = !!(enabled & USART_ENABLE_RX);
    tmp.te = !!(enabled & USART_ENABLE_TX);
    tmp.ue = 1;

    usart->c1 = tmp;
  }
}

void usart_transmit_byte(__IO usart_t* usart, uint8_t byte)
{
  usart->td_r = byte;
  /* Per the manual, when bit 7 of the IS register is set, then the usart
   * data has been sent to the shift register.
   *
   * This bit is cleared by writing to the TD register. */
  while (!(usart->is_r & BIT(7)))
    ;
}

void usart_transmit_bytes(__IO usart_t* usart, const uint8_t* bytes, uint32_t n)
{
  while (n --) {
    usart_transmit_byte(usart, *(bytes ++));
  }
}

void usart_transmit_str(__IO usart_t* usart, const char* str)
{
  while (*str) {
    if (*str == '\n') {
      usart_transmit_byte(usart, '\r');
    }
    usart_transmit_byte(usart, *(str ++));
  }
}