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#include "arch.h"
#include "arch/arm/cortex-m4/mpu.h"
#include "arch/stm32l4xxx/peripherals/clock.h"
#include "arch/stm32l4xxx/peripherals/rcc.h"
#include "arch/stm32l4xxx/peripherals/spi.h"
#include "arch/stm32l4xxx/peripherals/system.h"
#include "kern/gpio/gpio_manager.h"
#include "kern/init.h"
#include "kern/log.h"
#include "kern/mem.h"
#include "kern/mpu/mpu_manager.h"
#include "kern/panic.h"
#include "kern/priv.h"
#include "user/syscall.h"
void on_hard_fault()
{
panic("Hard fault encountered!\n");
}
void on_systick() /* Overrides weak-symbol on_systick. */
{
klogf("Systick\n");
}
void configure_mpu()
{
configure_flash_region((void*)0x08000000, REGION_SIZE_256Kb, NOT_PRIVILEGED);
configure_ram_region((void*)SRAM1_BASE, REGION_SIZE_64Kb, NOT_PRIVILEGED);
configure_ram_region((void*)SRAM2_BASE, REGION_SIZE_16Kb, NOT_PRIVILEGED);
configure_peripheral_region((void*)0x40000000, REGION_SIZE_512Mb, PRIVILEGED);
mpu_set_enabled(1);
}
#ifdef ARCH_STM32L4
/* Main function. This gets executed from the interrupt vector defined above. */
int main()
{
configure_mpu();
int ec;
// gpio_enable_alternate_function(
// GPIO_ALTERNATE_FUNCTION_SPI1_MISO, GPIO_PIN_PA6, &ec);
// if (ec) {
// klogf("Unable to set pin PA6 (ec=%d)\n", ec);
// }
gpio_enable_alternate_function(
GPIO_ALTERNATE_FUNCTION_SPI1_MOSI, GPIO_PIN_PA7, &ec);
if (ec) {
klogf("Unable to set pin PA7 (ec=%d)\n", ec);
}
gpio_enable_alternate_function(
GPIO_ALTERNATE_FUNCTION_SPI1_NSS, GPIO_PIN_PA4, &ec);
if (ec) {
klogf("Unable to set pin PA4 (ec=%d)\n", ec);
}
gpio_enable_alternate_function(
GPIO_ALTERNATE_FUNCTION_SPI1_SCK, GPIO_PIN_PA5, &ec);
if (ec) {
klogf("Unable to set pin PA5 (ec=%d)\n", ec);
}
regset(RCC.apb2en_r, rcc_spi1en, 1);
uint32_t reg = 0;
regset(reg, spi_ldma_tx, 0);
regset(reg, spi_ldma_rx, 0);
regset(reg, spi_frxth, 0);
regset(reg, spi_ds, SPI_DATA_SIZE_8_BITS);
regset(reg, spi_txeie, 0);
regset(reg, spi_rxneie, 0);
regset(reg, spi_errie, 0);
regset(reg, spi_frf, 0);
regset(reg, spi_nssp, 0);
regset(reg, spi_ssoe, 0);
regset(reg, spi_txdmaen, 0);
regset(reg, spi_rxdmaen, 0);
SPI1.c_r2 = reg;
reg = 0;
regset(reg, spi_bidimode, 0);
regset(reg, spi_crcen, 0);
regset(reg, spi_crcnext, 0);
regset(reg, spi_crcl, 0);
regset(reg, spi_rxonly, 0);
regset(reg, spi_ssm, 1);
regset(reg, spi_ssi, 1);
regset(reg, spi_lsbfirst, 0);
regset(reg, spi_spe, 1);
regset(reg, spi_br, SPI_BAUD_FPCLK_DIV_256);
regset(reg, spi_mstr, 1);
regset(reg, spi_cpol, 0);
regset(reg, spi_cpha, 0);
SPI1.c_r1 = reg;
uint8_t val = 0xf0;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
SPI1.d_r = val;
klogf("4 Spi Status %p\n", SPI1.s_r);
for (;;) SPI1.d_r = val;
// for (;;) {
// klogf("Spi Status %p\n", SPI1.s_r);
// // while (!regget(SPI1.s_r, spi_txe))
// // ;
// // klogf("Write\n");
// // SPI1.d_r = val;
// }
}
#endif
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