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author | Josh Rahm <joshuarahm@gmail.com> | 2022-12-28 02:37:20 -0700 |
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committer | Josh Rahm <joshuarahm@gmail.com> | 2022-12-28 02:37:20 -0700 |
commit | c2381347678ed99571fd6899f1bb8ba8a2f8fc4c (patch) | |
tree | 21ab97b0ee77bf2f9a84235bf7249491ae87641a /collatz.v | |
parent | 40b224e0f7a565c9b1cfcc32243d2bf9af37cb39 (diff) | |
download | verilog-c2381347678ed99571fd6899f1bb8ba8a2f8fc4c.tar.gz verilog-c2381347678ed99571fd6899f1bb8ba8a2f8fc4c.tar.bz2 verilog-c2381347678ed99571fd6899f1bb8ba8a2f8fc4c.zip |
Added (very) crude Collatz conjecture module.
Diffstat (limited to 'collatz.v')
-rw-r--r-- | collatz.v | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/collatz.v b/collatz.v new file mode 100644 index 0000000..e90c1bd --- /dev/null +++ b/collatz.v @@ -0,0 +1,57 @@ +module collatz ( + input clk, + input rst, + + input wire [15:0] in_start, + input wire start_int, + + output reg [15:0] o_count, + output finish_int +); + + localparam IDLE = 0; + localparam SPINNING = 1; + localparam WAIT_TICK = 2; + + reg [1:0] state = 0; + reg [15:0] count = 0; + reg [15:0] n = 0; + + wire is_even; + + assign is_even = ~n[0]; + assign finish_int = (n == 1 && state == IDLE); + + always @(posedge start_int) begin + if (state == IDLE) begin + state <= SPINNING; + n <= in_start; + end + end + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + state <= IDLE; + count <= 0; + n <= 0; + end else if (state == IDLE) begin + n <= 0; + end else if (state == SPINNING) begin + if (n <= 1) begin + o_count = count; + state = WAIT_TICK; + // finish_int should be triggered. + end else begin + if (is_even) begin + n <= n >> 1; + end else begin + n <= n * 3 + 1; + end + count <= count + 1; + end + end else if (state == WAIT_TICK) begin + state <= IDLE; + end + end + + endmodule |