From 9acc760308079ae553f4b47694a5682da99bf2a3 Mon Sep 17 00:00:00 2001 From: Josh Rahm Date: Wed, 28 Dec 2022 13:50:47 -0700 Subject: Rearchitect into separate projects. --- apio.ini | 3 -- clock_divider.v | 25 ------------- clock_divider/apio.ini | 3 ++ clock_divider/clock_divider.v | 25 +++++++++++++ clock_divider/clock_divider_tb.v | 55 +++++++++++++++++++++++++++ clock_divider_tb.v | 55 --------------------------- collatz.v | 80 ---------------------------------------- collatz/apio.ini | 3 ++ collatz/collatz.v | 79 +++++++++++++++++++++++++++++++++++++++ collatz/collatz_tb.v | 49 ++++++++++++++++++++++++ collatz_tb.v | 48 ------------------------ 11 files changed, 214 insertions(+), 211 deletions(-) delete mode 100644 apio.ini delete mode 100644 clock_divider.v create mode 100644 clock_divider/apio.ini create mode 100644 clock_divider/clock_divider.v create mode 100644 clock_divider/clock_divider_tb.v delete mode 100644 clock_divider_tb.v delete mode 100644 collatz.v create mode 100644 collatz/apio.ini create mode 100644 collatz/collatz.v create mode 100644 collatz/collatz_tb.v delete mode 100644 collatz_tb.v diff --git a/apio.ini b/apio.ini deleted file mode 100644 index 1faba9f..0000000 --- a/apio.ini +++ /dev/null @@ -1,3 +0,0 @@ -[env] -board = icestick - diff --git a/clock_divider.v b/clock_divider.v deleted file mode 100644 index 8f46aa3..0000000 --- a/clock_divider.v +++ /dev/null @@ -1,25 +0,0 @@ -module clock_divider #( - parameter integer COUNT_WIDTH = 24, - parameter [COUNT_WIDTH:0] MAX_COUNT = 6000000 -) ( - input clk, - input rst, - - output reg div_clk -); - - reg [COUNT_WIDTH:0] count = 0; - - always @(posedge clk or posedge rst) begin - if (rst == 1'b1) begin - count <= 0; - div_clk <= 0; - end else if (count == MAX_COUNT - 1) begin - count <= 0; - div_clk <= ~div_clk; - end else begin - count <= count + 1; - end - end - -endmodule diff --git a/clock_divider/apio.ini b/clock_divider/apio.ini new file mode 100644 index 0000000..1faba9f --- /dev/null +++ b/clock_divider/apio.ini @@ -0,0 +1,3 @@ +[env] +board = icestick + diff --git a/clock_divider/clock_divider.v b/clock_divider/clock_divider.v new file mode 100644 index 0000000..8f46aa3 --- /dev/null +++ b/clock_divider/clock_divider.v @@ -0,0 +1,25 @@ +module clock_divider #( + parameter integer COUNT_WIDTH = 24, + parameter [COUNT_WIDTH:0] MAX_COUNT = 6000000 +) ( + input clk, + input rst, + + output reg div_clk +); + + reg [COUNT_WIDTH:0] count = 0; + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + count <= 0; + div_clk <= 0; + end else if (count == MAX_COUNT - 1) begin + count <= 0; + div_clk <= ~div_clk; + end else begin + count <= count + 1; + end + end + +endmodule diff --git a/clock_divider/clock_divider_tb.v b/clock_divider/clock_divider_tb.v new file mode 100644 index 0000000..7499454 --- /dev/null +++ b/clock_divider/clock_divider_tb.v @@ -0,0 +1,55 @@ +`timescale 1 ns / 10 ps + +module clock_divider_tb (); + + reg clk = 0; + reg rst = 0; + + wire out; + wire out2; + + // Simulation time: 10_000 * 1 ns = 10 μs. + localparam integer DURATION = 10_000; + + // generate clock signal : 1 / ((2 * 41.67) * 1 ns) == 11,999,040.08 MHz + always begin + // Delay for 41.667 + #41.667; + + clk = ~clk; + end + + clock_divider #( + .COUNT_WIDTH(4), + .MAX_COUNT (4) + ) utt ( + .clk(clk), + .rst(rst), + .div_clk(out) + ); + + clock_divider #( + .COUNT_WIDTH(4), + .MAX_COUNT (4) + ) utt2 ( + .clk(out), + .rst(rst), + .div_clk(out2) + ); + + initial begin + #10 rst = 1'b1; + #1 rst = 1'b0; + end + + initial begin + $dumpfile("clock_divider_tb.vcd"); + $dumpvars(0, clock_divider_tb); + + #(DURATION); + $display("Finished!"); + $finish; + end + +endmodule + diff --git a/clock_divider_tb.v b/clock_divider_tb.v deleted file mode 100644 index 7499454..0000000 --- a/clock_divider_tb.v +++ /dev/null @@ -1,55 +0,0 @@ -`timescale 1 ns / 10 ps - -module clock_divider_tb (); - - reg clk = 0; - reg rst = 0; - - wire out; - wire out2; - - // Simulation time: 10_000 * 1 ns = 10 μs. - localparam integer DURATION = 10_000; - - // generate clock signal : 1 / ((2 * 41.67) * 1 ns) == 11,999,040.08 MHz - always begin - // Delay for 41.667 - #41.667; - - clk = ~clk; - end - - clock_divider #( - .COUNT_WIDTH(4), - .MAX_COUNT (4) - ) utt ( - .clk(clk), - .rst(rst), - .div_clk(out) - ); - - clock_divider #( - .COUNT_WIDTH(4), - .MAX_COUNT (4) - ) utt2 ( - .clk(out), - .rst(rst), - .div_clk(out2) - ); - - initial begin - #10 rst = 1'b1; - #1 rst = 1'b0; - end - - initial begin - $dumpfile("clock_divider_tb.vcd"); - $dumpvars(0, clock_divider_tb); - - #(DURATION); - $display("Finished!"); - $finish; - end - -endmodule - diff --git a/collatz.v b/collatz.v deleted file mode 100644 index 35550c2..0000000 --- a/collatz.v +++ /dev/null @@ -1,80 +0,0 @@ -/** - * Collatz Conjecture module. - * - * Takes a start integer and calculates the number of steps - * required for that number to get down to 1 using the collatz - * conjecture. - */ -module collatz ( - /* Input clock and reset pin. */ - input clk, - input rst, - - /* The number to calculate. */ - input wire [15:0] in_start, - /* Pulsing the start_int pin will start the calculation. */ - input wire start_int, - - /* Output count. */ - output reg [15:0] o_count, - - /* Set to high when the module is idle and ready to start. - * While computing, this output is set to low. - * - * A positive edge of this will indicate the output is ready - * to be consumed. */ - output idle -); - - // Define some state parameters. - localparam integer IDLE = 0; - localparam integer SPINNING = 1; - - reg state = 0; // IDLE or SPINNING - reg [15:0] count = 0; // Current count - reg [15:0] n = 0; // Current value - - wire is_even = ~n[0]; // Is the current value even. - assign idle = state == IDLE; - - // When the start_int input is set to high, copy the in_start to the current - // number and set the state to SPINNING. - always @(posedge start_int) begin - if (state == IDLE) begin - state <= SPINNING; - n <= in_start; - end - end - - // Each clock cycle, determine what needs to happen. - always @(posedge clk or posedge rst) begin - // On reset, reset the state. - if (rst == 1'b1) begin - state <= IDLE; - count <= 0; - n <= 0; - - // If the state is idle, reset the count to 0. - end else if (state == IDLE) begin - n <= 0; - - // If the state is calculating, do the next step. - end else if (state == SPINNING) begin - // If n is 1, then set the output and go back to the IDLE state. - if (n <= 1) begin - o_count = count; - state = IDLE; - end else begin - // If is_even, divide by two, otherwise multiply by 3 and add 1. - if (is_even) begin - n <= n >> 1; - end else begin - n <= n * 3 + 1; - end - // Increment the count. - count <= count + 1; - end - end - end - -endmodule diff --git a/collatz/apio.ini b/collatz/apio.ini new file mode 100644 index 0000000..1faba9f --- /dev/null +++ b/collatz/apio.ini @@ -0,0 +1,3 @@ +[env] +board = icestick + diff --git a/collatz/collatz.v b/collatz/collatz.v new file mode 100644 index 0000000..e046815 --- /dev/null +++ b/collatz/collatz.v @@ -0,0 +1,79 @@ +/** + * Collatz Conjecture module. + * + * Takes a start integer and calculates the number of steps + * required for that number to get down to 1 using the collatz + * conjecture. + */ +module collatz #( + parameter integer WIDTH = 16 +) ( + /* Input clock and reset pin. */ + input clk, + input rst, + + /* The number to calculate. */ + input wire [WIDTH-1:0] in_start, + /* Pulsing the start_int pin will start the calculation. */ + input wire start_int, + + /* Output count. */ + output reg [WIDTH-1:0] o_count, + + /* Set to high when the module is idle and ready to start. + * While computing, this output is set to low. + * + * A positive edge of this will indicate the output is ready + * to be consumed. */ + output idle +); + + // Define some state parameters. + localparam integer IDLE = 0; + localparam integer SPINNING = 1; + + reg state = 0; + reg [WIDTH-1:0] count = 0; + reg [WIDTH-1:0] n = 0; + + wire is_even = ~n[0]; // Is the current value even. + assign idle = state == IDLE; + + // When the start_int input is set to high, copy the in_start to the current + // number and set the state to SPINNING. + always @(posedge start_int) begin + if (state == IDLE) begin + state <= SPINNING; + n <= in_start; + end + end + + // Each clock cycle, determine what needs to happen. + always @(posedge clk or posedge rst) begin + // On reset, reset the state. + if (rst == 1'b1) begin + count = 0; + state <= IDLE; + n <= 0; + + // If the state is idle, reset the count to 0. + end else if (state == SPINNING) begin + // If n is 1, then set the output and go back to the IDLE state. + if (n <= 1) begin + o_count = count; + n <= 0; + state = IDLE; + end else begin + // If is_even, divide by two, otherwise multiply by 3 and add 1. + if (is_even) begin + n <= n >> 1; + end else begin + n <= n * 3 + 1; + end + // Increment the count. + count <= count + 1; + end + end + end + +endmodule diff --git a/collatz/collatz_tb.v b/collatz/collatz_tb.v new file mode 100644 index 0000000..c56b13c --- /dev/null +++ b/collatz/collatz_tb.v @@ -0,0 +1,49 @@ +`timescale 1 ns / 10 ps + +module collatz_tb (); + reg clk = 0; + reg rst = 0; + + wire idle; + + localparam integer DURATION = 500_000; + + always begin + #41.667; + clk = ~clk; + end + + reg [24:0] n = 1_000_000; + reg start_int; + + wire [24:0] count_out; + + collatz #( + .WIDTH(32) + ) ctz ( + .clk(clk), + .rst(rst), + .in_start(n), + .start_int(start_int), + .o_count(count_out), + .idle(idle) + ); + + initial begin + #10 rst = 1'b1; + #1 rst = 1'b0; + end + + initial begin + $dumpfile("collatz_tb.vcd"); + $dumpvars(0, collatz_tb); + + #50 start_int = 1; + #10 start_int = 0; + + #(DURATION); + $display("Finished!"); + $finish; + end + +endmodule diff --git a/collatz_tb.v b/collatz_tb.v deleted file mode 100644 index 7419d3f..0000000 --- a/collatz_tb.v +++ /dev/null @@ -1,48 +0,0 @@ -`timescale 1 ns / 10 ps - -module collatz_tb (); - reg clk = 0; - reg rst = 0; - - wire finish; - - localparam integer DURATION = 10_000; - - always begin - #41.667; - - clk = ~ clk; - end - - reg [15:0] n = 9; - reg start_int; - - wire [15:0] count_out; - - collatz ctz ( - .clk(clk), - .rst(rst), - .in_start(n), - .start_int(start_int), - .o_count(count_out), - .finish_int(finish) - ); - - initial begin - #10 rst = 1'b1; - #1 rst = 1'b0; - end - - initial begin - $dumpfile("collatz_tb.vcd"); - $dumpvars(0, collatz_tb); - - #50 start_int = 1; - #10 start_int = 0; - - #(DURATION); - $display("Finished!"); - $finish; - end - -endmodule -- cgit