clock_divider.v


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module clock_divider #(
    parameter integer COUNT_WIDTH = 24,
    parameter [COUNT_WIDTH:0] MAX_COUNT = 6000000
) (
    input clk,
    input rst,

    output reg div_clk
);

  reg [COUNT_WIDTH:0] count = 0;

  always @(posedge clk or posedge rst) begin
    if (rst == 1'b1) begin
      count   <= 0;
      div_clk <= 0;
    end else if (count == MAX_COUNT - 1) begin
      count   <= 0;
      div_clk <= ~div_clk;
    end else begin
      count <= count + 1;
    end
  end

endmodule