clock_divider/clock_divider_tb.v


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`timescale 1 ns / 10 ps

module clock_divider_tb ();

  reg  clk = 0;
  reg  rst = 0;

  wire out;
  wire out2;

  // Simulation time: 10_000 * 1 ns = 10 μs.
  localparam integer DURATION = 10_000;

  // generate clock signal : 1 / ((2 *  41.67) * 1 ns) == 11,999,040.08 MHz
  always begin
    // Delay for 41.667
    #41.667;

    clk = ~clk;
  end

  clock_divider #(
      .COUNT_WIDTH(4),
      .MAX_COUNT  (4)
  ) utt (
      .clk(clk),
      .rst(rst),
      .div_clk(out)
  );

  clock_divider #(
      .COUNT_WIDTH(4),
      .MAX_COUNT  (4)
  ) utt2 (
      .clk(out),
      .rst(rst),
      .div_clk(out2)
  );

  initial begin
    #10 rst = 1'b1;
    #1 rst = 1'b0;
  end

  initial begin
    $dumpfile("clock_divider_tb.vcd");
    $dumpvars(0, clock_divider_tb);

    #(DURATION);
    $display("Finished!");
    $finish;
  end

endmodule