From 22c5b3e1dc4e3cf7de3f73ebbf5b59542f207f4b Mon Sep 17 00:00:00 2001 From: Josh Rahm Date: Sun, 17 Nov 2024 23:04:11 -0700 Subject: System clock is sort of working. It appears the frequency divider does not work. I've followed the data sheet, but no matter what I set the frequency divider to it appears to not work. It's possible maybe the GPIO is using an un-divided clock, but I'm not sure. Also the 32khz clock does not work I think. It might be an issue with the board. The waveform is jagged and looks awful. But I can switch from the HSE to the PLL. --- src/io.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'src/io.c') diff --git a/src/io.c b/src/io.c index 0da33d1..6233e86 100644 --- a/src/io.c +++ b/src/io.c @@ -1,10 +1,11 @@ +#include "io.h" + #include #include #include "ch573/gpio.h" #include "ch573/uart.h" - -#include "io.h" +#include "clock.h" #ifndef DEBUG_UART #define DEBUG_UART UART1 @@ -26,6 +27,7 @@ static int uart1_FILE_put(char ch, FILE* unused) while (!UART.lsr.thr_empty.get(UART1)); UART.thr.set(UART1, ch); + while (!UART.lsr.thr_empty.get(UART1)); return 1; } @@ -49,6 +51,8 @@ FILE _uart1_FILE = (FILE){ FILE* const stdout = &_uart1_FILE; +static int uart1_init_for_stdout = 0; + void init_uart1_for_stdout(void) { GPIO_PORT.dir.set(GPIO_PORT_A, DIR_OUT, gpio_usart1_tx_pin); @@ -61,4 +65,22 @@ void init_uart1_for_stdout(void) volatile uint32_t dl = (10 * 6400000 / 8 / BAUD_RATE + 5) / 10; UART.dl.set(UART1, dl); + uart1_init_for_stdout = 1; +} + +/* When the system clock changes, we need to update the UART baud rate. */ +on_system_clock_changed(uart_clock_change)(const clock_cfg_t* cfg) +{ + if (uart1_init_for_stdout) { + clock_cfg_t c; + + if (get_system_clock(&c)) { + return; + } + + uint32_t freq = get_clock_freq(&c); + + uint32_t dl = (10 * freq / 8 / BAUD_RATE + 5) / 10; + UART.dl.set(UART1, dl); + } } -- cgit