Added a whole bunch of fiddle files. Started improving boot process.

It still works.

5 files changed, 760 insertions, 0 deletions

diff --git a/fdl/ch573/clock.fdl b/fdl/ch573/clock.fdl
new file mode 100644
index 0000000..c550d76
--- /dev/null
+++ b/fdl/ch573/clock.fdl
@@ -0,0 +1,209 @@
+import "ch573/common.fdl";
+
+/** Package for the system clock registers. */
+package ch573.clock {
+  location clock_base = 0x4000_1000;
+
+  using ch573.common;
+
+  type clock_cfg_t : struct {
+    skip_to(0x08);
+
+    assert_pos(0x08);
+    /** System clock configuration register */
+    reg clk_sys_cfg(16) : struct {
+      clk_pll_div : (5);
+      reserved(1);
+      /** The system clock source. */
+      clk_sys_mod : enum(2) {
+        /** 32 Mhz external clock source. */
+        [[ c: unqualified ]]
+        HCLK_SRC_CK32M = 0b00,
+
+        /** PLL clock source.*/
+        [[ c: unqualified ]]
+        HCLK_SRC_PLL = 0b01,
+
+        /** 32kHz internal clock. */
+        [[ c: unqualified ]]
+        HCLK_SRC_CK32K = 0b11,
+        reserved = 0b10,
+      };
+      reserved(8);
+    };
+
+    assert_pos(0x0A);
+    /** High frequency clock module power control register */
+    reg hfck_pwr_ctrl(8) : struct {
+      reserved(2);
+      /** External oscillator on. */
+      clk_xt32m_pon : bit_t;
+      reserved(1);
+      /** PLL Power on */
+      clk_pll_pon : bit_t;
+      reserved(3);
+    };
+
+    skip_to(0x2C);
+    assert_pos(0x2C);
+    /** Internal 32KHz clock tune register */
+    reg(16) : struct {
+      int32k_tune : (12);
+      reserved(4);
+    };
+
+    assert_pos(0x2E);
+    /** External 32KHz clock resonance tune register */
+    reg xt32k_tune(8) : struct {
+      reserved(4);
+      xt32k_c_load : (4);
+    };
+
+    assert_pos(0x2F);
+    /** 32KHz oscillator configuration register */
+    reg ck32k_config(8) : struct {
+      clk_int32k_pon : enable_t;
+      clk_xt32k_pon : enable_t;
+      clk_osc32k_xt : enum(1) {
+         [[ c: unqualified ]]
+         INTERNAL_32K_OSC = 1,
+         [[ c: unqualified ]]
+         EXTERNAL_32K_OSC = 0,
+      };
+      reserved(4);
+      rb_32k_clk_pin : enable_t;
+    };
+
+    assert_pos(0x30);
+    /** RTC flag and control register */
+    reg rtc_flag_ctrl(8) : struct {
+      reserved(4);
+      rtc_tmr_clr : bit_t;
+      rtc_trig_clr : bit_t;
+      ro rtc_tmr_flag : bit_t;
+      ro rtc_trig_flag : bit_t;
+    };
+
+    assert_pos(0x31);
+    /** RTC mode configuration register */
+    reg rtc_mode_ctrl(8) : struct {
+     rtc_tmr_mode : enum(3) {
+       [[ c: unqualified ]]
+       TMR_MODE_0_125_S = 0,
+       [[ c: unqualified ]]
+       TMR_MODE_0_25_S = 1,
+       [[ c: unqualified ]]
+       TMR_MODE_0_5_S = 2,
+       [[ c: unqualified ]]
+       TMR_MODE_1_S = 3,
+       [[ c: unqualified ]]
+       TMR_MODE_2_S = 4,
+       [[ c: unqualified ]]
+       TMR_MODE_4_S = 5,
+       [[ c: unqualified ]]
+       TMR_MODE_8_S = 6,
+       [[ c: unqualified ]]
+       TMR_MODE_16_S = 7,
+     };
+
+     /** Ignore and compare the lowest bit of matching value in trigger mode: */
+     rtc_ignore_b0 : enum(1) {
+       [[ c: unqualified ]]
+       IGNORE_LOWEST_BIT = 1,
+       [[ c: unqualified ]]
+       COMPARE_LOWEST_BIT = 0,
+     };
+
+     /** Rtc Timing mode enabled. */
+     rtc_tmr_en : enable_t;
+
+     /** Rtc trigger mode enabled. */
+     rtc_trig_en : enable_t;
+
+     /** Write 1 to load the low word of RTC counter, and automatically cleared
+      * after loading. Load the high 16 bits of R32_RTC_TRIG to R16_RTC_CNT_2S;
+      * load the low 16 bits of R32_RTC_TRIG to R16_RTC_CNT_32K */
+     rtc_load_lo : enable_t;
+
+     /** Write 1 to load the high word of RTC counter, and automatically cleared
+      * to 0 after loading. Load R32_RTC_TRIG (actually only the low 14 bits) to
+      * R32_RTC_CNT_DAY. */
+     rtc_load_hi : enable_t;
+    };
+
+    skip_to(0x34);
+    assert_pos(0x34);
+    /** RTC trigger value register */
+    reg rtc_trig(32);
+
+    assert_pos(0x38);
+    /** RTC based 32768Hz count value register */
+    reg rtc_cnt_32k(16);
+
+    assert_pos(0x3A);
+    /** RTC count value register in the unit of 2S */
+    reg rtc_cnt_2s(16);
+
+    assert_pos(0x3C);
+    /** RTC count value register in the unit of day */
+    reg (32) : struct {
+      rtc_cnt_day : (14);
+      reserved(18);
+    };
+
+    skip_to(0x4B);
+    assert_pos(0x4B);
+    /** PLL configuration register */
+    reg pll_config(8) : struct {
+      pll_config_dat : (7);
+      reserved(1);
+    };
+
+    skip_to(0x4E);
+    assert_pos(0x4E);
+    /** External 32MHz clock resonance tune register */
+    reg xt32m_tune(8) : struct {
+      /** External 32MHz oscillator bias current */
+      xt32m_i_bias : enum (2) {
+        /** 75% of rated current */
+        [[ c: unqualified ]]
+        CURRENT_75 = 0,
+        /** 100% of rated current */
+        [[ c: unqualified ]]
+        CURRENT_RATED = 1,
+        /** 125% of rated current */
+        [[ c: unqualified ]]
+        CURRENT_125 = 2,
+        /** 150% of rated current */
+        [[ c: unqualified ]]
+        CURRENT_150 = 3,
+      };
+      reserved(2);
+      /** Select the built-in load capacitor that matches the external 32MHz
+       * crystal (which may affect wireless communication): Capacity =
+       * RB_XT32M_C_LOAD * 2 + 10pF, 000b-111b correspond to approximately
+       * 10pF-24pF respectively. Choose according to the parameters of crystal
+       * used; the common value is 111b. */
+      xt32m_c_load : (3);
+      reserved(1);
+    };
+    reserved(8);
+
+    assert_pos(0x50);
+    /** Oscillator frequency calibration count value register */
+    reg(16) : struct {
+      osc_cal_cnt : (14);
+      reserved(2);
+    };
+
+    assert_pos(0x52);
+    /** Oscillator frequency calibration control register */
+    reg osc_cal_ctrl(8) : struct {
+      osc_cnt_en : bit_t;
+      osc_cnt_halt : bit_t;
+      reserved(6);
+    };
+  };
+
+  instance clock_cfg at clock_base : clock_cfg_t;
+};
diff --git a/fdl/ch573/common.fdl b/fdl/ch573/common.fdl
new file mode 100644
index 0000000..779097c
--- /dev/null
+++ b/fdl/ch573/common.fdl
@@ -0,0 +1,17 @@
+package ch573.common {
+  bits bit_t : enum(1) {
+    [[ c: unqualified ]]
+    ON = 0b1,
+
+    [[ c: unqualified ]]
+    OFF = 0b0,
+  };
+
+  bits enable_t : enum(1) {
+    [[ c: unqualified ]]
+    ENABLED = 1,
+
+    [[ c: unqualified ]]
+    DISABLED = 0,
+  };
+};
diff --git a/fdl/ch573/gpio.fdl b/fdl/ch573/gpio.fdl
new file mode 100644
index 0000000..c54d956
--- /dev/null
+++ b/fdl/ch573/gpio.fdl
@@ -0,0 +1,219 @@
+import "ch573/common.fdl";
+
+/** Package for */
+package ch573.gpio {
+
+  location sys_base = 0x4000_1000;
+  location gpio_base = 0x4000_1018;
+
+  location gpio_port_a_base = 0x4000_10A0;
+  location gpio_port_b_base = 0x4000_10C0;
+
+  using ch573.common;
+
+  bits pd_drv_t : enum(1) {
+    [[ c: unqualified ]]
+    PD_DRV_DRIVE = 0,
+
+    [[ c: unqualified ]]
+    PD_DRV_OPEN_DRAIN = 1,
+  };
+
+  /** Gpio port type. */
+  type gpio_port_t : struct {
+    /** Port direction register. */
+    reg (32) : struct {
+       dir : enum(1) {
+         [[ c: unqualified ]]
+         DIR_OUT = 1,
+
+         [[ c: unqualified ]]
+         DIR_IN = 0,
+       } [16];
+       reserved(16);
+    };
+
+    /** Pin input register. */
+    reg pin(32);
+
+    /** Pin output register. */
+    reg (32) : struct {
+      out : bit_t[16];
+      reserved(16);
+    };
+
+    /** Data reset register. */
+    reg clr(32);
+
+    /** Pull-up resistor configuration. */
+    reg pu(32);
+
+    /** pull-down/drive configuration register. */
+    reg (32) : struct {
+      pd_drv : pd_drv_t[16];
+      reserved(16);
+    };
+  };
+
+  /** Gpio Type. */
+  type gpio_t : struct {
+    /** Function pin remapping register. */
+    reg pin_alternate(16) : struct {
+      /** 
+       * TMR0 function pin mapping selection bit:
+       *
+       *  1: TMR0_/PWM0_/CAP0_ is mapped to PB[23]
+       *  0: TMR0_/PWM0_/CAP0_ is mapped to PA[9]
+       */
+      rw pin_tmr0 : bit_t;
+
+      /**
+       * TMR1 function pin mapping selection bit:
+       *
+       *  1: TMR1_/PWM1_/CAP1_ is mapped to PB[10];
+       *  0: TMR1/PWM1/CAP1 is mapped to PA[10].
+       */
+      rw pin_tmr1 : bit_t;
+
+      /**
+       * TMR2 function pin mapping selection bit:
+       *
+       *  1: TMR2_/PWM2_/CAP2_ is mapped to PB[11];
+       *  0: TMR2/PWM2/CAP2 is mapped to PA[11].
+       */
+      rw pin_tmr2 : bit_t;
+
+      reserved(1);
+
+      /**
+       * UART0 function pin mapping selection bit:
+       *
+       *  1: RXD0_/TXD0_ is mapped to PA[15]/PA[14];
+       *  0: RXD0/TXD0 is mapped to PB[4]/PB[7].
+       */
+      rw pin_uart0 : bit_t;
+
+      /**
+       * UART1 function pin mapping selection bit:
+       *
+       *  1: RXD1_/TXD1_ is mapped to PB[12]/PB[13];
+       *  0: RXD1/TXD1 is mapped to PA[8]/PA[9].
+       */
+      rw pin_uart1 : bit_t;
+
+      reserved(2);
+
+      /**
+       * SPI0 function pin mapping selection bit:
+       *
+       *  1: SCK0_/SCS_/MOSI_/MISO_ is mapped to PB[12]/PB[13]/PB[14]/PB[15];
+       *  0: SCK0/SCS/MOSI/MISO is mapped to PA[12]/PA[13]/PA[14]/PA[15].
+       */
+      rw pin_spi0 : bit_t;
+
+      reserved(7);
+
+    };
+
+    /** Peripheral analog pin configuration register. */
+    reg pin_analog_ie(16) : struct {
+      reserved(6);
+
+      pin_usb_dp_pu : bit_t;
+
+      /**
+       * USB pin enable:
+       *
+       *   1: PB10-11 are USB communication pins;
+       *   0: PB10-11 are not used for USB communication.
+       */
+      pin_usb_ie : bit_t;
+      
+      /**
+       * ADC/TKEY 8/9 channel pin digital input disable:
+       *
+       *   1: Disable PB0/PB6 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_adc8_9_ie : bit_t;
+
+      /**
+       * ADC/TKEY 0 channel pin digital input disable:
+       *
+       *   1: Disable PA4 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_adc0_ie : bit_t;
+
+      /**
+       * ADC/TKEY 1 channel pin digital input disable:
+       *
+       *   1: Disable PA5 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_adc1_ie : bit_t;
+      
+      /**
+       * ADC/TKEY 12 channel pin digital input disable:
+       *
+       *   1: Disable the PA8 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_adc12_ie : bit_t;
+
+      /**
+       * ADC/TKEY 13 channel pin digital input disable:
+       *
+       *   1: Disable PA9 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_adc13_ie : bit_t;
+
+      /**
+       * 32KHz crystal LSE pin digital input disable:
+       *
+       *   1: Disable PA10-11 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_xt32k_ie : bit_t;
+
+      /**
+       * ADC/TKEY 2/3 channel pin digital input disable:
+       *
+       *   1: Disable PA12-13 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_adc2_3_ie : bit_t;
+
+      /**
+       * ADC/TKEY 4/5 channel pin digital input disable:
+       *
+       *   1: Disable PA14-15 digital input to save power consumption;
+       *   0: Enable digital input.
+       */
+      pin_adc4_5_ie : bit_t;
+    };
+
+    /** Port A interrupt enable register. */
+    reg pa_interrupt_enable(16);
+
+    /** Port B interrupt enable register. */
+    reg pb_interrupt_enable(16);
+
+    /** Port A interrupt mode configure register. */
+    reg pa_interrupt_mode(16);
+
+    /** Port B interrupt mode configure register. */
+    reg pb_interrupt_mode(16);
+
+    /** Port A interrupt flag register. */
+    reg pa_interrupt_flag(16);
+
+    /** Port B interrupt flag register. */
+    reg pb_interrupt_flag(16);
+  };
+
+  instance gpio at gpio_base : gpio_t;
+  instance gpio_port_a at gpio_port_a_base : gpio_port_t;
+  instance gpio_port_b at gpio_port_b_base : gpio_port_t;
+};
diff --git a/fdl/ch573/spi.fdl b/fdl/ch573/spi.fdl
new file mode 100644
index 0000000..855d17f
--- /dev/null
+++ b/fdl/ch573/spi.fdl
@@ -0,0 +1,158 @@
+import "ch573/common.fdl";
+
+/** Package for the SPI subsystem. */
+package ch573.spi {
+
+  location spi_base = 0x4000_4000;
+
+  using ch573.common;
+
+  type spi_t : struct {
+    /** SPI0 Control Mode Register */
+    reg ctrl_mod(8) : struct {
+      /** SPI master/slave mode select */
+      mode_slave     : bit_t;
+      /** Clear FIFO/counter/interrupt flag */
+      all_clear      : bit_t;
+      /** 2-wire/3-wire SPI mode select in slave mode */
+      wire_2_mod     : bit_t;
+      union {
+        /** Clock idle mode select in master mode */
+        mst_sck_mod  : bit_t;
+        /** First byte command mode select in slave mode */
+        slv_cmd_mod  : bit_t;
+      };
+      /** FIFO direction setting bit */
+      fifo_dir       : bit_t;
+      /** SCK output enable bit */
+      sck_oe         : bit_t;
+      /** MOSI output enable bit */
+      mosi_oe        : bit_t;
+      /** MISO output enable bit */
+      miso_oe        : bit_t;
+    };
+
+    /** SPI0 Control Configuration Register */
+    reg ctrl_cfg(8) : struct {
+      /** DMA function enable bit */
+      dma_enable     : bit_t;
+      reserved(1);
+      /** DMA address loop enable bit */
+      dma_loop       : bit_t;
+      reserved(1);
+      /** Auto-clear RB_SPI_IF_BYTE_END when accessing BUFFER/FIFO */
+      auto_if        : bit_t;
+      /** SPI data bit sequence selection */
+      bit_order      : bit_t;
+      /** Input delay enable in master mode */
+      mst_dly_en     : bit_t;
+      reserved(1);
+    };
+
+    /** SPI0 Interrupt Enable Register */
+    reg inter_en(8) : struct {
+      /** All byte transmission completion interrupt enable bit */
+      ie_cnt_end     : bit_t;
+      /** Single byte transmission completion interrupt enable bit */
+      ie_byte_end    : bit_t;
+      /** More than half FIFO used interrupt enable bit */
+      ie_fifo_hf     : bit_t;
+      /** DMA end interrupt enable bit */
+      ie_dma_end     : bit_t;
+      /** FIFO overflow interrupt enable bit */
+      ie_fifo_ov     : bit_t;
+      reserved(2);
+      /** Enable receiving the first byte interrupt in slave mode */
+      ie_fst_byte    : bit_t;
+    };
+
+    assert_pos(0x03);
+    union {
+      /** SPI0 Clock Divider Register */
+      reg clock_div(8);
+      /** SPI0 Preset data register in slave mode. */
+      reg slave_pre(8);
+    };
+
+    assert_pos(0x04);
+    /** SPI0 Data Buffer Register */
+    reg data_buf(8);
+
+    assert_pos(0x05);
+    /** SPI0 Status Register */
+    reg status(8) : struct {
+      reserved(4);
+      /** Command receive completion in slave mode */
+      slv_cmd_act    : bit_t;
+      /** FIFO ready status */
+      fifo_ready     : bit_t;
+      /** First loading status after chip select in slave mode */
+      slv_cs_load    : bit_t;
+      /** Chip select status in slave mode */
+      slv_select     : bit_t;
+    };
+
+    assert_pos(0x06);
+    /** SPI0 Interrupt Flag Register */
+    reg int_flag(8) : struct {
+      /** All byte transmission completion flag */
+      if_cnt_end     : bit_t;
+      /** Single byte transmission completion flag */
+      if_byte_end    : bit_t;
+      /** More than half FIFO used flag */
+      if_fifo_hf     : bit_t;
+      /** DMA completion flag */
+      if_dma_end     : bit_t;
+      /** FIFO overflow flag */
+      if_fifo_ov     : bit_t;
+      reserved(1);
+      /** SPI idle status */
+      free           : bit_t;
+      /** First byte received flag in slave mode */
+      if_fst_byte    : bit_t;
+    };
+
+    assert_pos(0x07);
+    /** SPI0 FIFO Count Register */
+    reg fifo_count(8);
+
+    skip_to(0x0C);
+    /** SPI0 Total Transmission Length Register */
+    reg total_count(16);
+
+    skip_to(0x10);
+    reg fifo(8);
+    reserved(16);
+
+    assert_pos(0x13);
+    reg fifo_count_1(8);
+
+    assert_pos(0x14);
+    /** SPI0 DMA Buffer Current Address */
+    reg (16) : struct {
+      /** DMA buffer current address (lower 14 bits valid) */
+      dma_now        : (14);
+      reserved(2);
+    };
+    reserved(16);
+
+    assert_pos(0x18);
+    /** SPI0 DMA Buffer Start Address */
+    reg (16) : struct {
+      /** DMA buffer start address (lower 14 bits valid) */
+      dma_beg        : (14);
+      reserved(2);
+    };
+    reserved(16);
+
+    assert_pos(0x1C);
+    /** SPI0 DMA Buffer End Address */
+    reg (16) : struct {
+      /** DMA buffer end address (lower 14 bits valid) */
+      dma_end        : (14);
+      reserved(2);
+    };
+  };
+
+  instance spi0 at spi_base : spi_t;
+};
diff --git a/fdl/ch573/uart.fdl b/fdl/ch573/uart.fdl
new file mode 100644
index 0000000..bc2df2d
--- /dev/null
+++ b/fdl/ch573/uart.fdl
@@ -0,0 +1,157 @@
+import "ch573/common.fdl";
+
+/** Package for the UART subsystem. */
+package ch573.uart {
+
+  location uart0_base = 0x4000_3000;
+  location uart1_base = 0x4000_3400;
+  location uart2_base = 0x4000_3800;
+  location uart3_base = 0x4000_3C00;
+
+  using ch573.common;
+
+  type uart_t : struct {
+    /** MODEM Control Register */
+    reg mcr(8) : struct {
+      /** DTR signal output level control (UART0 only) */
+      dtr       : bit_t;
+      /** RTS signal output level control (UART0 only) */
+      rts       : bit_t;
+      /** User-defined MODEM control bit (UART0 only) */
+      out1      : bit_t;
+      union {
+        /** UART interrupt request output control */
+        out2      : bit_t;
+        int_oe    : bit_t;
+      };
+      /** Internal loop-back test mode (UART0 only) */
+      loop      : bit_t;
+      /** Automatic CTS and RTS hardware flow control (UART0 only) */
+      au_flow   : bit_t;
+      /** DTR pin output is in transmission (UART0 only) */
+      tnow      : bit_t;
+      /** Half-duplex mode control (UART0 only) */
+      half      : bit_t;
+    };
+
+    /** Interrupt Enable Register */
+    reg ier(8) : struct {
+      /** Receive data interrupt enable */
+      recv_rdy  : bit_t;
+      /** Transmit hold register empty interrupt enable */
+      thr_empty : bit_t;
+      /** Receive line status interrupt enable */
+      line_stat : bit_t;
+      /** Modem status change interrupt enable (UART0 only) */
+      modem_chg : bit_t;
+      /** DTR output enable (UART0 only) */
+      dtr_en    : bit_t;
+      /** RTS output enable (UART0 only) */
+      rts_en    : bit_t;
+      /** TXD output enable */
+      txd_en    : bit_t;
+      /** Software reset control */
+      reset     : bit_t;
+    };
+
+    /** FIFO Control Register */
+    reg fcr(8) : struct {
+      /** FIFO enable */
+      fifo_en   : bit_t;
+      /** Clear receiver FIFO */
+      rx_fifo_clr : bit_t;
+      /** Clear transmitter FIFO */
+      tx_fifo_clr : bit_t;
+      reserved(3);
+      /** FIFO trigger level select */
+      fifo_trig : (2);
+    };
+
+    /** Line Control Register */
+    reg lcr(8) : struct {
+      /** UART word size (5-8 bits) */
+      word_sz   : (2);
+      /** Stop bit setting */
+      stop_bit  : bit_t;
+      /** Parity bit enable */
+      par_en    : bit_t;
+      /** Parity bit format */
+      par_mod   : (2);
+      /** Generate break line interval */
+      break_en  : bit_t;
+      /** Divisor latch access enable */
+      dlab      : bit_t;
+    };
+
+    /** Interrupt Identification Register */
+    reg iir(8) : struct {
+      union {
+        /** No interrupt status */
+        struct {
+          no_int    : bit_t;
+          reserved(3);
+        };
+        /** Interrupt flag mask */
+        int_mask  : (4);
+      };
+      reserved(2);
+      /** FIFO enable status */
+      fifo_id   : (2);
+    };
+
+    /** Line Status Register */
+    reg lsr(8) : struct {
+      /** Data ready */
+      data_rdy  : bit_t;
+      /** Overrun error */
+      over_err  : bit_t;
+      /** Parity error */
+      par_err   : bit_t;
+      /** Framing error */
+      frame_err : bit_t;
+      /** Break interrupt */
+      break_int : bit_t;
+      /** Transmitter holding register empty */
+      thr_empty : bit_t;
+      /** Transmitter empty */
+      tx_empty  : bit_t;
+      /** FIFO data error */
+      fifo_err  : bit_t;
+    };
+
+    skip_to(0x08);
+    union {
+      /** Transmit Hold Register. */
+      reg thr(8);
+      /** Receive Buffer Register. */
+      reg rbr(8);
+    };
+    reserved(8);
+
+    assert_pos(0x0A);
+    /** Receive FIFO Count Register */
+    reg rfc(8);
+
+    assert_pos(0x0B);
+    /** Transmit FIFO Count Register */
+    reg tfc(8);
+
+    assert_pos(0x0C);
+    /** Baud Rate Divisor Latch */
+    reg dl(16);
+
+    assert_pos(0x0E);
+    /** Prescaler Divisor Register */
+    reg div(8);
+
+    assert_pos(0x0F);
+    /** Slave Address Register (UART0 only) */
+    reg adr(8);
+  };
+
+  instance uart0 at uart0_base : uart_t;
+  instance uart1 at uart1_base : uart_t;
+  instance uart2 at uart2_base : uart_t;
+  instance uart3 at uart3_base : uart_t;
+};
+